xref: /openbmc/qemu/target/ppc/cpu.h (revision 073d9f2c) 
1 /*
2  *  PowerPC emulation cpu definitions for qemu.
3  *
4  *  Copyright (c) 2003-2007 Jocelyn Mayer
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef PPC_CPU_H
21 #define PPC_CPU_H
22 
23 #include "qemu-common.h"
24 #include "qemu/int128.h"
25 
26 //#define PPC_EMULATE_32BITS_HYPV
27 
28 #if defined (TARGET_PPC64)
29 /* PowerPC 64 definitions */
30 #define TARGET_LONG_BITS 64
31 #define TARGET_PAGE_BITS 12
32 
33 #define TCG_GUEST_DEFAULT_MO 0
34 
35 /* Note that the official physical address space bits is 62-M where M
36    is implementation dependent.  I've not looked up M for the set of
37    cpus we emulate at the system level.  */
38 #define TARGET_PHYS_ADDR_SPACE_BITS 62
39 
40 /* Note that the PPC environment architecture talks about 80 bit virtual
41    addresses, with segmentation.  Obviously that's not all visible to a
42    single process, which is all we're concerned with here.  */
43 #ifdef TARGET_ABI32
44 # define TARGET_VIRT_ADDR_SPACE_BITS 32
45 #else
46 # define TARGET_VIRT_ADDR_SPACE_BITS 64
47 #endif
48 
49 #define TARGET_PAGE_BITS_64K 16
50 #define TARGET_PAGE_BITS_16M 24
51 
52 #else /* defined (TARGET_PPC64) */
53 /* PowerPC 32 definitions */
54 #define TARGET_LONG_BITS 32
55 #define TARGET_PAGE_BITS 12
56 
57 #define TARGET_PHYS_ADDR_SPACE_BITS 36
58 #define TARGET_VIRT_ADDR_SPACE_BITS 32
59 
60 #endif /* defined (TARGET_PPC64) */
61 
62 #define CPUArchState struct CPUPPCState
63 
64 #include "exec/cpu-defs.h"
65 #include "cpu-qom.h"
66 
67 #if defined (TARGET_PPC64)
68 #define PPC_ELF_MACHINE     EM_PPC64
69 #else
70 #define PPC_ELF_MACHINE     EM_PPC
71 #endif
72 
73 #define PPC_BIT(bit)            (0x8000000000000000ULL >> (bit))
74 #define PPC_BIT32(bit)          (0x80000000 >> (bit))
75 #define PPC_BIT8(bit)           (0x80 >> (bit))
76 #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
77 #define PPC_BITMASK32(bs, be)   ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
78                                  PPC_BIT32(bs))
79 #define PPC_BITMASK8(bs, be)    ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
80 
81 /*****************************************************************************/
82 /* Exception vectors definitions                                             */
83 enum {
84     POWERPC_EXCP_NONE    = -1,
85     /* The 64 first entries are used by the PowerPC embedded specification   */
86     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
87     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
88     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
89     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
90     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
91     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
92     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
93     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
94     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
95     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
96     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
97     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
98     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
99     POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
100     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
101     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
102     /* Vectors 16 to 31 are reserved                                         */
103     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
104     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
105     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
106     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
107     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
108     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
109     POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */
110     POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/
111     POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */
112     /* Vectors 42 to 63 are reserved                                         */
113     /* Exceptions defined in the PowerPC server specification                */
114     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
115     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
116     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
117     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
118     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
119     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
120     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
121     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
122     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
123     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
124     /* 40x specific exceptions                                               */
125     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
126     /* 601 specific exceptions                                               */
127     POWERPC_EXCP_IO       = 75, /* IO error exception                        */
128     POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
129     /* 602 specific exceptions                                               */
130     POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
131     /* 602/603 specific exceptions                                           */
132     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
133     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
134     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
135     /* Exceptions available on most PowerPC                                  */
136     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
137     POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
138     POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
139     POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
140     POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
141     /* 7xx/74xx specific exceptions                                          */
142     POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
143     /* 74xx specific exceptions                                              */
144     POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
145     /* 970FX specific exceptions                                             */
146     POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
147     POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
148     /* Freescale embedded cores specific exceptions                          */
149     POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
150     POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
151     POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
152     POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
153     /* VSX Unavailable (Power ISA 2.06 and later)                            */
154     POWERPC_EXCP_VSXU     = 94, /* VSX Unavailable                           */
155     POWERPC_EXCP_FU       = 95, /* Facility Unavailable                      */
156     /* Additional ISA 2.06 and later server exceptions                       */
157     POWERPC_EXCP_HV_EMU   = 96, /* HV emulation assistance                   */
158     POWERPC_EXCP_HV_MAINT = 97, /* HMI                                       */
159     POWERPC_EXCP_HV_FU    = 98, /* Hypervisor Facility unavailable           */
160     /* Server doorbell variants */
161     POWERPC_EXCP_SDOOR    = 99,
162     POWERPC_EXCP_SDOOR_HV = 100,
163     /* EOL                                                                   */
164     POWERPC_EXCP_NB       = 101,
165     /* QEMU exceptions: used internally during code translation              */
166     POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
167     POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
168     /* QEMU exceptions: special cases we want to stop translation            */
169     POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
170     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
171 };
172 
173 /* Exceptions error codes                                                    */
174 enum {
175     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
176     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
177     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
178     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
179     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
180     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
181     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
182     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
183     /* FP exceptions                                                         */
184     POWERPC_EXCP_FP            = 0x10,
185     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
186     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
187     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
188     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
189     POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
190     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
191     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
192     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
193     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
194     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
195     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
196     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
197     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
198     /* Invalid instruction                                                   */
199     POWERPC_EXCP_INVAL         = 0x20,
200     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
201     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
202     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
203     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
204     /* Privileged instruction                                                */
205     POWERPC_EXCP_PRIV          = 0x30,
206     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
207     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
208     /* Trap                                                                  */
209     POWERPC_EXCP_TRAP          = 0x40,
210 };
211 
212 #define PPC_INPUT(env) (env->bus_model)
213 
214 /*****************************************************************************/
215 typedef struct opc_handler_t opc_handler_t;
216 
217 /*****************************************************************************/
218 /* Types used to describe some PowerPC registers etc. */
219 typedef struct DisasContext DisasContext;
220 typedef struct ppc_spr_t ppc_spr_t;
221 typedef union ppc_tlb_t ppc_tlb_t;
222 typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
223 
224 /* SPR access micro-ops generations callbacks */
225 struct ppc_spr_t {
226     void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
227     void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
228 #if !defined(CONFIG_USER_ONLY)
229     void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
230     void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
231     void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
232     void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
233 #endif
234     const char *name;
235     target_ulong default_value;
236 #ifdef CONFIG_KVM
237     /* We (ab)use the fact that all the SPRs will have ids for the
238      * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
239      * don't sync this */
240     uint64_t one_reg_id;
241 #endif
242 };
243 
244 /* VSX/Altivec registers (128 bits) */
245 typedef union _ppc_vsr_t {
246     uint8_t u8[16];
247     uint16_t u16[8];
248     uint32_t u32[4];
249     uint64_t u64[2];
250     int8_t s8[16];
251     int16_t s16[8];
252     int32_t s32[4];
253     int64_t s64[2];
254     float32 f32[4];
255     float64 f64[2];
256     float128 f128;
257 #ifdef CONFIG_INT128
258     __uint128_t u128;
259 #endif
260     Int128  s128;
261 } ppc_vsr_t;
262 
263 typedef ppc_vsr_t ppc_avr_t;
264 
265 #if !defined(CONFIG_USER_ONLY)
266 /* Software TLB cache */
267 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
268 struct ppc6xx_tlb_t {
269     target_ulong pte0;
270     target_ulong pte1;
271     target_ulong EPN;
272 };
273 
274 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
275 struct ppcemb_tlb_t {
276     uint64_t RPN;
277     target_ulong EPN;
278     target_ulong PID;
279     target_ulong size;
280     uint32_t prot;
281     uint32_t attr; /* Storage attributes */
282 };
283 
284 typedef struct ppcmas_tlb_t {
285      uint32_t mas8;
286      uint32_t mas1;
287      uint64_t mas2;
288      uint64_t mas7_3;
289 } ppcmas_tlb_t;
290 
291 union ppc_tlb_t {
292     ppc6xx_tlb_t *tlb6;
293     ppcemb_tlb_t *tlbe;
294     ppcmas_tlb_t *tlbm;
295 };
296 
297 /* possible TLB variants */
298 #define TLB_NONE               0
299 #define TLB_6XX                1
300 #define TLB_EMB                2
301 #define TLB_MAS                3
302 #endif
303 
304 typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
305 
306 typedef struct ppc_slb_t ppc_slb_t;
307 struct ppc_slb_t {
308     uint64_t esid;
309     uint64_t vsid;
310     const PPCHash64SegmentPageSizes *sps;
311 };
312 
313 #define MAX_SLB_ENTRIES         64
314 #define SEGMENT_SHIFT_256M      28
315 #define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))
316 
317 #define SEGMENT_SHIFT_1T        40
318 #define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))
319 
320 
321 /*****************************************************************************/
322 /* Machine state register bits definition                                    */
323 #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
324 #define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
325 #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
326 #define MSR_SHV  60 /* hypervisor state                               hflags */
327 #define MSR_TS0  34 /* Transactional state, 2 bits (Book3s)                  */
328 #define MSR_TS1  33
329 #define MSR_TM   32 /* Transactional Memory Available (Book3s)               */
330 #define MSR_CM   31 /* Computation mode for BookE                     hflags */
331 #define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
332 #define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */
333 #define MSR_GS   28 /* guest state for BookE                                 */
334 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
335 #define MSR_VR   25 /* altivec available                            x hflags */
336 #define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
337 #define MSR_AP   23 /* Access privilege state on 602                  hflags */
338 #define MSR_VSX  23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
339 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
340 #define MSR_KEY  19 /* key bit on 603e                                       */
341 #define MSR_POW  18 /* Power management                                      */
342 #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
343 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
344 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
345 #define MSR_EE   15 /* External interrupt enable                             */
346 #define MSR_PR   14 /* Problem state                                  hflags */
347 #define MSR_FP   13 /* Floating point available                       hflags */
348 #define MSR_ME   12 /* Machine check interrupt enable                        */
349 #define MSR_FE0  11 /* Floating point exception mode 0                hflags */
350 #define MSR_SE   10 /* Single-step trace enable                     x hflags */
351 #define MSR_DWE  10 /* Debug wait enable on 405                     x        */
352 #define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
353 #define MSR_BE   9  /* Branch trace enable                          x hflags */
354 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
355 #define MSR_FE1  8  /* Floating point exception mode 1                hflags */
356 #define MSR_AL   7  /* AL bit on POWER                                       */
357 #define MSR_EP   6  /* Exception prefix on 601                               */
358 #define MSR_IR   5  /* Instruction relocate                                  */
359 #define MSR_DR   4  /* Data relocate                                         */
360 #define MSR_IS   5  /* Instruction address space (BookE)                     */
361 #define MSR_DS   4  /* Data address space (BookE)                            */
362 #define MSR_PE   3  /* Protection enable on 403                              */
363 #define MSR_PX   2  /* Protection exclusive on 403                  x        */
364 #define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
365 #define MSR_RI   1  /* Recoverable interrupt                        1        */
366 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
367 
368 /* LPCR bits */
369 #define LPCR_VPM0         PPC_BIT(0)
370 #define LPCR_VPM1         PPC_BIT(1)
371 #define LPCR_ISL          PPC_BIT(2)
372 #define LPCR_KBV          PPC_BIT(3)
373 #define LPCR_DPFD_SHIFT   (63 - 11)
374 #define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
375 #define LPCR_VRMASD_SHIFT (63 - 16)
376 #define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
377 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
378 #define LPCR_PECE_U_SHIFT (63 - 19)
379 #define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
380 #define LPCR_HVEE         PPC_BIT(17) /* Hypervisor Virt Exit Enable */
381 #define LPCR_RMLS_SHIFT   (63 - 37)
382 #define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
383 #define LPCR_ILE          PPC_BIT(38)
384 #define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt location */
385 #define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
386 #define LPCR_UPRT         PPC_BIT(41) /* Use Process Table */
387 #define LPCR_EVIRT        PPC_BIT(42) /* Enhanced Virtualisation */
388 #define LPCR_ONL          PPC_BIT(45)
389 #define LPCR_LD           PPC_BIT(46) /* Large Decrementer */
390 #define LPCR_P7_PECE0     PPC_BIT(49)
391 #define LPCR_P7_PECE1     PPC_BIT(50)
392 #define LPCR_P7_PECE2     PPC_BIT(51)
393 #define LPCR_P8_PECE0     PPC_BIT(47)
394 #define LPCR_P8_PECE1     PPC_BIT(48)
395 #define LPCR_P8_PECE2     PPC_BIT(49)
396 #define LPCR_P8_PECE3     PPC_BIT(50)
397 #define LPCR_P8_PECE4     PPC_BIT(51)
398 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
399 #define LPCR_PECE_L_SHIFT (63 - 51)
400 #define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
401 #define LPCR_PDEE         PPC_BIT(47) /* Privileged Doorbell Exit EN */
402 #define LPCR_HDEE         PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
403 #define LPCR_EEE          PPC_BIT(49) /* External Exit Enable        */
404 #define LPCR_DEE          PPC_BIT(50) /* Decrementer Exit Enable     */
405 #define LPCR_OEE          PPC_BIT(51) /* Other Exit Enable           */
406 #define LPCR_MER          PPC_BIT(52)
407 #define LPCR_GTSE         PPC_BIT(53) /* Guest Translation Shootdown */
408 #define LPCR_TC           PPC_BIT(54)
409 #define LPCR_HEIC         PPC_BIT(59) /* HV Extern Interrupt Control */
410 #define LPCR_LPES0        PPC_BIT(60)
411 #define LPCR_LPES1        PPC_BIT(61)
412 #define LPCR_RMI          PPC_BIT(62)
413 #define LPCR_HVICE        PPC_BIT(62) /* HV Virtualisation Int Enable */
414 #define LPCR_HDICE        PPC_BIT(63)
415 
416 #define msr_sf   ((env->msr >> MSR_SF)   & 1)
417 #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
418 #define msr_shv  ((env->msr >> MSR_SHV)  & 1)
419 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
420 #define msr_icm  ((env->msr >> MSR_ICM)  & 1)
421 #define msr_thv  ((env->msr >> MSR_THV)  & 1)
422 #define msr_gs   ((env->msr >> MSR_GS)   & 1)
423 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
424 #define msr_vr   ((env->msr >> MSR_VR)   & 1)
425 #define msr_spe  ((env->msr >> MSR_SPE)  & 1)
426 #define msr_ap   ((env->msr >> MSR_AP)   & 1)
427 #define msr_vsx  ((env->msr >> MSR_VSX)  & 1)
428 #define msr_sa   ((env->msr >> MSR_SA)   & 1)
429 #define msr_key  ((env->msr >> MSR_KEY)  & 1)
430 #define msr_pow  ((env->msr >> MSR_POW)  & 1)
431 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
432 #define msr_ce   ((env->msr >> MSR_CE)   & 1)
433 #define msr_ile  ((env->msr >> MSR_ILE)  & 1)
434 #define msr_ee   ((env->msr >> MSR_EE)   & 1)
435 #define msr_pr   ((env->msr >> MSR_PR)   & 1)
436 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
437 #define msr_me   ((env->msr >> MSR_ME)   & 1)
438 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
439 #define msr_se   ((env->msr >> MSR_SE)   & 1)
440 #define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
441 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
442 #define msr_be   ((env->msr >> MSR_BE)   & 1)
443 #define msr_de   ((env->msr >> MSR_DE)   & 1)
444 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
445 #define msr_al   ((env->msr >> MSR_AL)   & 1)
446 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
447 #define msr_ir   ((env->msr >> MSR_IR)   & 1)
448 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
449 #define msr_is   ((env->msr >> MSR_IS)   & 1)
450 #define msr_ds   ((env->msr >> MSR_DS)   & 1)
451 #define msr_pe   ((env->msr >> MSR_PE)   & 1)
452 #define msr_px   ((env->msr >> MSR_PX)   & 1)
453 #define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
454 #define msr_ri   ((env->msr >> MSR_RI)   & 1)
455 #define msr_le   ((env->msr >> MSR_LE)   & 1)
456 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
457 #define msr_tm   ((env->msr >> MSR_TM)   & 1)
458 
459 #define DBCR0_ICMP (1 << 27)
460 #define DBCR0_BRT (1 << 26)
461 #define DBSR_ICMP (1 << 27)
462 #define DBSR_BRT (1 << 26)
463 
464 /* Hypervisor bit is more specific */
465 #if defined(TARGET_PPC64)
466 #define MSR_HVB (1ULL << MSR_SHV)
467 #define msr_hv  msr_shv
468 #else
469 #if defined(PPC_EMULATE_32BITS_HYPV)
470 #define MSR_HVB (1ULL << MSR_THV)
471 #define msr_hv  msr_thv
472 #else
473 #define MSR_HVB (0ULL)
474 #define msr_hv  (0)
475 #endif
476 #endif
477 
478 /* DSISR */
479 #define DSISR_NOPTE              0x40000000
480 /* Not permitted by access authority of encoded access authority */
481 #define DSISR_PROTFAULT          0x08000000
482 #define DSISR_ISSTORE            0x02000000
483 /* Not permitted by virtual page class key protection */
484 #define DSISR_AMR                0x00200000
485 /* Unsupported Radix Tree Configuration */
486 #define DSISR_R_BADCONFIG        0x00080000
487 
488 /* SRR1 error code fields */
489 
490 #define SRR1_NOPTE               DSISR_NOPTE
491 /* Not permitted due to no-execute or guard bit set */
492 #define SRR1_NOEXEC_GUARD        0x10000000
493 #define SRR1_PROTFAULT           DSISR_PROTFAULT
494 #define SRR1_IAMR                DSISR_AMR
495 
496 /* Facility Status and Control (FSCR) bits */
497 #define FSCR_EBB        (63 - 56) /* Event-Based Branch Facility */
498 #define FSCR_TAR        (63 - 55) /* Target Address Register */
499 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
500 #define FSCR_IC_MASK    (0xFFULL)
501 #define FSCR_IC_POS     (63 - 7)
502 #define FSCR_IC_DSCR_SPR3   2
503 #define FSCR_IC_PMU         3
504 #define FSCR_IC_BHRB        4
505 #define FSCR_IC_TM          5
506 #define FSCR_IC_EBB         7
507 #define FSCR_IC_TAR         8
508 
509 /* Exception state register bits definition                                  */
510 #define ESR_PIL   PPC_BIT(36) /* Illegal Instruction                    */
511 #define ESR_PPR   PPC_BIT(37) /* Privileged Instruction                 */
512 #define ESR_PTR   PPC_BIT(38) /* Trap                                   */
513 #define ESR_FP    PPC_BIT(39) /* Floating-Point Operation               */
514 #define ESR_ST    PPC_BIT(40) /* Store Operation                        */
515 #define ESR_AP    PPC_BIT(44) /* Auxiliary Processor Operation          */
516 #define ESR_PUO   PPC_BIT(45) /* Unimplemented Operation                */
517 #define ESR_BO    PPC_BIT(46) /* Byte Ordering                          */
518 #define ESR_PIE   PPC_BIT(47) /* Imprecise exception                    */
519 #define ESR_DATA  PPC_BIT(53) /* Data Access (Embedded page table)      */
520 #define ESR_TLBI  PPC_BIT(54) /* TLB Ineligible (Embedded page table)   */
521 #define ESR_PT    PPC_BIT(55) /* Page Table (Embedded page table)       */
522 #define ESR_SPV   PPC_BIT(56) /* SPE/VMX operation                      */
523 #define ESR_EPID  PPC_BIT(57) /* External Process ID operation          */
524 #define ESR_VLEMI PPC_BIT(58) /* VLE operation                          */
525 #define ESR_MIF   PPC_BIT(62) /* Misaligned instruction (VLE)           */
526 
527 /* Transaction EXception And Summary Register bits                           */
528 #define TEXASR_FAILURE_PERSISTENT                (63 - 7)
529 #define TEXASR_DISALLOWED                        (63 - 8)
530 #define TEXASR_NESTING_OVERFLOW                  (63 - 9)
531 #define TEXASR_FOOTPRINT_OVERFLOW                (63 - 10)
532 #define TEXASR_SELF_INDUCED_CONFLICT             (63 - 11)
533 #define TEXASR_NON_TRANSACTIONAL_CONFLICT        (63 - 12)
534 #define TEXASR_TRANSACTION_CONFLICT              (63 - 13)
535 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
536 #define TEXASR_IMPLEMENTATION_SPECIFIC           (63 - 15)
537 #define TEXASR_INSTRUCTION_FETCH_CONFLICT        (63 - 16)
538 #define TEXASR_ABORT                             (63 - 31)
539 #define TEXASR_SUSPENDED                         (63 - 32)
540 #define TEXASR_PRIVILEGE_HV                      (63 - 34)
541 #define TEXASR_PRIVILEGE_PR                      (63 - 35)
542 #define TEXASR_FAILURE_SUMMARY                   (63 - 36)
543 #define TEXASR_TFIAR_EXACT                       (63 - 37)
544 #define TEXASR_ROT                               (63 - 38)
545 #define TEXASR_TRANSACTION_LEVEL                 (63 - 52) /* 12 bits */
546 
547 enum {
548     POWERPC_FLAG_NONE     = 0x00000000,
549     /* Flag for MSR bit 25 signification (VRE/SPE)                           */
550     POWERPC_FLAG_SPE      = 0x00000001,
551     POWERPC_FLAG_VRE      = 0x00000002,
552     /* Flag for MSR bit 17 signification (TGPR/CE)                           */
553     POWERPC_FLAG_TGPR     = 0x00000004,
554     POWERPC_FLAG_CE       = 0x00000008,
555     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
556     POWERPC_FLAG_SE       = 0x00000010,
557     POWERPC_FLAG_DWE      = 0x00000020,
558     POWERPC_FLAG_UBLE     = 0x00000040,
559     /* Flag for MSR bit 9 signification (BE/DE)                              */
560     POWERPC_FLAG_BE       = 0x00000080,
561     POWERPC_FLAG_DE       = 0x00000100,
562     /* Flag for MSR bit 2 signification (PX/PMM)                             */
563     POWERPC_FLAG_PX       = 0x00000200,
564     POWERPC_FLAG_PMM      = 0x00000400,
565     /* Flag for special features                                             */
566     /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
567     POWERPC_FLAG_RTC_CLK  = 0x00010000,
568     POWERPC_FLAG_BUS_CLK  = 0x00020000,
569     /* Has CFAR                                                              */
570     POWERPC_FLAG_CFAR     = 0x00040000,
571     /* Has VSX                                                               */
572     POWERPC_FLAG_VSX      = 0x00080000,
573     /* Has Transaction Memory (ISA 2.07)                                     */
574     POWERPC_FLAG_TM       = 0x00100000,
575 };
576 
577 /*****************************************************************************/
578 /* Floating point status and control register                                */
579 #define FPSCR_FX     31 /* Floating-point exception summary                  */
580 #define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
581 #define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
582 #define FPSCR_OX     28 /* Floating-point overflow exception                 */
583 #define FPSCR_UX     27 /* Floating-point underflow exception                */
584 #define FPSCR_ZX     26 /* Floating-point zero divide exception              */
585 #define FPSCR_XX     25 /* Floating-point inexact exception                  */
586 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
587 #define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
588 #define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
589 #define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
590 #define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
591 #define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
592 #define FPSCR_FR     18 /* Floating-point fraction rounded                   */
593 #define FPSCR_FI     17 /* Floating-point fraction inexact                   */
594 #define FPSCR_C      16 /* Floating-point result class descriptor            */
595 #define FPSCR_FL     15 /* Floating-point less than or negative              */
596 #define FPSCR_FG     14 /* Floating-point greater than or negative           */
597 #define FPSCR_FE     13 /* Floating-point equal or zero                      */
598 #define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
599 #define FPSCR_FPCC   12 /* Floating-point condition code                     */
600 #define FPSCR_FPRF   12 /* Floating-point result flags                       */
601 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
602 #define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
603 #define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
604 #define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
605 #define FPSCR_OE     6  /* Floating-point overflow exception enable          */
606 #define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
607 #define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
608 #define FPSCR_XE     3  /* Floating-point inexact exception enable           */
609 #define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
610 #define FPSCR_RN1    1
611 #define FPSCR_RN     0  /* Floating-point rounding control                   */
612 #define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
613 #define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
614 #define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
615 #define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
616 #define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
617 #define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
618 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
619 #define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
620 #define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
621 #define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
622 #define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
623 #define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
624 #define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
625 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
626 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
627 #define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
628 #define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
629 #define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
630 #define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
631 #define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
632 #define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
633 #define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
634 #define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
635 /* Invalid operation exception summary */
636 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
637                                   (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
638                                   (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
639                                   (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
640                                   (1 << FPSCR_VXCVI)))
641 /* exception summary */
642 #define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
643 /* enabled exception summary */
644 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
645                    0x1F)
646 
647 #define FP_FX		(1ull << FPSCR_FX)
648 #define FP_FEX		(1ull << FPSCR_FEX)
649 #define FP_VX		(1ull << FPSCR_VX)
650 #define FP_OX		(1ull << FPSCR_OX)
651 #define FP_UX		(1ull << FPSCR_UX)
652 #define FP_ZX		(1ull << FPSCR_ZX)
653 #define FP_XX		(1ull << FPSCR_XX)
654 #define FP_VXSNAN	(1ull << FPSCR_VXSNAN)
655 #define FP_VXISI	(1ull << FPSCR_VXISI)
656 #define FP_VXIDI	(1ull << FPSCR_VXIDI)
657 #define FP_VXZDZ	(1ull << FPSCR_VXZDZ)
658 #define FP_VXIMZ	(1ull << FPSCR_VXIMZ)
659 #define FP_VXVC		(1ull << FPSCR_VXVC)
660 #define FP_FR		(1ull << FSPCR_FR)
661 #define FP_FI		(1ull << FPSCR_FI)
662 #define FP_C		(1ull << FPSCR_C)
663 #define FP_FL		(1ull << FPSCR_FL)
664 #define FP_FG		(1ull << FPSCR_FG)
665 #define FP_FE		(1ull << FPSCR_FE)
666 #define FP_FU		(1ull << FPSCR_FU)
667 #define FP_FPCC		(FP_FL | FP_FG | FP_FE | FP_FU)
668 #define FP_FPRF		(FP_C  | FP_FL | FP_FG | FP_FE | FP_FU)
669 #define FP_VXSOFT	(1ull << FPSCR_VXSOFT)
670 #define FP_VXSQRT	(1ull << FPSCR_VXSQRT)
671 #define FP_VXCVI	(1ull << FPSCR_VXCVI)
672 #define FP_VE		(1ull << FPSCR_VE)
673 #define FP_OE		(1ull << FPSCR_OE)
674 #define FP_UE		(1ull << FPSCR_UE)
675 #define FP_ZE		(1ull << FPSCR_ZE)
676 #define FP_XE		(1ull << FPSCR_XE)
677 #define FP_NI		(1ull << FPSCR_NI)
678 #define FP_RN1		(1ull << FPSCR_RN1)
679 #define FP_RN		(1ull << FPSCR_RN)
680 
681 /* the exception bits which can be cleared by mcrfs - includes FX */
682 #define FP_EX_CLEAR_BITS (FP_FX     | FP_OX     | FP_UX     | FP_ZX     | \
683                           FP_XX     | FP_VXSNAN | FP_VXISI  | FP_VXIDI  | \
684                           FP_VXZDZ  | FP_VXIMZ  | FP_VXVC   | FP_VXSOFT | \
685                           FP_VXSQRT | FP_VXCVI)
686 
687 /*****************************************************************************/
688 /* Vector status and control register */
689 #define VSCR_NJ		16 /* Vector non-java */
690 #define VSCR_SAT	0 /* Vector saturation */
691 #define vscr_nj		(((env->vscr) >> VSCR_NJ)	& 0x1)
692 #define vscr_sat	(((env->vscr) >> VSCR_SAT)	& 0x1)
693 
694 /*****************************************************************************/
695 /* BookE e500 MMU registers */
696 
697 #define MAS0_NV_SHIFT      0
698 #define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)
699 
700 #define MAS0_WQ_SHIFT      12
701 #define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)
702 /* Write TLB entry regardless of reservation */
703 #define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)
704 /* Write TLB entry only already in use */
705 #define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)
706 /* Clear TLB entry */
707 #define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)
708 
709 #define MAS0_HES_SHIFT     14
710 #define MAS0_HES           (1 << MAS0_HES_SHIFT)
711 
712 #define MAS0_ESEL_SHIFT    16
713 #define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)
714 
715 #define MAS0_TLBSEL_SHIFT  28
716 #define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)
717 #define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)
718 #define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)
719 #define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)
720 #define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)
721 
722 #define MAS0_ATSEL_SHIFT   31
723 #define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)
724 #define MAS0_ATSEL_TLB     0
725 #define MAS0_ATSEL_LRAT    MAS0_ATSEL
726 
727 #define MAS1_TSIZE_SHIFT   7
728 #define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
729 
730 #define MAS1_TS_SHIFT      12
731 #define MAS1_TS            (1 << MAS1_TS_SHIFT)
732 
733 #define MAS1_IND_SHIFT     13
734 #define MAS1_IND           (1 << MAS1_IND_SHIFT)
735 
736 #define MAS1_TID_SHIFT     16
737 #define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)
738 
739 #define MAS1_IPROT_SHIFT   30
740 #define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)
741 
742 #define MAS1_VALID_SHIFT   31
743 #define MAS1_VALID         0x80000000
744 
745 #define MAS2_EPN_SHIFT     12
746 #define MAS2_EPN_MASK      (~0ULL << MAS2_EPN_SHIFT)
747 
748 #define MAS2_ACM_SHIFT     6
749 #define MAS2_ACM           (1 << MAS2_ACM_SHIFT)
750 
751 #define MAS2_VLE_SHIFT     5
752 #define MAS2_VLE           (1 << MAS2_VLE_SHIFT)
753 
754 #define MAS2_W_SHIFT       4
755 #define MAS2_W             (1 << MAS2_W_SHIFT)
756 
757 #define MAS2_I_SHIFT       3
758 #define MAS2_I             (1 << MAS2_I_SHIFT)
759 
760 #define MAS2_M_SHIFT       2
761 #define MAS2_M             (1 << MAS2_M_SHIFT)
762 
763 #define MAS2_G_SHIFT       1
764 #define MAS2_G             (1 << MAS2_G_SHIFT)
765 
766 #define MAS2_E_SHIFT       0
767 #define MAS2_E             (1 << MAS2_E_SHIFT)
768 
769 #define MAS3_RPN_SHIFT     12
770 #define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)
771 
772 #define MAS3_U0                 0x00000200
773 #define MAS3_U1                 0x00000100
774 #define MAS3_U2                 0x00000080
775 #define MAS3_U3                 0x00000040
776 #define MAS3_UX                 0x00000020
777 #define MAS3_SX                 0x00000010
778 #define MAS3_UW                 0x00000008
779 #define MAS3_SW                 0x00000004
780 #define MAS3_UR                 0x00000002
781 #define MAS3_SR                 0x00000001
782 #define MAS3_SPSIZE_SHIFT       1
783 #define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)
784 
785 #define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT
786 #define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK
787 #define MAS4_TIDSELD_MASK       0x00030000
788 #define MAS4_TIDSELD_PID0       0x00000000
789 #define MAS4_TIDSELD_PID1       0x00010000
790 #define MAS4_TIDSELD_PID2       0x00020000
791 #define MAS4_TIDSELD_PIDZ       0x00030000
792 #define MAS4_INDD               0x00008000      /* Default IND */
793 #define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT
794 #define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK
795 #define MAS4_ACMD               0x00000040
796 #define MAS4_VLED               0x00000020
797 #define MAS4_WD                 0x00000010
798 #define MAS4_ID                 0x00000008
799 #define MAS4_MD                 0x00000004
800 #define MAS4_GD                 0x00000002
801 #define MAS4_ED                 0x00000001
802 #define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
803 #define MAS4_WIMGED_SHIFT       0
804 
805 #define MAS5_SGS                0x80000000
806 #define MAS5_SLPID_MASK         0x00000fff
807 
808 #define MAS6_SPID0              0x3fff0000
809 #define MAS6_SPID1              0x00007ffe
810 #define MAS6_ISIZE(x)           MAS1_TSIZE(x)
811 #define MAS6_SAS                0x00000001
812 #define MAS6_SPID               MAS6_SPID0
813 #define MAS6_SIND               0x00000002      /* Indirect page */
814 #define MAS6_SIND_SHIFT         1
815 #define MAS6_SPID_MASK          0x3fff0000
816 #define MAS6_SPID_SHIFT         16
817 #define MAS6_ISIZE_MASK         0x00000f80
818 #define MAS6_ISIZE_SHIFT        7
819 
820 #define MAS7_RPN                0xffffffff
821 
822 #define MAS8_TGS                0x80000000
823 #define MAS8_VF                 0x40000000
824 #define MAS8_TLBPID             0x00000fff
825 
826 /* Bit definitions for MMUCFG */
827 #define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
828 #define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
829 #define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
830 #define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
831 #define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
832 #define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
833 #define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
834 #define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
835 #define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
836 
837 /* Bit definitions for MMUCSR0 */
838 #define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
839 #define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
840 #define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
841 #define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
842 #define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
843                          MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
844 #define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
845 #define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
846 #define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
847 #define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
848 
849 /* TLBnCFG encoding */
850 #define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
851 #define TLBnCFG_HES             0x00002000      /* HW select supported */
852 #define TLBnCFG_AVAIL           0x00004000      /* variable page size */
853 #define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
854 #define TLBnCFG_GTWE            0x00010000      /* Guest can write */
855 #define TLBnCFG_IND             0x00020000      /* IND entries supported */
856 #define TLBnCFG_PT              0x00040000      /* Can load from page table */
857 #define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
858 #define TLBnCFG_MINSIZE_SHIFT   20
859 #define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
860 #define TLBnCFG_MAXSIZE_SHIFT   16
861 #define TLBnCFG_ASSOC           0xff000000      /* Associativity */
862 #define TLBnCFG_ASSOC_SHIFT     24
863 
864 /* TLBnPS encoding */
865 #define TLBnPS_4K               0x00000004
866 #define TLBnPS_8K               0x00000008
867 #define TLBnPS_16K              0x00000010
868 #define TLBnPS_32K              0x00000020
869 #define TLBnPS_64K              0x00000040
870 #define TLBnPS_128K             0x00000080
871 #define TLBnPS_256K             0x00000100
872 #define TLBnPS_512K             0x00000200
873 #define TLBnPS_1M               0x00000400
874 #define TLBnPS_2M               0x00000800
875 #define TLBnPS_4M               0x00001000
876 #define TLBnPS_8M               0x00002000
877 #define TLBnPS_16M              0x00004000
878 #define TLBnPS_32M              0x00008000
879 #define TLBnPS_64M              0x00010000
880 #define TLBnPS_128M             0x00020000
881 #define TLBnPS_256M             0x00040000
882 #define TLBnPS_512M             0x00080000
883 #define TLBnPS_1G               0x00100000
884 #define TLBnPS_2G               0x00200000
885 #define TLBnPS_4G               0x00400000
886 #define TLBnPS_8G               0x00800000
887 #define TLBnPS_16G              0x01000000
888 #define TLBnPS_32G              0x02000000
889 #define TLBnPS_64G              0x04000000
890 #define TLBnPS_128G             0x08000000
891 #define TLBnPS_256G             0x10000000
892 
893 /* tlbilx action encoding */
894 #define TLBILX_T_ALL                    0
895 #define TLBILX_T_TID                    1
896 #define TLBILX_T_FULLMATCH              3
897 #define TLBILX_T_CLASS0                 4
898 #define TLBILX_T_CLASS1                 5
899 #define TLBILX_T_CLASS2                 6
900 #define TLBILX_T_CLASS3                 7
901 
902 /* BookE 2.06 helper defines */
903 
904 #define BOOKE206_FLUSH_TLB0    (1 << 0)
905 #define BOOKE206_FLUSH_TLB1    (1 << 1)
906 #define BOOKE206_FLUSH_TLB2    (1 << 2)
907 #define BOOKE206_FLUSH_TLB3    (1 << 3)
908 
909 /* number of possible TLBs */
910 #define BOOKE206_MAX_TLBN      4
911 
912 #define EPID_EPID_SHIFT 0x0
913 #define EPID_EPID 0xFF
914 #define EPID_ELPID_SHIFT 0x10
915 #define EPID_ELPID 0x3F0000
916 #define EPID_EGS 0x20000000
917 #define EPID_EGS_SHIFT 29
918 #define EPID_EAS 0x40000000
919 #define EPID_EAS_SHIFT 30
920 #define EPID_EPR 0x80000000
921 #define EPID_EPR_SHIFT 31
922 /* We don't support EGS and ELPID */
923 #define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
924 
925 /*****************************************************************************/
926 /* Server and Embedded Processor Control */
927 
928 #define DBELL_TYPE_SHIFT               27
929 #define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)
930 #define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)
931 #define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)
932 #define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)
933 #define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)
934 #define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)
935 
936 #define DBELL_TYPE_DBELL_SERVER        (0x05 << DBELL_TYPE_SHIFT)
937 
938 #define DBELL_BRDCAST                  PPC_BIT(37)
939 #define DBELL_LPIDTAG_SHIFT            14
940 #define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)
941 #define DBELL_PIRTAG_MASK              0x3fff
942 
943 #define DBELL_PROCIDTAG_MASK           PPC_BITMASK(44, 63)
944 
945 #define PPC_PAGE_SIZES_MAX_SZ   8
946 
947 struct ppc_radix_page_info {
948     uint32_t count;
949     uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
950 };
951 
952 /*****************************************************************************/
953 /* The whole PowerPC CPU context */
954 
955 /* PowerPC needs eight modes for different hypervisor/supervisor/guest +
956  * real/paged mode combinations. The other two modes are for external PID
957  * load/store.
958  */
959 #define NB_MMU_MODES    10
960 #define MMU_MODE8_SUFFIX _epl
961 #define MMU_MODE9_SUFFIX _eps
962 #define PPC_TLB_EPID_LOAD 8
963 #define PPC_TLB_EPID_STORE 9
964 
965 #define PPC_CPU_OPCODES_LEN          0x40
966 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
967 
968 struct CPUPPCState {
969     /* First are the most commonly used resources
970      * during translated code execution
971      */
972     /* general purpose registers */
973     target_ulong gpr[32];
974     /* Storage for GPR MSB, used by the SPE extension */
975     target_ulong gprh[32];
976     /* LR */
977     target_ulong lr;
978     /* CTR */
979     target_ulong ctr;
980     /* condition register */
981     uint32_t crf[8];
982 #if defined(TARGET_PPC64)
983     /* CFAR */
984     target_ulong cfar;
985 #endif
986     /* XER (with SO, OV, CA split out) */
987     target_ulong xer;
988     target_ulong so;
989     target_ulong ov;
990     target_ulong ca;
991     target_ulong ov32;
992     target_ulong ca32;
993     /* Reservation address */
994     target_ulong reserve_addr;
995     /* Reservation value */
996     target_ulong reserve_val;
997     target_ulong reserve_val2;
998 
999     /* Those ones are used in supervisor mode only */
1000     /* machine state register */
1001     target_ulong msr;
1002     /* temporary general purpose registers */
1003     target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
1004 
1005     /* Floating point execution context */
1006     float_status fp_status;
1007     /* floating point status and control register */
1008     target_ulong fpscr;
1009 
1010     /* Next instruction pointer */
1011     target_ulong nip;
1012 
1013     /* High part of 128-bit helper return.  */
1014     uint64_t retxh;
1015 
1016     int access_type; /* when a memory exception occurs, the access
1017                         type is stored here */
1018 
1019     CPU_COMMON
1020 
1021     /* MMU context - only relevant for full system emulation */
1022 #if !defined(CONFIG_USER_ONLY)
1023 #if defined(TARGET_PPC64)
1024     /* PowerPC 64 SLB area */
1025     ppc_slb_t slb[MAX_SLB_ENTRIES];
1026     /* tcg TLB needs flush (deferred slb inval instruction typically) */
1027 #endif
1028     /* segment registers */
1029     target_ulong sr[32];
1030     /* BATs */
1031     uint32_t nb_BATs;
1032     target_ulong DBAT[2][8];
1033     target_ulong IBAT[2][8];
1034     /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1035     int32_t nb_tlb;      /* Total number of TLB                              */
1036     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1037     int nb_ways;     /* Number of ways in the TLB set                        */
1038     int last_way;    /* Last used way used to allocate TLB in a LRU way      */
1039     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
1040     int nb_pids;     /* Number of available PID registers                    */
1041     int tlb_type;    /* Type of TLB we're dealing with                       */
1042     ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed        */
1043     /* 403 dedicated access protection registers */
1044     target_ulong pb[4];
1045     bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */
1046     bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */
1047     uint32_t tlb_need_flush; /* Delayed flush needed */
1048 #define TLB_NEED_LOCAL_FLUSH   0x1
1049 #define TLB_NEED_GLOBAL_FLUSH  0x2
1050 #endif
1051 
1052     /* Other registers */
1053     /* Special purpose registers */
1054     target_ulong spr[1024];
1055     ppc_spr_t spr_cb[1024];
1056     /* Vector status and control register */
1057     uint32_t vscr;
1058     /* VSX registers (including FP and AVR) */
1059     ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1060     /* SPE registers */
1061     uint64_t spe_acc;
1062     uint32_t spe_fscr;
1063     /* SPE and Altivec can share a status since they will never be used
1064      * simultaneously */
1065     float_status vec_status;
1066 
1067     /* Internal devices resources */
1068     /* Time base and decrementer */
1069     ppc_tb_t *tb_env;
1070     /* Device control registers */
1071     ppc_dcr_t *dcr_env;
1072 
1073     int dcache_line_size;
1074     int icache_line_size;
1075 
1076     /* Those resources are used during exception processing */
1077     /* CPU model definition */
1078     target_ulong msr_mask;
1079     powerpc_mmu_t mmu_model;
1080     powerpc_excp_t excp_model;
1081     powerpc_input_t bus_model;
1082     int bfd_mach;
1083     uint32_t flags;
1084     uint64_t insns_flags;
1085     uint64_t insns_flags2;
1086 #if defined(TARGET_PPC64)
1087     ppc_slb_t vrma_slb;
1088     target_ulong rmls;
1089 #endif
1090 
1091     int error_code;
1092     uint32_t pending_interrupts;
1093 #if !defined(CONFIG_USER_ONLY)
1094     /* This is the IRQ controller, which is implementation dependent
1095      * and only relevant when emulating a complete machine.
1096      */
1097     uint32_t irq_input_state;
1098     void **irq_inputs;
1099     /* Exception vectors */
1100     target_ulong excp_vectors[POWERPC_EXCP_NB];
1101     target_ulong excp_prefix;
1102     target_ulong ivor_mask;
1103     target_ulong ivpr_mask;
1104     target_ulong hreset_vector;
1105     hwaddr mpic_iack;
1106     /* true when the external proxy facility mode is enabled */
1107     bool mpic_proxy;
1108     /* set when the processor has an HV mode, thus HV priv
1109      * instructions and SPRs are diallowed if MSR:HV is 0
1110      */
1111     bool has_hv_mode;
1112     /* On P7/P8, set when in PM state, we need to handle resume
1113      * in a special way (such as routing some resume causes to
1114      * 0x100), so flag this here.
1115      */
1116     bool in_pm_state;
1117 #endif
1118 
1119     /* Those resources are used only during code translation */
1120     /* opcode handlers */
1121     opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1122 
1123     /* Those resources are used only in QEMU core */
1124     target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
1125     target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1126     int immu_idx;         /* precomputed MMU index to speed up insn access */
1127     int dmmu_idx;         /* precomputed MMU index to speed up data accesses */
1128 
1129     /* Power management */
1130     int (*check_pow)(CPUPPCState *env);
1131 
1132 #if !defined(CONFIG_USER_ONLY)
1133     void *load_info;    /* Holds boot loading state.  */
1134 #endif
1135 
1136     /* booke timers */
1137 
1138     /* Specifies bit locations of the Time Base used to signal a fixed timer
1139      * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1140      *
1141      * 0 selects the least significant bit.
1142      * 63 selects the most significant bit.
1143      */
1144     uint8_t fit_period[4];
1145     uint8_t wdt_period[4];
1146 
1147     /* Transactional memory state */
1148     target_ulong tm_gpr[32];
1149     ppc_avr_t tm_vsr[64];
1150     uint64_t tm_cr;
1151     uint64_t tm_lr;
1152     uint64_t tm_ctr;
1153     uint64_t tm_fpscr;
1154     uint64_t tm_amr;
1155     uint64_t tm_ppr;
1156     uint64_t tm_vrsave;
1157     uint32_t tm_vscr;
1158     uint64_t tm_dscr;
1159     uint64_t tm_tar;
1160 };
1161 
1162 #define SET_FIT_PERIOD(a_, b_, c_, d_)          \
1163 do {                                            \
1164     env->fit_period[0] = (a_);                  \
1165     env->fit_period[1] = (b_);                  \
1166     env->fit_period[2] = (c_);                  \
1167     env->fit_period[3] = (d_);                  \
1168  } while (0)
1169 
1170 #define SET_WDT_PERIOD(a_, b_, c_, d_)          \
1171 do {                                            \
1172     env->wdt_period[0] = (a_);                  \
1173     env->wdt_period[1] = (b_);                  \
1174     env->wdt_period[2] = (c_);                  \
1175     env->wdt_period[3] = (d_);                  \
1176  } while (0)
1177 
1178 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1179 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1180 
1181 struct XiveTCTX;
1182 struct ICPState;
1183 
1184 /**
1185  * PowerPCCPU:
1186  * @env: #CPUPPCState
1187  * @vcpu_id: vCPU identifier given to KVM
1188  * @compat_pvr: Current logical PVR, zero if in "raw" mode
1189  *
1190  * A PowerPC CPU.
1191  */
1192 struct PowerPCCPU {
1193     /*< private >*/
1194     CPUState parent_obj;
1195     /*< public >*/
1196 
1197     CPUPPCState env;
1198     int vcpu_id;
1199     uint32_t compat_pvr;
1200     PPCVirtualHypervisor *vhyp;
1201     struct ICPState *icp;
1202     struct XiveTCTX *tctx;
1203     void *machine_data;
1204     int32_t node_id; /* NUMA node this CPU belongs to */
1205     PPCHash64Options *hash64_opts;
1206 
1207     /* Fields related to migration compatibility hacks */
1208     bool pre_2_8_migration;
1209     target_ulong mig_msr_mask;
1210     uint64_t mig_insns_flags;
1211     uint64_t mig_insns_flags2;
1212     uint32_t mig_nb_BATs;
1213     bool pre_2_10_migration;
1214     bool pre_3_0_migration;
1215     int32_t mig_slb_nr;
1216 };
1217 
1218 static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
1219 {
1220     return container_of(env, PowerPCCPU, env);
1221 }
1222 
1223 #define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
1224 
1225 #define ENV_OFFSET offsetof(PowerPCCPU, env)
1226 
1227 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1228 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1229 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1230 
1231 struct PPCVirtualHypervisor {
1232     Object parent;
1233 };
1234 
1235 struct PPCVirtualHypervisorClass {
1236     InterfaceClass parent;
1237     void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1238     hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1239     const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1240                                          hwaddr ptex, int n);
1241     void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1242                         const ppc_hash_pte64_t *hptes,
1243                         hwaddr ptex, int n);
1244     void (*store_hpte)(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1245                        uint64_t pte0, uint64_t pte1);
1246     uint64_t (*get_patbe)(PPCVirtualHypervisor *vhyp);
1247     target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1248 };
1249 
1250 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1251 #define PPC_VIRTUAL_HYPERVISOR(obj)                 \
1252     OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR)
1253 #define PPC_VIRTUAL_HYPERVISOR_CLASS(klass)         \
1254     OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \
1255                        TYPE_PPC_VIRTUAL_HYPERVISOR)
1256 #define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \
1257     OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \
1258                      TYPE_PPC_VIRTUAL_HYPERVISOR)
1259 
1260 void ppc_cpu_do_interrupt(CPUState *cpu);
1261 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1262 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
1263                         int flags);
1264 void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
1265                              fprintf_function cpu_fprintf, int flags);
1266 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1267 int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1268 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1269 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1270 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1271 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1272                                int cpuid, void *opaque);
1273 int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1274                                int cpuid, void *opaque);
1275 #ifndef CONFIG_USER_ONLY
1276 void ppc_cpu_do_system_reset(CPUState *cs);
1277 extern const struct VMStateDescription vmstate_ppc_cpu;
1278 #endif
1279 
1280 /*****************************************************************************/
1281 void ppc_translate_init(void);
1282 /* you can call this signal handler from your SIGBUS and SIGSEGV
1283    signal handlers to inform the virtual CPU of exceptions. non zero
1284    is returned if the signal was handled by the virtual CPU.  */
1285 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1286                             void *puc);
1287 #if defined(CONFIG_USER_ONLY)
1288 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
1289                              int mmu_idx);
1290 #endif
1291 
1292 #if !defined(CONFIG_USER_ONLY)
1293 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1294 void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
1295 #endif /* !defined(CONFIG_USER_ONLY) */
1296 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1297 
1298 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1299 
1300 /* Time-base and decrementer management */
1301 #ifndef NO_CPU_IO_DEFS
1302 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1303 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1304 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1305 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1306 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1307 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1308 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1309 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1310 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1311 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1312 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1313 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1314 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1315 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1316 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1317 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1318 #if !defined(CONFIG_USER_ONLY)
1319 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1320 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1321 target_ulong load_40x_pit (CPUPPCState *env);
1322 void store_40x_pit (CPUPPCState *env, target_ulong val);
1323 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1324 void store_40x_sler (CPUPPCState *env, uint32_t val);
1325 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1326 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1327 void ppc_tlb_invalidate_all (CPUPPCState *env);
1328 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1329 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1330 #endif
1331 #endif
1332 
1333 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1334 
1335 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1336 {
1337     uint64_t gprv;
1338 
1339     gprv = env->gpr[gprn];
1340     if (env->flags & POWERPC_FLAG_SPE) {
1341         /* If the CPU implements the SPE extension, we have to get the
1342          * high bits of the GPR from the gprh storage area
1343          */
1344         gprv &= 0xFFFFFFFFULL;
1345         gprv |= (uint64_t)env->gprh[gprn] << 32;
1346     }
1347 
1348     return gprv;
1349 }
1350 
1351 /* Device control registers */
1352 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1353 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1354 
1355 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1356 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
1357 #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
1358 
1359 #define cpu_signal_handler cpu_ppc_signal_handler
1360 #define cpu_list ppc_cpu_list
1361 
1362 /* MMU modes definitions */
1363 #define MMU_USER_IDX 0
1364 static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
1365 {
1366     return ifetch ? env->immu_idx : env->dmmu_idx;
1367 }
1368 
1369 /* Compatibility modes */
1370 #if defined(TARGET_PPC64)
1371 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1372                       uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1373 bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1374                            uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1375 
1376 void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1377 
1378 #if !defined(CONFIG_USER_ONLY)
1379 void ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1380 #endif
1381 int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1382 void ppc_compat_add_property(Object *obj, const char *name,
1383                              uint32_t *compat_pvr, const char *basedesc,
1384                              Error **errp);
1385 #endif /* defined(TARGET_PPC64) */
1386 
1387 #include "exec/cpu-all.h"
1388 
1389 /*****************************************************************************/
1390 /* CRF definitions */
1391 #define CRF_LT_BIT    3
1392 #define CRF_GT_BIT    2
1393 #define CRF_EQ_BIT    1
1394 #define CRF_SO_BIT    0
1395 #define CRF_LT        (1 << CRF_LT_BIT)
1396 #define CRF_GT        (1 << CRF_GT_BIT)
1397 #define CRF_EQ        (1 << CRF_EQ_BIT)
1398 #define CRF_SO        (1 << CRF_SO_BIT)
1399 /* For SPE extensions */
1400 #define CRF_CH        (1 << CRF_LT_BIT)
1401 #define CRF_CL        (1 << CRF_GT_BIT)
1402 #define CRF_CH_OR_CL  (1 << CRF_EQ_BIT)
1403 #define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1404 
1405 /* XER definitions */
1406 #define XER_SO  31
1407 #define XER_OV  30
1408 #define XER_CA  29
1409 #define XER_OV32  19
1410 #define XER_CA32  18
1411 #define XER_CMP  8
1412 #define XER_BC   0
1413 #define xer_so  (env->so)
1414 #define xer_ov  (env->ov)
1415 #define xer_ca  (env->ca)
1416 #define xer_ov32  (env->ov)
1417 #define xer_ca32  (env->ca)
1418 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1419 #define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
1420 
1421 /* SPR definitions */
1422 #define SPR_MQ                (0x000)
1423 #define SPR_XER               (0x001)
1424 #define SPR_601_VRTCU         (0x004)
1425 #define SPR_601_VRTCL         (0x005)
1426 #define SPR_601_UDECR         (0x006)
1427 #define SPR_LR                (0x008)
1428 #define SPR_CTR               (0x009)
1429 #define SPR_UAMR              (0x00D)
1430 #define SPR_DSCR              (0x011)
1431 #define SPR_DSISR             (0x012)
1432 #define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
1433 #define SPR_601_RTCU          (0x014)
1434 #define SPR_601_RTCL          (0x015)
1435 #define SPR_DECR              (0x016)
1436 #define SPR_SDR1              (0x019)
1437 #define SPR_SRR0              (0x01A)
1438 #define SPR_SRR1              (0x01B)
1439 #define SPR_CFAR              (0x01C)
1440 #define SPR_AMR               (0x01D)
1441 #define SPR_ACOP              (0x01F)
1442 #define SPR_BOOKE_PID         (0x030)
1443 #define SPR_BOOKS_PID         (0x030)
1444 #define SPR_BOOKE_DECAR       (0x036)
1445 #define SPR_BOOKE_CSRR0       (0x03A)
1446 #define SPR_BOOKE_CSRR1       (0x03B)
1447 #define SPR_BOOKE_DEAR        (0x03D)
1448 #define SPR_IAMR              (0x03D)
1449 #define SPR_BOOKE_ESR         (0x03E)
1450 #define SPR_BOOKE_IVPR        (0x03F)
1451 #define SPR_MPC_EIE           (0x050)
1452 #define SPR_MPC_EID           (0x051)
1453 #define SPR_MPC_NRI           (0x052)
1454 #define SPR_TFHAR             (0x080)
1455 #define SPR_TFIAR             (0x081)
1456 #define SPR_TEXASR            (0x082)
1457 #define SPR_TEXASRU           (0x083)
1458 #define SPR_UCTRL             (0x088)
1459 #define SPR_TIDR              (0x090)
1460 #define SPR_MPC_CMPA          (0x090)
1461 #define SPR_MPC_CMPB          (0x091)
1462 #define SPR_MPC_CMPC          (0x092)
1463 #define SPR_MPC_CMPD          (0x093)
1464 #define SPR_MPC_ECR           (0x094)
1465 #define SPR_MPC_DER           (0x095)
1466 #define SPR_MPC_COUNTA        (0x096)
1467 #define SPR_MPC_COUNTB        (0x097)
1468 #define SPR_CTRL              (0x098)
1469 #define SPR_MPC_CMPE          (0x098)
1470 #define SPR_MPC_CMPF          (0x099)
1471 #define SPR_FSCR              (0x099)
1472 #define SPR_MPC_CMPG          (0x09A)
1473 #define SPR_MPC_CMPH          (0x09B)
1474 #define SPR_MPC_LCTRL1        (0x09C)
1475 #define SPR_MPC_LCTRL2        (0x09D)
1476 #define SPR_UAMOR             (0x09D)
1477 #define SPR_MPC_ICTRL         (0x09E)
1478 #define SPR_MPC_BAR           (0x09F)
1479 #define SPR_PSPB              (0x09F)
1480 #define SPR_DAWR              (0x0B4)
1481 #define SPR_RPR               (0x0BA)
1482 #define SPR_CIABR             (0x0BB)
1483 #define SPR_DAWRX             (0x0BC)
1484 #define SPR_HFSCR             (0x0BE)
1485 #define SPR_VRSAVE            (0x100)
1486 #define SPR_USPRG0            (0x100)
1487 #define SPR_USPRG1            (0x101)
1488 #define SPR_USPRG2            (0x102)
1489 #define SPR_USPRG3            (0x103)
1490 #define SPR_USPRG4            (0x104)
1491 #define SPR_USPRG5            (0x105)
1492 #define SPR_USPRG6            (0x106)
1493 #define SPR_USPRG7            (0x107)
1494 #define SPR_VTBL              (0x10C)
1495 #define SPR_VTBU              (0x10D)
1496 #define SPR_SPRG0             (0x110)
1497 #define SPR_SPRG1             (0x111)
1498 #define SPR_SPRG2             (0x112)
1499 #define SPR_SPRG3             (0x113)
1500 #define SPR_SPRG4             (0x114)
1501 #define SPR_SCOMC             (0x114)
1502 #define SPR_SPRG5             (0x115)
1503 #define SPR_SCOMD             (0x115)
1504 #define SPR_SPRG6             (0x116)
1505 #define SPR_SPRG7             (0x117)
1506 #define SPR_ASR               (0x118)
1507 #define SPR_EAR               (0x11A)
1508 #define SPR_TBL               (0x11C)
1509 #define SPR_TBU               (0x11D)
1510 #define SPR_TBU40             (0x11E)
1511 #define SPR_SVR               (0x11E)
1512 #define SPR_BOOKE_PIR         (0x11E)
1513 #define SPR_PVR               (0x11F)
1514 #define SPR_HSPRG0            (0x130)
1515 #define SPR_BOOKE_DBSR        (0x130)
1516 #define SPR_HSPRG1            (0x131)
1517 #define SPR_HDSISR            (0x132)
1518 #define SPR_HDAR              (0x133)
1519 #define SPR_BOOKE_EPCR        (0x133)
1520 #define SPR_SPURR             (0x134)
1521 #define SPR_BOOKE_DBCR0       (0x134)
1522 #define SPR_IBCR              (0x135)
1523 #define SPR_PURR              (0x135)
1524 #define SPR_BOOKE_DBCR1       (0x135)
1525 #define SPR_DBCR              (0x136)
1526 #define SPR_HDEC              (0x136)
1527 #define SPR_BOOKE_DBCR2       (0x136)
1528 #define SPR_HIOR              (0x137)
1529 #define SPR_MBAR              (0x137)
1530 #define SPR_RMOR              (0x138)
1531 #define SPR_BOOKE_IAC1        (0x138)
1532 #define SPR_HRMOR             (0x139)
1533 #define SPR_BOOKE_IAC2        (0x139)
1534 #define SPR_HSRR0             (0x13A)
1535 #define SPR_BOOKE_IAC3        (0x13A)
1536 #define SPR_HSRR1             (0x13B)
1537 #define SPR_BOOKE_IAC4        (0x13B)
1538 #define SPR_BOOKE_DAC1        (0x13C)
1539 #define SPR_MMCRH             (0x13C)
1540 #define SPR_DABR2             (0x13D)
1541 #define SPR_BOOKE_DAC2        (0x13D)
1542 #define SPR_TFMR              (0x13D)
1543 #define SPR_BOOKE_DVC1        (0x13E)
1544 #define SPR_LPCR              (0x13E)
1545 #define SPR_BOOKE_DVC2        (0x13F)
1546 #define SPR_LPIDR             (0x13F)
1547 #define SPR_BOOKE_TSR         (0x150)
1548 #define SPR_HMER              (0x150)
1549 #define SPR_HMEER             (0x151)
1550 #define SPR_PCR               (0x152)
1551 #define SPR_BOOKE_LPIDR       (0x152)
1552 #define SPR_BOOKE_TCR         (0x154)
1553 #define SPR_BOOKE_TLB0PS      (0x158)
1554 #define SPR_BOOKE_TLB1PS      (0x159)
1555 #define SPR_BOOKE_TLB2PS      (0x15A)
1556 #define SPR_BOOKE_TLB3PS      (0x15B)
1557 #define SPR_AMOR              (0x15D)
1558 #define SPR_BOOKE_MAS7_MAS3   (0x174)
1559 #define SPR_BOOKE_IVOR0       (0x190)
1560 #define SPR_BOOKE_IVOR1       (0x191)
1561 #define SPR_BOOKE_IVOR2       (0x192)
1562 #define SPR_BOOKE_IVOR3       (0x193)
1563 #define SPR_BOOKE_IVOR4       (0x194)
1564 #define SPR_BOOKE_IVOR5       (0x195)
1565 #define SPR_BOOKE_IVOR6       (0x196)
1566 #define SPR_BOOKE_IVOR7       (0x197)
1567 #define SPR_BOOKE_IVOR8       (0x198)
1568 #define SPR_BOOKE_IVOR9       (0x199)
1569 #define SPR_BOOKE_IVOR10      (0x19A)
1570 #define SPR_BOOKE_IVOR11      (0x19B)
1571 #define SPR_BOOKE_IVOR12      (0x19C)
1572 #define SPR_BOOKE_IVOR13      (0x19D)
1573 #define SPR_BOOKE_IVOR14      (0x19E)
1574 #define SPR_BOOKE_IVOR15      (0x19F)
1575 #define SPR_BOOKE_IVOR38      (0x1B0)
1576 #define SPR_BOOKE_IVOR39      (0x1B1)
1577 #define SPR_BOOKE_IVOR40      (0x1B2)
1578 #define SPR_BOOKE_IVOR41      (0x1B3)
1579 #define SPR_BOOKE_IVOR42      (0x1B4)
1580 #define SPR_BOOKE_GIVOR2      (0x1B8)
1581 #define SPR_BOOKE_GIVOR3      (0x1B9)
1582 #define SPR_BOOKE_GIVOR4      (0x1BA)
1583 #define SPR_BOOKE_GIVOR8      (0x1BB)
1584 #define SPR_BOOKE_GIVOR13     (0x1BC)
1585 #define SPR_BOOKE_GIVOR14     (0x1BD)
1586 #define SPR_TIR               (0x1BE)
1587 #define SPR_PTCR              (0x1D0)
1588 #define SPR_BOOKE_SPEFSCR     (0x200)
1589 #define SPR_Exxx_BBEAR        (0x201)
1590 #define SPR_Exxx_BBTAR        (0x202)
1591 #define SPR_Exxx_L1CFG0       (0x203)
1592 #define SPR_Exxx_L1CFG1       (0x204)
1593 #define SPR_Exxx_NPIDR        (0x205)
1594 #define SPR_ATBL              (0x20E)
1595 #define SPR_ATBU              (0x20F)
1596 #define SPR_IBAT0U            (0x210)
1597 #define SPR_BOOKE_IVOR32      (0x210)
1598 #define SPR_RCPU_MI_GRA       (0x210)
1599 #define SPR_IBAT0L            (0x211)
1600 #define SPR_BOOKE_IVOR33      (0x211)
1601 #define SPR_IBAT1U            (0x212)
1602 #define SPR_BOOKE_IVOR34      (0x212)
1603 #define SPR_IBAT1L            (0x213)
1604 #define SPR_BOOKE_IVOR35      (0x213)
1605 #define SPR_IBAT2U            (0x214)
1606 #define SPR_BOOKE_IVOR36      (0x214)
1607 #define SPR_IBAT2L            (0x215)
1608 #define SPR_BOOKE_IVOR37      (0x215)
1609 #define SPR_IBAT3U            (0x216)
1610 #define SPR_IBAT3L            (0x217)
1611 #define SPR_DBAT0U            (0x218)
1612 #define SPR_RCPU_L2U_GRA      (0x218)
1613 #define SPR_DBAT0L            (0x219)
1614 #define SPR_DBAT1U            (0x21A)
1615 #define SPR_DBAT1L            (0x21B)
1616 #define SPR_DBAT2U            (0x21C)
1617 #define SPR_DBAT2L            (0x21D)
1618 #define SPR_DBAT3U            (0x21E)
1619 #define SPR_DBAT3L            (0x21F)
1620 #define SPR_IBAT4U            (0x230)
1621 #define SPR_RPCU_BBCMCR       (0x230)
1622 #define SPR_MPC_IC_CST        (0x230)
1623 #define SPR_Exxx_CTXCR        (0x230)
1624 #define SPR_IBAT4L            (0x231)
1625 #define SPR_MPC_IC_ADR        (0x231)
1626 #define SPR_Exxx_DBCR3        (0x231)
1627 #define SPR_IBAT5U            (0x232)
1628 #define SPR_MPC_IC_DAT        (0x232)
1629 #define SPR_Exxx_DBCNT        (0x232)
1630 #define SPR_IBAT5L            (0x233)
1631 #define SPR_IBAT6U            (0x234)
1632 #define SPR_IBAT6L            (0x235)
1633 #define SPR_IBAT7U            (0x236)
1634 #define SPR_IBAT7L            (0x237)
1635 #define SPR_DBAT4U            (0x238)
1636 #define SPR_RCPU_L2U_MCR      (0x238)
1637 #define SPR_MPC_DC_CST        (0x238)
1638 #define SPR_Exxx_ALTCTXCR     (0x238)
1639 #define SPR_DBAT4L            (0x239)
1640 #define SPR_MPC_DC_ADR        (0x239)
1641 #define SPR_DBAT5U            (0x23A)
1642 #define SPR_BOOKE_MCSRR0      (0x23A)
1643 #define SPR_MPC_DC_DAT        (0x23A)
1644 #define SPR_DBAT5L            (0x23B)
1645 #define SPR_BOOKE_MCSRR1      (0x23B)
1646 #define SPR_DBAT6U            (0x23C)
1647 #define SPR_BOOKE_MCSR        (0x23C)
1648 #define SPR_DBAT6L            (0x23D)
1649 #define SPR_Exxx_MCAR         (0x23D)
1650 #define SPR_DBAT7U            (0x23E)
1651 #define SPR_BOOKE_DSRR0       (0x23E)
1652 #define SPR_DBAT7L            (0x23F)
1653 #define SPR_BOOKE_DSRR1       (0x23F)
1654 #define SPR_BOOKE_SPRG8       (0x25C)
1655 #define SPR_BOOKE_SPRG9       (0x25D)
1656 #define SPR_BOOKE_MAS0        (0x270)
1657 #define SPR_BOOKE_MAS1        (0x271)
1658 #define SPR_BOOKE_MAS2        (0x272)
1659 #define SPR_BOOKE_MAS3        (0x273)
1660 #define SPR_BOOKE_MAS4        (0x274)
1661 #define SPR_BOOKE_MAS5        (0x275)
1662 #define SPR_BOOKE_MAS6        (0x276)
1663 #define SPR_BOOKE_PID1        (0x279)
1664 #define SPR_BOOKE_PID2        (0x27A)
1665 #define SPR_MPC_DPDR          (0x280)
1666 #define SPR_MPC_IMMR          (0x288)
1667 #define SPR_BOOKE_TLB0CFG     (0x2B0)
1668 #define SPR_BOOKE_TLB1CFG     (0x2B1)
1669 #define SPR_BOOKE_TLB2CFG     (0x2B2)
1670 #define SPR_BOOKE_TLB3CFG     (0x2B3)
1671 #define SPR_BOOKE_EPR         (0x2BE)
1672 #define SPR_PERF0             (0x300)
1673 #define SPR_RCPU_MI_RBA0      (0x300)
1674 #define SPR_MPC_MI_CTR        (0x300)
1675 #define SPR_POWER_USIER       (0x300)
1676 #define SPR_PERF1             (0x301)
1677 #define SPR_RCPU_MI_RBA1      (0x301)
1678 #define SPR_POWER_UMMCR2      (0x301)
1679 #define SPR_PERF2             (0x302)
1680 #define SPR_RCPU_MI_RBA2      (0x302)
1681 #define SPR_MPC_MI_AP         (0x302)
1682 #define SPR_POWER_UMMCRA      (0x302)
1683 #define SPR_PERF3             (0x303)
1684 #define SPR_RCPU_MI_RBA3      (0x303)
1685 #define SPR_MPC_MI_EPN        (0x303)
1686 #define SPR_POWER_UPMC1       (0x303)
1687 #define SPR_PERF4             (0x304)
1688 #define SPR_POWER_UPMC2       (0x304)
1689 #define SPR_PERF5             (0x305)
1690 #define SPR_MPC_MI_TWC        (0x305)
1691 #define SPR_POWER_UPMC3       (0x305)
1692 #define SPR_PERF6             (0x306)
1693 #define SPR_MPC_MI_RPN        (0x306)
1694 #define SPR_POWER_UPMC4       (0x306)
1695 #define SPR_PERF7             (0x307)
1696 #define SPR_POWER_UPMC5       (0x307)
1697 #define SPR_PERF8             (0x308)
1698 #define SPR_RCPU_L2U_RBA0     (0x308)
1699 #define SPR_MPC_MD_CTR        (0x308)
1700 #define SPR_POWER_UPMC6       (0x308)
1701 #define SPR_PERF9             (0x309)
1702 #define SPR_RCPU_L2U_RBA1     (0x309)
1703 #define SPR_MPC_MD_CASID      (0x309)
1704 #define SPR_970_UPMC7         (0X309)
1705 #define SPR_PERFA             (0x30A)
1706 #define SPR_RCPU_L2U_RBA2     (0x30A)
1707 #define SPR_MPC_MD_AP         (0x30A)
1708 #define SPR_970_UPMC8         (0X30A)
1709 #define SPR_PERFB             (0x30B)
1710 #define SPR_RCPU_L2U_RBA3     (0x30B)
1711 #define SPR_MPC_MD_EPN        (0x30B)
1712 #define SPR_POWER_UMMCR0      (0X30B)
1713 #define SPR_PERFC             (0x30C)
1714 #define SPR_MPC_MD_TWB        (0x30C)
1715 #define SPR_POWER_USIAR       (0X30C)
1716 #define SPR_PERFD             (0x30D)
1717 #define SPR_MPC_MD_TWC        (0x30D)
1718 #define SPR_POWER_USDAR       (0X30D)
1719 #define SPR_PERFE             (0x30E)
1720 #define SPR_MPC_MD_RPN        (0x30E)
1721 #define SPR_POWER_UMMCR1      (0X30E)
1722 #define SPR_PERFF             (0x30F)
1723 #define SPR_MPC_MD_TW         (0x30F)
1724 #define SPR_UPERF0            (0x310)
1725 #define SPR_POWER_SIER        (0x310)
1726 #define SPR_UPERF1            (0x311)
1727 #define SPR_POWER_MMCR2       (0x311)
1728 #define SPR_UPERF2            (0x312)
1729 #define SPR_POWER_MMCRA       (0X312)
1730 #define SPR_UPERF3            (0x313)
1731 #define SPR_POWER_PMC1        (0X313)
1732 #define SPR_UPERF4            (0x314)
1733 #define SPR_POWER_PMC2        (0X314)
1734 #define SPR_UPERF5            (0x315)
1735 #define SPR_POWER_PMC3        (0X315)
1736 #define SPR_UPERF6            (0x316)
1737 #define SPR_POWER_PMC4        (0X316)
1738 #define SPR_UPERF7            (0x317)
1739 #define SPR_POWER_PMC5        (0X317)
1740 #define SPR_UPERF8            (0x318)
1741 #define SPR_POWER_PMC6        (0X318)
1742 #define SPR_UPERF9            (0x319)
1743 #define SPR_970_PMC7          (0X319)
1744 #define SPR_UPERFA            (0x31A)
1745 #define SPR_970_PMC8          (0X31A)
1746 #define SPR_UPERFB            (0x31B)
1747 #define SPR_POWER_MMCR0       (0X31B)
1748 #define SPR_UPERFC            (0x31C)
1749 #define SPR_POWER_SIAR        (0X31C)
1750 #define SPR_UPERFD            (0x31D)
1751 #define SPR_POWER_SDAR        (0X31D)
1752 #define SPR_UPERFE            (0x31E)
1753 #define SPR_POWER_MMCR1       (0X31E)
1754 #define SPR_UPERFF            (0x31F)
1755 #define SPR_RCPU_MI_RA0       (0x320)
1756 #define SPR_MPC_MI_DBCAM      (0x320)
1757 #define SPR_BESCRS            (0x320)
1758 #define SPR_RCPU_MI_RA1       (0x321)
1759 #define SPR_MPC_MI_DBRAM0     (0x321)
1760 #define SPR_BESCRSU           (0x321)
1761 #define SPR_RCPU_MI_RA2       (0x322)
1762 #define SPR_MPC_MI_DBRAM1     (0x322)
1763 #define SPR_BESCRR            (0x322)
1764 #define SPR_RCPU_MI_RA3       (0x323)
1765 #define SPR_BESCRRU           (0x323)
1766 #define SPR_EBBHR             (0x324)
1767 #define SPR_EBBRR             (0x325)
1768 #define SPR_BESCR             (0x326)
1769 #define SPR_RCPU_L2U_RA0      (0x328)
1770 #define SPR_MPC_MD_DBCAM      (0x328)
1771 #define SPR_RCPU_L2U_RA1      (0x329)
1772 #define SPR_MPC_MD_DBRAM0     (0x329)
1773 #define SPR_RCPU_L2U_RA2      (0x32A)
1774 #define SPR_MPC_MD_DBRAM1     (0x32A)
1775 #define SPR_RCPU_L2U_RA3      (0x32B)
1776 #define SPR_TAR               (0x32F)
1777 #define SPR_IC                (0x350)
1778 #define SPR_VTB               (0x351)
1779 #define SPR_MMCRC             (0x353)
1780 #define SPR_PSSCR             (0x357)
1781 #define SPR_440_INV0          (0x370)
1782 #define SPR_440_INV1          (0x371)
1783 #define SPR_440_INV2          (0x372)
1784 #define SPR_440_INV3          (0x373)
1785 #define SPR_440_ITV0          (0x374)
1786 #define SPR_440_ITV1          (0x375)
1787 #define SPR_440_ITV2          (0x376)
1788 #define SPR_440_ITV3          (0x377)
1789 #define SPR_440_CCR1          (0x378)
1790 #define SPR_TACR              (0x378)
1791 #define SPR_TCSCR             (0x379)
1792 #define SPR_CSIGR             (0x37a)
1793 #define SPR_DCRIPR            (0x37B)
1794 #define SPR_POWER_SPMC1       (0x37C)
1795 #define SPR_POWER_SPMC2       (0x37D)
1796 #define SPR_POWER_MMCRS       (0x37E)
1797 #define SPR_WORT              (0x37F)
1798 #define SPR_PPR               (0x380)
1799 #define SPR_750_GQR0          (0x390)
1800 #define SPR_440_DNV0          (0x390)
1801 #define SPR_750_GQR1          (0x391)
1802 #define SPR_440_DNV1          (0x391)
1803 #define SPR_750_GQR2          (0x392)
1804 #define SPR_440_DNV2          (0x392)
1805 #define SPR_750_GQR3          (0x393)
1806 #define SPR_440_DNV3          (0x393)
1807 #define SPR_750_GQR4          (0x394)
1808 #define SPR_440_DTV0          (0x394)
1809 #define SPR_750_GQR5          (0x395)
1810 #define SPR_440_DTV1          (0x395)
1811 #define SPR_750_GQR6          (0x396)
1812 #define SPR_440_DTV2          (0x396)
1813 #define SPR_750_GQR7          (0x397)
1814 #define SPR_440_DTV3          (0x397)
1815 #define SPR_750_THRM4         (0x398)
1816 #define SPR_750CL_HID2        (0x398)
1817 #define SPR_440_DVLIM         (0x398)
1818 #define SPR_750_WPAR          (0x399)
1819 #define SPR_440_IVLIM         (0x399)
1820 #define SPR_TSCR              (0x399)
1821 #define SPR_750_DMAU          (0x39A)
1822 #define SPR_750_DMAL          (0x39B)
1823 #define SPR_440_RSTCFG        (0x39B)
1824 #define SPR_BOOKE_DCDBTRL     (0x39C)
1825 #define SPR_BOOKE_DCDBTRH     (0x39D)
1826 #define SPR_BOOKE_ICDBTRL     (0x39E)
1827 #define SPR_BOOKE_ICDBTRH     (0x39F)
1828 #define SPR_74XX_UMMCR2       (0x3A0)
1829 #define SPR_7XX_UPMC5         (0x3A1)
1830 #define SPR_7XX_UPMC6         (0x3A2)
1831 #define SPR_UBAMR             (0x3A7)
1832 #define SPR_7XX_UMMCR0        (0x3A8)
1833 #define SPR_7XX_UPMC1         (0x3A9)
1834 #define SPR_7XX_UPMC2         (0x3AA)
1835 #define SPR_7XX_USIAR         (0x3AB)
1836 #define SPR_7XX_UMMCR1        (0x3AC)
1837 #define SPR_7XX_UPMC3         (0x3AD)
1838 #define SPR_7XX_UPMC4         (0x3AE)
1839 #define SPR_USDA              (0x3AF)
1840 #define SPR_40x_ZPR           (0x3B0)
1841 #define SPR_BOOKE_MAS7        (0x3B0)
1842 #define SPR_74XX_MMCR2        (0x3B0)
1843 #define SPR_7XX_PMC5          (0x3B1)
1844 #define SPR_40x_PID           (0x3B1)
1845 #define SPR_7XX_PMC6          (0x3B2)
1846 #define SPR_440_MMUCR         (0x3B2)
1847 #define SPR_4xx_CCR0          (0x3B3)
1848 #define SPR_BOOKE_EPLC        (0x3B3)
1849 #define SPR_405_IAC3          (0x3B4)
1850 #define SPR_BOOKE_EPSC        (0x3B4)
1851 #define SPR_405_IAC4          (0x3B5)
1852 #define SPR_405_DVC1          (0x3B6)
1853 #define SPR_405_DVC2          (0x3B7)
1854 #define SPR_BAMR              (0x3B7)
1855 #define SPR_7XX_MMCR0         (0x3B8)
1856 #define SPR_7XX_PMC1          (0x3B9)
1857 #define SPR_40x_SGR           (0x3B9)
1858 #define SPR_7XX_PMC2          (0x3BA)
1859 #define SPR_40x_DCWR          (0x3BA)
1860 #define SPR_7XX_SIAR          (0x3BB)
1861 #define SPR_405_SLER          (0x3BB)
1862 #define SPR_7XX_MMCR1         (0x3BC)
1863 #define SPR_405_SU0R          (0x3BC)
1864 #define SPR_401_SKR           (0x3BC)
1865 #define SPR_7XX_PMC3          (0x3BD)
1866 #define SPR_405_DBCR1         (0x3BD)
1867 #define SPR_7XX_PMC4          (0x3BE)
1868 #define SPR_SDA               (0x3BF)
1869 #define SPR_403_VTBL          (0x3CC)
1870 #define SPR_403_VTBU          (0x3CD)
1871 #define SPR_DMISS             (0x3D0)
1872 #define SPR_DCMP              (0x3D1)
1873 #define SPR_HASH1             (0x3D2)
1874 #define SPR_HASH2             (0x3D3)
1875 #define SPR_BOOKE_ICDBDR      (0x3D3)
1876 #define SPR_TLBMISS           (0x3D4)
1877 #define SPR_IMISS             (0x3D4)
1878 #define SPR_40x_ESR           (0x3D4)
1879 #define SPR_PTEHI             (0x3D5)
1880 #define SPR_ICMP              (0x3D5)
1881 #define SPR_40x_DEAR          (0x3D5)
1882 #define SPR_PTELO             (0x3D6)
1883 #define SPR_RPA               (0x3D6)
1884 #define SPR_40x_EVPR          (0x3D6)
1885 #define SPR_L3PM              (0x3D7)
1886 #define SPR_403_CDBCR         (0x3D7)
1887 #define SPR_L3ITCR0           (0x3D8)
1888 #define SPR_TCR               (0x3D8)
1889 #define SPR_40x_TSR           (0x3D8)
1890 #define SPR_IBR               (0x3DA)
1891 #define SPR_40x_TCR           (0x3DA)
1892 #define SPR_ESASRR            (0x3DB)
1893 #define SPR_40x_PIT           (0x3DB)
1894 #define SPR_403_TBL           (0x3DC)
1895 #define SPR_403_TBU           (0x3DD)
1896 #define SPR_SEBR              (0x3DE)
1897 #define SPR_40x_SRR2          (0x3DE)
1898 #define SPR_SER               (0x3DF)
1899 #define SPR_40x_SRR3          (0x3DF)
1900 #define SPR_L3OHCR            (0x3E8)
1901 #define SPR_L3ITCR1           (0x3E9)
1902 #define SPR_L3ITCR2           (0x3EA)
1903 #define SPR_L3ITCR3           (0x3EB)
1904 #define SPR_HID0              (0x3F0)
1905 #define SPR_40x_DBSR          (0x3F0)
1906 #define SPR_HID1              (0x3F1)
1907 #define SPR_IABR              (0x3F2)
1908 #define SPR_40x_DBCR0         (0x3F2)
1909 #define SPR_601_HID2          (0x3F2)
1910 #define SPR_Exxx_L1CSR0       (0x3F2)
1911 #define SPR_ICTRL             (0x3F3)
1912 #define SPR_HID2              (0x3F3)
1913 #define SPR_750CL_HID4        (0x3F3)
1914 #define SPR_Exxx_L1CSR1       (0x3F3)
1915 #define SPR_440_DBDR          (0x3F3)
1916 #define SPR_LDSTDB            (0x3F4)
1917 #define SPR_750_TDCL          (0x3F4)
1918 #define SPR_40x_IAC1          (0x3F4)
1919 #define SPR_MMUCSR0           (0x3F4)
1920 #define SPR_970_HID4          (0x3F4)
1921 #define SPR_DABR              (0x3F5)
1922 #define DABR_MASK (~(target_ulong)0x7)
1923 #define SPR_Exxx_BUCSR        (0x3F5)
1924 #define SPR_40x_IAC2          (0x3F5)
1925 #define SPR_601_HID5          (0x3F5)
1926 #define SPR_40x_DAC1          (0x3F6)
1927 #define SPR_MSSCR0            (0x3F6)
1928 #define SPR_970_HID5          (0x3F6)
1929 #define SPR_MSSSR0            (0x3F7)
1930 #define SPR_MSSCR1            (0x3F7)
1931 #define SPR_DABRX             (0x3F7)
1932 #define SPR_40x_DAC2          (0x3F7)
1933 #define SPR_MMUCFG            (0x3F7)
1934 #define SPR_LDSTCR            (0x3F8)
1935 #define SPR_L2PMCR            (0x3F8)
1936 #define SPR_750FX_HID2        (0x3F8)
1937 #define SPR_Exxx_L1FINV0      (0x3F8)
1938 #define SPR_L2CR              (0x3F9)
1939 #define SPR_L3CR              (0x3FA)
1940 #define SPR_750_TDCH          (0x3FA)
1941 #define SPR_IABR2             (0x3FA)
1942 #define SPR_40x_DCCR          (0x3FA)
1943 #define SPR_ICTC              (0x3FB)
1944 #define SPR_40x_ICCR          (0x3FB)
1945 #define SPR_THRM1             (0x3FC)
1946 #define SPR_403_PBL1          (0x3FC)
1947 #define SPR_SP                (0x3FD)
1948 #define SPR_THRM2             (0x3FD)
1949 #define SPR_403_PBU1          (0x3FD)
1950 #define SPR_604_HID13         (0x3FD)
1951 #define SPR_LT                (0x3FE)
1952 #define SPR_THRM3             (0x3FE)
1953 #define SPR_RCPU_FPECR        (0x3FE)
1954 #define SPR_403_PBL2          (0x3FE)
1955 #define SPR_PIR               (0x3FF)
1956 #define SPR_403_PBU2          (0x3FF)
1957 #define SPR_601_HID15         (0x3FF)
1958 #define SPR_604_HID15         (0x3FF)
1959 #define SPR_E500_SVR          (0x3FF)
1960 
1961 /* Disable MAS Interrupt Updates for Hypervisor */
1962 #define EPCR_DMIUH            (1 << 22)
1963 /* Disable Guest TLB Management Instructions */
1964 #define EPCR_DGTMI            (1 << 23)
1965 /* Guest Interrupt Computation Mode */
1966 #define EPCR_GICM             (1 << 24)
1967 /* Interrupt Computation Mode */
1968 #define EPCR_ICM              (1 << 25)
1969 /* Disable Embedded Hypervisor Debug */
1970 #define EPCR_DUVD             (1 << 26)
1971 /* Instruction Storage Interrupt Directed to Guest State */
1972 #define EPCR_ISIGS            (1 << 27)
1973 /* Data Storage Interrupt Directed to Guest State */
1974 #define EPCR_DSIGS            (1 << 28)
1975 /* Instruction TLB Error Interrupt Directed to Guest State */
1976 #define EPCR_ITLBGS           (1 << 29)
1977 /* Data TLB Error Interrupt Directed to Guest State */
1978 #define EPCR_DTLBGS           (1 << 30)
1979 /* External Input Interrupt Directed to Guest State */
1980 #define EPCR_EXTGS            (1 << 31)
1981 
1982 #define   L1CSR0_CPE		0x00010000	/* Data Cache Parity Enable */
1983 #define   L1CSR0_CUL		0x00000400	/* (D-)Cache Unable to Lock */
1984 #define   L1CSR0_DCLFR		0x00000100	/* D-Cache Lock Flash Reset */
1985 #define   L1CSR0_DCFI		0x00000002	/* Data Cache Flash Invalidate */
1986 #define   L1CSR0_DCE		0x00000001	/* Data Cache Enable */
1987 
1988 #define   L1CSR1_CPE		0x00010000	/* Instruction Cache Parity Enable */
1989 #define   L1CSR1_ICUL		0x00000400	/* I-Cache Unable to Lock */
1990 #define   L1CSR1_ICLFR		0x00000100	/* I-Cache Lock Flash Reset */
1991 #define   L1CSR1_ICFI		0x00000002	/* Instruction Cache Flash Invalidate */
1992 #define   L1CSR1_ICE		0x00000001	/* Instruction Cache Enable */
1993 
1994 /* HID0 bits */
1995 #define HID0_DEEPNAP        (1 << 24)           /* pre-2.06 */
1996 #define HID0_DOZE           (1 << 23)           /* pre-2.06 */
1997 #define HID0_NAP            (1 << 22)           /* pre-2.06 */
1998 #define HID0_HILE           PPC_BIT(19) /* POWER8 */
1999 #define HID0_POWER9_HILE    PPC_BIT(4)
2000 
2001 /*****************************************************************************/
2002 /* PowerPC Instructions types definitions                                    */
2003 enum {
2004     PPC_NONE           = 0x0000000000000000ULL,
2005     /* PowerPC base instructions set                                         */
2006     PPC_INSNS_BASE     = 0x0000000000000001ULL,
2007     /*   integer operations instructions                                     */
2008 #define PPC_INTEGER PPC_INSNS_BASE
2009     /*   flow control instructions                                           */
2010 #define PPC_FLOW    PPC_INSNS_BASE
2011     /*   virtual memory instructions                                         */
2012 #define PPC_MEM     PPC_INSNS_BASE
2013     /*   ld/st with reservation instructions                                 */
2014 #define PPC_RES     PPC_INSNS_BASE
2015     /*   spr/msr access instructions                                         */
2016 #define PPC_MISC    PPC_INSNS_BASE
2017     /* Deprecated instruction sets                                           */
2018     /*   Original POWER instruction set                                      */
2019     PPC_POWER          = 0x0000000000000002ULL,
2020     /*   POWER2 instruction set extension                                    */
2021     PPC_POWER2         = 0x0000000000000004ULL,
2022     /*   Power RTC support                                                   */
2023     PPC_POWER_RTC      = 0x0000000000000008ULL,
2024     /*   Power-to-PowerPC bridge (601)                                       */
2025     PPC_POWER_BR       = 0x0000000000000010ULL,
2026     /* 64 bits PowerPC instruction set                                       */
2027     PPC_64B            = 0x0000000000000020ULL,
2028     /*   New 64 bits extensions (PowerPC 2.0x)                               */
2029     PPC_64BX           = 0x0000000000000040ULL,
2030     /*   64 bits hypervisor extensions                                       */
2031     PPC_64H            = 0x0000000000000080ULL,
2032     /*   New wait instruction (PowerPC 2.0x)                                 */
2033     PPC_WAIT           = 0x0000000000000100ULL,
2034     /*   Time base mftb instruction                                          */
2035     PPC_MFTB           = 0x0000000000000200ULL,
2036 
2037     /* Fixed-point unit extensions                                           */
2038     /*   PowerPC 602 specific                                                */
2039     PPC_602_SPEC       = 0x0000000000000400ULL,
2040     /*   isel instruction                                                    */
2041     PPC_ISEL           = 0x0000000000000800ULL,
2042     /*   popcntb instruction                                                 */
2043     PPC_POPCNTB        = 0x0000000000001000ULL,
2044     /*   string load / store                                                 */
2045     PPC_STRING         = 0x0000000000002000ULL,
2046     /*   real mode cache inhibited load / store                              */
2047     PPC_CILDST         = 0x0000000000004000ULL,
2048 
2049     /* Floating-point unit extensions                                        */
2050     /*   Optional floating point instructions                                */
2051     PPC_FLOAT          = 0x0000000000010000ULL,
2052     /* New floating-point extensions (PowerPC 2.0x)                          */
2053     PPC_FLOAT_EXT      = 0x0000000000020000ULL,
2054     PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
2055     PPC_FLOAT_FRES     = 0x0000000000080000ULL,
2056     PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
2057     PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2058     PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
2059     PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
2060 
2061     /* Vector/SIMD extensions                                                */
2062     /*   Altivec support                                                     */
2063     PPC_ALTIVEC        = 0x0000000001000000ULL,
2064     /*   PowerPC 2.03 SPE extension                                          */
2065     PPC_SPE            = 0x0000000002000000ULL,
2066     /*   PowerPC 2.03 SPE single-precision floating-point extension          */
2067     PPC_SPE_SINGLE     = 0x0000000004000000ULL,
2068     /*   PowerPC 2.03 SPE double-precision floating-point extension          */
2069     PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
2070 
2071     /* Optional memory control instructions                                  */
2072     PPC_MEM_TLBIA      = 0x0000000010000000ULL,
2073     PPC_MEM_TLBIE      = 0x0000000020000000ULL,
2074     PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
2075     /*   sync instruction                                                    */
2076     PPC_MEM_SYNC       = 0x0000000080000000ULL,
2077     /*   eieio instruction                                                   */
2078     PPC_MEM_EIEIO      = 0x0000000100000000ULL,
2079 
2080     /* Cache control instructions                                            */
2081     PPC_CACHE          = 0x0000000200000000ULL,
2082     /*   icbi instruction                                                    */
2083     PPC_CACHE_ICBI     = 0x0000000400000000ULL,
2084     /*   dcbz instruction                                                    */
2085     PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
2086     /*   dcba instruction                                                    */
2087     PPC_CACHE_DCBA     = 0x0000002000000000ULL,
2088     /*   Freescale cache locking instructions                                */
2089     PPC_CACHE_LOCK     = 0x0000004000000000ULL,
2090 
2091     /* MMU related extensions                                                */
2092     /*   external control instructions                                       */
2093     PPC_EXTERN         = 0x0000010000000000ULL,
2094     /*   segment register access instructions                                */
2095     PPC_SEGMENT        = 0x0000020000000000ULL,
2096     /*   PowerPC 6xx TLB management instructions                             */
2097     PPC_6xx_TLB        = 0x0000040000000000ULL,
2098     /* PowerPC 74xx TLB management instructions                              */
2099     PPC_74xx_TLB       = 0x0000080000000000ULL,
2100     /*   PowerPC 40x TLB management instructions                             */
2101     PPC_40x_TLB        = 0x0000100000000000ULL,
2102     /*   segment register access instructions for PowerPC 64 "bridge"        */
2103     PPC_SEGMENT_64B    = 0x0000200000000000ULL,
2104     /*   SLB management                                                      */
2105     PPC_SLBI           = 0x0000400000000000ULL,
2106 
2107     /* Embedded PowerPC dedicated instructions                               */
2108     PPC_WRTEE          = 0x0001000000000000ULL,
2109     /* PowerPC 40x exception model                                           */
2110     PPC_40x_EXCP       = 0x0002000000000000ULL,
2111     /* PowerPC 405 Mac instructions                                          */
2112     PPC_405_MAC        = 0x0004000000000000ULL,
2113     /* PowerPC 440 specific instructions                                     */
2114     PPC_440_SPEC       = 0x0008000000000000ULL,
2115     /* BookE (embedded) PowerPC specification                                */
2116     PPC_BOOKE          = 0x0010000000000000ULL,
2117     /* mfapidi instruction                                                   */
2118     PPC_MFAPIDI        = 0x0020000000000000ULL,
2119     /* tlbiva instruction                                                    */
2120     PPC_TLBIVA         = 0x0040000000000000ULL,
2121     /* tlbivax instruction                                                   */
2122     PPC_TLBIVAX        = 0x0080000000000000ULL,
2123     /* PowerPC 4xx dedicated instructions                                    */
2124     PPC_4xx_COMMON     = 0x0100000000000000ULL,
2125     /* PowerPC 40x ibct instructions                                         */
2126     PPC_40x_ICBT       = 0x0200000000000000ULL,
2127     /* rfmci is not implemented in all BookE PowerPC                         */
2128     PPC_RFMCI          = 0x0400000000000000ULL,
2129     /* rfdi instruction                                                      */
2130     PPC_RFDI           = 0x0800000000000000ULL,
2131     /* DCR accesses                                                          */
2132     PPC_DCR            = 0x1000000000000000ULL,
2133     /* DCR extended accesse                                                  */
2134     PPC_DCRX           = 0x2000000000000000ULL,
2135     /* user-mode DCR access, implemented in PowerPC 460                      */
2136     PPC_DCRUX          = 0x4000000000000000ULL,
2137     /* popcntw and popcntd instructions                                      */
2138     PPC_POPCNTWD       = 0x8000000000000000ULL,
2139 
2140 #define PPC_TCG_INSNS  (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2141                         | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2142                         | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2143                         | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2144                         | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2145                         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2146                         | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2147                         | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2148                         | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2149                         | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2150                         | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2151                         | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2152                         | PPC_CACHE | PPC_CACHE_ICBI \
2153                         | PPC_CACHE_DCBZ \
2154                         | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2155                         | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2156                         | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2157                         | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2158                         | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2159                         | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2160                         | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2161                         | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2162                         | PPC_POPCNTWD | PPC_CILDST)
2163 
2164     /* extended type values */
2165 
2166     /* BookE 2.06 PowerPC specification                                      */
2167     PPC2_BOOKE206      = 0x0000000000000001ULL,
2168     /* VSX (extensions to Altivec / VMX)                                     */
2169     PPC2_VSX           = 0x0000000000000002ULL,
2170     /* Decimal Floating Point (DFP)                                          */
2171     PPC2_DFP           = 0x0000000000000004ULL,
2172     /* Embedded.Processor Control                                            */
2173     PPC2_PRCNTL        = 0x0000000000000008ULL,
2174     /* Byte-reversed, indexed, double-word load and store                    */
2175     PPC2_DBRX          = 0x0000000000000010ULL,
2176     /* Book I 2.05 PowerPC specification                                     */
2177     PPC2_ISA205        = 0x0000000000000020ULL,
2178     /* VSX additions in ISA 2.07                                             */
2179     PPC2_VSX207        = 0x0000000000000040ULL,
2180     /* ISA 2.06B bpermd                                                      */
2181     PPC2_PERM_ISA206   = 0x0000000000000080ULL,
2182     /* ISA 2.06B divide extended variants                                    */
2183     PPC2_DIVE_ISA206   = 0x0000000000000100ULL,
2184     /* ISA 2.06B larx/stcx. instructions                                     */
2185     PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2186     /* ISA 2.06B floating point integer conversion                           */
2187     PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2188     /* ISA 2.06B floating point test instructions                            */
2189     PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2190     /* ISA 2.07 bctar instruction                                            */
2191     PPC2_BCTAR_ISA207  = 0x0000000000001000ULL,
2192     /* ISA 2.07 load/store quadword                                          */
2193     PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
2194     /* ISA 2.07 Altivec                                                      */
2195     PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
2196     /* PowerISA 2.07 Book3s specification                                    */
2197     PPC2_ISA207S       = 0x0000000000008000ULL,
2198     /* Double precision floating point conversion for signed integer 64      */
2199     PPC2_FP_CVT_S64    = 0x0000000000010000ULL,
2200     /* Transactional Memory (ISA 2.07, Book II)                              */
2201     PPC2_TM            = 0x0000000000020000ULL,
2202     /* Server PM instructgions (ISA 2.06, Book III)                          */
2203     PPC2_PM_ISA206     = 0x0000000000040000ULL,
2204     /* POWER ISA 3.0                                                         */
2205     PPC2_ISA300        = 0x0000000000080000ULL,
2206 
2207 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2208                         PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2209                         PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2210                         PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2211                         PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2212                         PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2213                         PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2214                         PPC2_ISA300)
2215 };
2216 
2217 /*****************************************************************************/
2218 /* Memory access type :
2219  * may be needed for precise access rights control and precise exceptions.
2220  */
2221 enum {
2222     /* 1 bit to define user level / supervisor access */
2223     ACCESS_USER  = 0x00,
2224     ACCESS_SUPER = 0x01,
2225     /* Type of instruction that generated the access */
2226     ACCESS_CODE  = 0x10, /* Code fetch access                */
2227     ACCESS_INT   = 0x20, /* Integer load/store access        */
2228     ACCESS_FLOAT = 0x30, /* floating point load/store access */
2229     ACCESS_RES   = 0x40, /* load/store with reservation      */
2230     ACCESS_EXT   = 0x50, /* external access                  */
2231     ACCESS_CACHE = 0x60, /* Cache manipulation               */
2232 };
2233 
2234 /* Hardware interruption sources:
2235  * all those exception can be raised simulteaneously
2236  */
2237 /* Input pins definitions */
2238 enum {
2239     /* 6xx bus input pins */
2240     PPC6xx_INPUT_HRESET     = 0,
2241     PPC6xx_INPUT_SRESET     = 1,
2242     PPC6xx_INPUT_CKSTP_IN   = 2,
2243     PPC6xx_INPUT_MCP        = 3,
2244     PPC6xx_INPUT_SMI        = 4,
2245     PPC6xx_INPUT_INT        = 5,
2246     PPC6xx_INPUT_TBEN       = 6,
2247     PPC6xx_INPUT_WAKEUP     = 7,
2248     PPC6xx_INPUT_NB,
2249 };
2250 
2251 enum {
2252     /* Embedded PowerPC input pins */
2253     PPCBookE_INPUT_HRESET     = 0,
2254     PPCBookE_INPUT_SRESET     = 1,
2255     PPCBookE_INPUT_CKSTP_IN   = 2,
2256     PPCBookE_INPUT_MCP        = 3,
2257     PPCBookE_INPUT_SMI        = 4,
2258     PPCBookE_INPUT_INT        = 5,
2259     PPCBookE_INPUT_CINT       = 6,
2260     PPCBookE_INPUT_NB,
2261 };
2262 
2263 enum {
2264     /* PowerPC E500 input pins */
2265     PPCE500_INPUT_RESET_CORE = 0,
2266     PPCE500_INPUT_MCK        = 1,
2267     PPCE500_INPUT_CINT       = 3,
2268     PPCE500_INPUT_INT        = 4,
2269     PPCE500_INPUT_DEBUG      = 6,
2270     PPCE500_INPUT_NB,
2271 };
2272 
2273 enum {
2274     /* PowerPC 40x input pins */
2275     PPC40x_INPUT_RESET_CORE = 0,
2276     PPC40x_INPUT_RESET_CHIP = 1,
2277     PPC40x_INPUT_RESET_SYS  = 2,
2278     PPC40x_INPUT_CINT       = 3,
2279     PPC40x_INPUT_INT        = 4,
2280     PPC40x_INPUT_HALT       = 5,
2281     PPC40x_INPUT_DEBUG      = 6,
2282     PPC40x_INPUT_NB,
2283 };
2284 
2285 enum {
2286     /* RCPU input pins */
2287     PPCRCPU_INPUT_PORESET   = 0,
2288     PPCRCPU_INPUT_HRESET    = 1,
2289     PPCRCPU_INPUT_SRESET    = 2,
2290     PPCRCPU_INPUT_IRQ0      = 3,
2291     PPCRCPU_INPUT_IRQ1      = 4,
2292     PPCRCPU_INPUT_IRQ2      = 5,
2293     PPCRCPU_INPUT_IRQ3      = 6,
2294     PPCRCPU_INPUT_IRQ4      = 7,
2295     PPCRCPU_INPUT_IRQ5      = 8,
2296     PPCRCPU_INPUT_IRQ6      = 9,
2297     PPCRCPU_INPUT_IRQ7      = 10,
2298     PPCRCPU_INPUT_NB,
2299 };
2300 
2301 #if defined(TARGET_PPC64)
2302 enum {
2303     /* PowerPC 970 input pins */
2304     PPC970_INPUT_HRESET     = 0,
2305     PPC970_INPUT_SRESET     = 1,
2306     PPC970_INPUT_CKSTP      = 2,
2307     PPC970_INPUT_TBEN       = 3,
2308     PPC970_INPUT_MCP        = 4,
2309     PPC970_INPUT_INT        = 5,
2310     PPC970_INPUT_THINT      = 6,
2311     PPC970_INPUT_NB,
2312 };
2313 
2314 enum {
2315     /* POWER7 input pins */
2316     POWER7_INPUT_INT        = 0,
2317     /* POWER7 probably has other inputs, but we don't care about them
2318      * for any existing machine.  We can wire these up when we need
2319      * them */
2320     POWER7_INPUT_NB,
2321 };
2322 #endif
2323 
2324 /* Hardware exceptions definitions */
2325 enum {
2326     /* External hardware exception sources */
2327     PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
2328     PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
2329     PPC_INTERRUPT_MCK,            /* Machine check exception              */
2330     PPC_INTERRUPT_EXT,            /* External interrupt                   */
2331     PPC_INTERRUPT_SMI,            /* System management interrupt          */
2332     PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
2333     PPC_INTERRUPT_DEBUG,          /* External debug exception             */
2334     PPC_INTERRUPT_THERM,          /* Thermal exception                    */
2335     /* Internal hardware exception sources */
2336     PPC_INTERRUPT_DECR,           /* Decrementer exception                */
2337     PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
2338     PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
2339     PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
2340     PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
2341     PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
2342     PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
2343     PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
2344     PPC_INTERRUPT_HMI,            /* Hypervisor Maintainance interrupt    */
2345     PPC_INTERRUPT_HDOORBELL,      /* Hypervisor Doorbell interrupt        */
2346 };
2347 
2348 /* Processor Compatibility mask (PCR) */
2349 enum {
2350     PCR_COMPAT_2_05     = PPC_BIT(62),
2351     PCR_COMPAT_2_06     = PPC_BIT(61),
2352     PCR_COMPAT_2_07     = PPC_BIT(60),
2353     PCR_COMPAT_3_00     = PPC_BIT(59),
2354     PCR_VEC_DIS         = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2355     PCR_VSX_DIS         = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2356     PCR_TM_DIS          = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2357 };
2358 
2359 /* HMER/HMEER */
2360 enum {
2361     HMER_MALFUNCTION_ALERT      = PPC_BIT(0),
2362     HMER_PROC_RECV_DONE         = PPC_BIT(2),
2363     HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2364     HMER_TFAC_ERROR             = PPC_BIT(4),
2365     HMER_TFMR_PARITY_ERROR      = PPC_BIT(5),
2366     HMER_XSCOM_FAIL             = PPC_BIT(8),
2367     HMER_XSCOM_DONE             = PPC_BIT(9),
2368     HMER_PROC_RECV_AGAIN        = PPC_BIT(11),
2369     HMER_WARN_RISE              = PPC_BIT(14),
2370     HMER_WARN_FALL              = PPC_BIT(15),
2371     HMER_SCOM_FIR_HMI           = PPC_BIT(16),
2372     HMER_TRIG_FIR_HMI           = PPC_BIT(17),
2373     HMER_HYP_RESOURCE_ERR       = PPC_BIT(20),
2374     HMER_XSCOM_STATUS_MASK      = PPC_BITMASK(21, 23),
2375 };
2376 
2377 /* Alternate Interrupt Location (AIL) */
2378 enum {
2379     AIL_NONE                = 0,
2380     AIL_RESERVED            = 1,
2381     AIL_0001_8000           = 2,
2382     AIL_C000_0000_0000_4000 = 3,
2383 };
2384 
2385 /*****************************************************************************/
2386 
2387 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2388 target_ulong cpu_read_xer(CPUPPCState *env);
2389 void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2390 
2391 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2392                                         target_ulong *cs_base, uint32_t *flags)
2393 {
2394     *pc = env->nip;
2395     *cs_base = 0;
2396     *flags = env->hflags;
2397 }
2398 
2399 void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2400 void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2401                                       uintptr_t raddr);
2402 void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2403                                        uint32_t error_code);
2404 void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2405                                           uint32_t error_code, uintptr_t raddr);
2406 
2407 #if !defined(CONFIG_USER_ONLY)
2408 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2409 {
2410     uintptr_t tlbml = (uintptr_t)tlbm;
2411     uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2412 
2413     return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2414 }
2415 
2416 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2417 {
2418     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2419     int r = tlbncfg & TLBnCFG_N_ENTRY;
2420     return r;
2421 }
2422 
2423 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2424 {
2425     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2426     int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2427     return r;
2428 }
2429 
2430 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2431 {
2432     int id = booke206_tlbm_id(env, tlbm);
2433     int end = 0;
2434     int i;
2435 
2436     for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2437         end += booke206_tlb_size(env, i);
2438         if (id < end) {
2439             return i;
2440         }
2441     }
2442 
2443     cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2444     return 0;
2445 }
2446 
2447 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2448 {
2449     int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2450     int tlbid = booke206_tlbm_id(env, tlb);
2451     return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2452 }
2453 
2454 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2455                                               target_ulong ea, int way)
2456 {
2457     int r;
2458     uint32_t ways = booke206_tlb_ways(env, tlbn);
2459     int ways_bits = ctz32(ways);
2460     int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2461     int i;
2462 
2463     way &= ways - 1;
2464     ea >>= MAS2_EPN_SHIFT;
2465     ea &= (1 << (tlb_bits - ways_bits)) - 1;
2466     r = (ea << ways_bits) | way;
2467 
2468     if (r >= booke206_tlb_size(env, tlbn)) {
2469         return NULL;
2470     }
2471 
2472     /* bump up to tlbn index */
2473     for (i = 0; i < tlbn; i++) {
2474         r += booke206_tlb_size(env, i);
2475     }
2476 
2477     return &env->tlb.tlbm[r];
2478 }
2479 
2480 /* returns bitmap of supported page sizes for a given TLB */
2481 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2482 {
2483     uint32_t ret = 0;
2484 
2485     if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2486         /* MAV2 */
2487         ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2488     } else {
2489         uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2490         uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2491         uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2492         int i;
2493         for (i = min; i <= max; i++) {
2494             ret |= (1 << (i << 1));
2495         }
2496     }
2497 
2498     return ret;
2499 }
2500 
2501 static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2502                                             ppcmas_tlb_t *tlb)
2503 {
2504     uint8_t i;
2505     int32_t tsize = -1;
2506 
2507     for (i = 0; i < 32; i++) {
2508         if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2509             if (tsize == -1) {
2510                 tsize = i;
2511             } else {
2512                 return;
2513             }
2514         }
2515     }
2516 
2517     /* TLBnPS unimplemented? Odd.. */
2518     assert(tsize != -1);
2519     tlb->mas1 &= ~MAS1_TSIZE_MASK;
2520     tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2521 }
2522 
2523 #endif
2524 
2525 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2526 {
2527     if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2528         return msr & (1ULL << MSR_CM);
2529     }
2530 
2531     return msr & (1ULL << MSR_SF);
2532 }
2533 
2534 /**
2535  * Check whether register rx is in the range between start and
2536  * start + nregs (as needed by the LSWX and LSWI instructions)
2537  */
2538 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2539 {
2540     return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2541            (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2542 }
2543 
2544 /* Accessors for FP, VMX and VSX registers */
2545 static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
2546 {
2547     return &env->vsr[i].u64[0];
2548 }
2549 
2550 static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2551 {
2552     return &env->vsr[i].u64[1];
2553 }
2554 
2555 static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2556 {
2557     return &env->vsr[32 + i];
2558 }
2559 
2560 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2561 
2562 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2563 #endif /* PPC_CPU_H */
2564