1 /*
2 * PowerPC CPU routines for qemu.
3 *
4 * Copyright (c) 2017 Nikunj A Dadhania, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "cpu-models.h"
23 #include "cpu-qom.h"
24 #include "exec/log.h"
25 #include "fpu/softfloat-helpers.h"
26 #include "mmu-hash64.h"
27 #include "helper_regs.h"
28 #include "sysemu/tcg.h"
29
cpu_read_xer(const CPUPPCState * env)30 target_ulong cpu_read_xer(const CPUPPCState *env)
31 {
32 if (is_isa300(env)) {
33 return env->xer | (env->so << XER_SO) |
34 (env->ov << XER_OV) | (env->ca << XER_CA) |
35 (env->ov32 << XER_OV32) | (env->ca32 << XER_CA32);
36 }
37
38 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) |
39 (env->ca << XER_CA);
40 }
41
cpu_write_xer(CPUPPCState * env,target_ulong xer)42 void cpu_write_xer(CPUPPCState *env, target_ulong xer)
43 {
44 env->so = (xer >> XER_SO) & 1;
45 env->ov = (xer >> XER_OV) & 1;
46 env->ca = (xer >> XER_CA) & 1;
47 /* write all the flags, while reading back check of isa300 */
48 env->ov32 = (xer >> XER_OV32) & 1;
49 env->ca32 = (xer >> XER_CA32) & 1;
50 env->xer = xer & ~((1ul << XER_SO) |
51 (1ul << XER_OV) | (1ul << XER_CA) |
52 (1ul << XER_OV32) | (1ul << XER_CA32));
53 }
54
ppc_store_vscr(CPUPPCState * env,uint32_t vscr)55 void ppc_store_vscr(CPUPPCState *env, uint32_t vscr)
56 {
57 env->vscr = vscr & ~(1u << VSCR_SAT);
58 /* Which bit we set is completely arbitrary, but clear the rest. */
59 env->vscr_sat.u64[0] = vscr & (1u << VSCR_SAT);
60 env->vscr_sat.u64[1] = 0;
61 set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status);
62 set_flush_inputs_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status);
63 }
64
ppc_get_vscr(CPUPPCState * env)65 uint32_t ppc_get_vscr(CPUPPCState *env)
66 {
67 uint32_t sat = (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) != 0;
68 return env->vscr | (sat << VSCR_SAT);
69 }
70
ppc_set_cr(CPUPPCState * env,uint64_t cr)71 void ppc_set_cr(CPUPPCState *env, uint64_t cr)
72 {
73 for (int i = 7; i >= 0; i--) {
74 env->crf[i] = cr & 0xf;
75 cr >>= 4;
76 }
77 }
78
ppc_get_cr(const CPUPPCState * env)79 uint64_t ppc_get_cr(const CPUPPCState *env)
80 {
81 uint64_t cr = 0;
82 for (int i = 0; i < 8; i++) {
83 cr |= (env->crf[i] & 0xf) << (4 * (7 - i));
84 }
85 return cr;
86 }
87
88 /* GDBstub can read and write MSR... */
ppc_store_msr(CPUPPCState * env,target_ulong value)89 void ppc_store_msr(CPUPPCState *env, target_ulong value)
90 {
91 hreg_store_msr(env, value, 0);
92 }
93
94 #if !defined(CONFIG_USER_ONLY)
ppc_store_lpcr(PowerPCCPU * cpu,target_ulong val)95 void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
96 {
97 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
98 CPUPPCState *env = &cpu->env;
99
100 env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
101 /* The gtse bit affects hflags */
102 hreg_compute_hflags(env);
103
104 ppc_maybe_interrupt(env);
105 }
106
107 #if defined(TARGET_PPC64)
ppc_update_ciabr(CPUPPCState * env)108 void ppc_update_ciabr(CPUPPCState *env)
109 {
110 CPUState *cs = env_cpu(env);
111 target_ulong ciabr = env->spr[SPR_CIABR];
112 target_ulong ciea, priv;
113
114 ciea = ciabr & PPC_BITMASK(0, 61);
115 priv = ciabr & PPC_BITMASK(62, 63);
116
117 if (env->ciabr_breakpoint) {
118 cpu_breakpoint_remove_by_ref(cs, env->ciabr_breakpoint);
119 env->ciabr_breakpoint = NULL;
120 }
121
122 if (priv) {
123 cpu_breakpoint_insert(cs, ciea, BP_CPU, &env->ciabr_breakpoint);
124 }
125 }
126
ppc_store_ciabr(CPUPPCState * env,target_ulong val)127 void ppc_store_ciabr(CPUPPCState *env, target_ulong val)
128 {
129 env->spr[SPR_CIABR] = val;
130 ppc_update_ciabr(env);
131 }
132
ppc_update_daw0(CPUPPCState * env)133 void ppc_update_daw0(CPUPPCState *env)
134 {
135 CPUState *cs = env_cpu(env);
136 target_ulong deaw = env->spr[SPR_DAWR0] & PPC_BITMASK(0, 60);
137 uint32_t dawrx = env->spr[SPR_DAWRX0];
138 int mrd = extract32(dawrx, PPC_BIT_NR(48), 54 - 48);
139 bool dw = extract32(dawrx, PPC_BIT_NR(57), 1);
140 bool dr = extract32(dawrx, PPC_BIT_NR(58), 1);
141 bool hv = extract32(dawrx, PPC_BIT_NR(61), 1);
142 bool sv = extract32(dawrx, PPC_BIT_NR(62), 1);
143 bool pr = extract32(dawrx, PPC_BIT_NR(62), 1);
144 vaddr len;
145 int flags;
146
147 if (env->dawr0_watchpoint) {
148 cpu_watchpoint_remove_by_ref(cs, env->dawr0_watchpoint);
149 env->dawr0_watchpoint = NULL;
150 }
151
152 if (!dr && !dw) {
153 return;
154 }
155
156 if (!hv && !sv && !pr) {
157 return;
158 }
159
160 len = (mrd + 1) * 8;
161 flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
162 if (dr) {
163 flags |= BP_MEM_READ;
164 }
165 if (dw) {
166 flags |= BP_MEM_WRITE;
167 }
168
169 cpu_watchpoint_insert(cs, deaw, len, flags, &env->dawr0_watchpoint);
170 }
171
ppc_store_dawr0(CPUPPCState * env,target_ulong val)172 void ppc_store_dawr0(CPUPPCState *env, target_ulong val)
173 {
174 env->spr[SPR_DAWR0] = val;
175 ppc_update_daw0(env);
176 }
177
ppc_store_dawrx0(CPUPPCState * env,uint32_t val)178 void ppc_store_dawrx0(CPUPPCState *env, uint32_t val)
179 {
180 int hrammc = extract32(val, PPC_BIT_NR(56), 1);
181
182 if (hrammc) {
183 /* This might be done with a second watchpoint at the xor of DEAW[0] */
184 qemu_log_mask(LOG_UNIMP, "%s: DAWRX0[HRAMMC] is unimplemented\n",
185 __func__);
186 }
187
188 env->spr[SPR_DAWRX0] = val;
189 ppc_update_daw0(env);
190 }
191 #endif
192 #endif
193
fpscr_set_rounding_mode(CPUPPCState * env)194 static inline void fpscr_set_rounding_mode(CPUPPCState *env)
195 {
196 int rnd_type;
197
198 /* Set rounding mode */
199 switch (env->fpscr & FP_RN) {
200 case 0:
201 /* Best approximation (round to nearest) */
202 rnd_type = float_round_nearest_even;
203 break;
204 case 1:
205 /* Smaller magnitude (round toward zero) */
206 rnd_type = float_round_to_zero;
207 break;
208 case 2:
209 /* Round toward +infinite */
210 rnd_type = float_round_up;
211 break;
212 default:
213 case 3:
214 /* Round toward -infinite */
215 rnd_type = float_round_down;
216 break;
217 }
218 set_float_rounding_mode(rnd_type, &env->fp_status);
219 }
220
ppc_store_fpscr(CPUPPCState * env,target_ulong val)221 void ppc_store_fpscr(CPUPPCState *env, target_ulong val)
222 {
223 val &= FPSCR_MTFS_MASK;
224 if (val & FPSCR_IX) {
225 val |= FP_VX;
226 }
227 if ((val >> FPSCR_XX) & (val >> FPSCR_XE) & 0x1f) {
228 val |= FP_FEX;
229 }
230 env->fpscr = val;
231 env->fp_status.rebias_overflow = (FP_OE & env->fpscr) ? true : false;
232 env->fp_status.rebias_underflow = (FP_UE & env->fpscr) ? true : false;
233 if (tcg_enabled()) {
234 fpscr_set_rounding_mode(env);
235 }
236 }
237