1 /* 2 * QEMU PowerPC CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 #ifndef QEMU_PPC_CPU_QOM_H 21 #define QEMU_PPC_CPU_QOM_H 22 23 #include "hw/core/cpu.h" 24 #include "qom/object.h" 25 26 #ifdef TARGET_PPC64 27 #define TYPE_POWERPC_CPU "powerpc64-cpu" 28 #else 29 #define TYPE_POWERPC_CPU "powerpc-cpu" 30 #endif 31 32 OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) 33 34 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU 35 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX 36 #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU 37 38 #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host") 39 40 ObjectClass *ppc_cpu_class_by_name(const char *name); 41 42 typedef struct CPUArchState CPUPPCState; 43 typedef struct ppc_tb_t ppc_tb_t; 44 typedef struct ppc_dcr_t ppc_dcr_t; 45 46 /*****************************************************************************/ 47 /* MMU model */ 48 typedef enum powerpc_mmu_t powerpc_mmu_t; 49 enum powerpc_mmu_t { 50 POWERPC_MMU_UNKNOWN = 0x00000000, 51 /* Standard 32 bits PowerPC MMU */ 52 POWERPC_MMU_32B = 0x00000001, 53 /* PowerPC 6xx MMU with software TLB */ 54 POWERPC_MMU_SOFT_6xx = 0x00000002, 55 /* 56 * PowerPC 74xx MMU with software TLB (this has been 57 * disabled, see git history for more information. 58 * keywords: tlbld tlbli TLBMISS PTEHI PTELO) 59 */ 60 POWERPC_MMU_SOFT_74xx = 0x00000003, 61 /* PowerPC 4xx MMU with software TLB */ 62 POWERPC_MMU_SOFT_4xx = 0x00000004, 63 /* PowerPC MMU in real mode only */ 64 POWERPC_MMU_REAL = 0x00000006, 65 /* Freescale MPC8xx MMU model */ 66 POWERPC_MMU_MPC8xx = 0x00000007, 67 /* BookE MMU model */ 68 POWERPC_MMU_BOOKE = 0x00000008, 69 /* BookE 2.06 MMU model */ 70 POWERPC_MMU_BOOKE206 = 0x00000009, 71 #define POWERPC_MMU_64 0x00010000 72 /* 64 bits PowerPC MMU */ 73 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, 74 /* Architecture 2.03 and later (has LPCR) */ 75 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, 76 /* Architecture 2.06 variant */ 77 POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003, 78 /* Architecture 2.07 variant */ 79 POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004, 80 /* Architecture 3.00 variant */ 81 POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005, 82 }; 83 84 static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model) 85 { 86 return mmu_model & POWERPC_MMU_64; 87 } 88 89 /*****************************************************************************/ 90 /* Exception model */ 91 typedef enum powerpc_excp_t powerpc_excp_t; 92 enum powerpc_excp_t { 93 POWERPC_EXCP_UNKNOWN = 0, 94 /* Standard PowerPC exception model */ 95 POWERPC_EXCP_STD, 96 /* PowerPC 40x exception model */ 97 POWERPC_EXCP_40x, 98 /* PowerPC 603/604/G2 exception model */ 99 POWERPC_EXCP_6xx, 100 /* PowerPC 7xx exception model */ 101 POWERPC_EXCP_7xx, 102 /* PowerPC 74xx exception model */ 103 POWERPC_EXCP_74xx, 104 /* BookE exception model */ 105 POWERPC_EXCP_BOOKE, 106 /* PowerPC 970 exception model */ 107 POWERPC_EXCP_970, 108 /* POWER7 exception model */ 109 POWERPC_EXCP_POWER7, 110 /* POWER8 exception model */ 111 POWERPC_EXCP_POWER8, 112 /* POWER9 exception model */ 113 POWERPC_EXCP_POWER9, 114 /* POWER10 exception model */ 115 POWERPC_EXCP_POWER10, 116 }; 117 118 /*****************************************************************************/ 119 /* PM instructions */ 120 typedef enum { 121 PPC_PM_DOZE, 122 PPC_PM_NAP, 123 PPC_PM_SLEEP, 124 PPC_PM_RVWINKLE, 125 PPC_PM_STOP, 126 } powerpc_pm_insn_t; 127 128 /*****************************************************************************/ 129 /* Input pins model */ 130 typedef enum powerpc_input_t powerpc_input_t; 131 enum powerpc_input_t { 132 PPC_FLAGS_INPUT_UNKNOWN = 0, 133 /* PowerPC 6xx bus */ 134 PPC_FLAGS_INPUT_6xx, 135 /* BookE bus */ 136 PPC_FLAGS_INPUT_BookE, 137 /* PowerPC 405 bus */ 138 PPC_FLAGS_INPUT_405, 139 /* PowerPC 970 bus */ 140 PPC_FLAGS_INPUT_970, 141 /* PowerPC POWER7 bus */ 142 PPC_FLAGS_INPUT_POWER7, 143 /* PowerPC POWER9 bus */ 144 PPC_FLAGS_INPUT_POWER9, 145 /* Freescale RCPU bus */ 146 PPC_FLAGS_INPUT_RCPU, 147 }; 148 149 typedef struct PPCHash64Options PPCHash64Options; 150 151 /** 152 * PowerPCCPUClass: 153 * @parent_realize: The parent class' realize handler. 154 * @parent_phases: The parent class' reset phase handlers. 155 * 156 * A PowerPC CPU model. 157 */ 158 struct PowerPCCPUClass { 159 /*< private >*/ 160 CPUClass parent_class; 161 /*< public >*/ 162 163 DeviceRealize parent_realize; 164 DeviceUnrealize parent_unrealize; 165 ResettablePhases parent_phases; 166 void (*parent_parse_features)(const char *type, char *str, Error **errp); 167 168 uint32_t pvr; 169 /* 170 * If @best is false, match if pcc is in the family of pvr 171 * Else match only if pcc is the best match for pvr in this family. 172 */ 173 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best); 174 uint64_t pcr_mask; /* Available bits in PCR register */ 175 uint64_t pcr_supported; /* Bits for supported PowerISA versions */ 176 uint32_t svr; 177 uint64_t insns_flags; 178 uint64_t insns_flags2; 179 uint64_t msr_mask; 180 uint64_t lpcr_mask; /* Available bits in the LPCR */ 181 uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */ 182 powerpc_mmu_t mmu_model; 183 powerpc_excp_t excp_model; 184 powerpc_input_t bus_model; 185 uint32_t flags; 186 int bfd_mach; 187 uint32_t l1_dcache_size, l1_icache_size; 188 #ifndef CONFIG_USER_ONLY 189 unsigned int gdb_num_sprs; 190 const char *gdb_spr_xml; 191 #endif 192 const PPCHash64Options *hash64_opts; 193 struct ppc_radix_page_info *radix_page_info; 194 uint32_t lrg_decr_bits; 195 int n_host_threads; 196 void (*init_proc)(CPUPPCState *env); 197 int (*check_pow)(CPUPPCState *env); 198 }; 199 200 #ifndef CONFIG_USER_ONLY 201 typedef struct PPCTimebase { 202 uint64_t guest_timebase; 203 int64_t time_of_the_day_ns; 204 bool runstate_paused; 205 } PPCTimebase; 206 207 extern const VMStateDescription vmstate_ppc_timebase; 208 209 #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \ 210 .name = (stringify(_field)), \ 211 .version_id = (_version), \ 212 .size = sizeof(PPCTimebase), \ 213 .vmsd = &vmstate_ppc_timebase, \ 214 .flags = VMS_STRUCT, \ 215 .offset = vmstate_offset_value(_state, _field, PPCTimebase), \ 216 } 217 218 void cpu_ppc_clock_vm_state_change(void *opaque, bool running, 219 RunState state); 220 #endif 221 222 #endif 223