1 /* 2 * QEMU PowerPC CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 #ifndef QEMU_PPC_CPU_QOM_H 21 #define QEMU_PPC_CPU_QOM_H 22 23 #include "hw/core/cpu.h" 24 #include "qom/object.h" 25 26 #ifdef TARGET_PPC64 27 #define TYPE_POWERPC_CPU "powerpc64-cpu" 28 #else 29 #define TYPE_POWERPC_CPU "powerpc-cpu" 30 #endif 31 32 OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass, 33 POWERPC_CPU) 34 35 typedef struct CPUPPCState CPUPPCState; 36 typedef struct ppc_tb_t ppc_tb_t; 37 typedef struct ppc_dcr_t ppc_dcr_t; 38 39 /*****************************************************************************/ 40 /* MMU model */ 41 typedef enum powerpc_mmu_t powerpc_mmu_t; 42 enum powerpc_mmu_t { 43 POWERPC_MMU_UNKNOWN = 0x00000000, 44 /* Standard 32 bits PowerPC MMU */ 45 POWERPC_MMU_32B = 0x00000001, 46 /* PowerPC 6xx MMU with software TLB */ 47 POWERPC_MMU_SOFT_6xx = 0x00000002, 48 /* 49 * PowerPC 74xx MMU with software TLB (this has been 50 * disabled, see git history for more information. 51 * keywords: tlbld tlbli TLBMISS PTEHI PTELO) 52 */ 53 POWERPC_MMU_SOFT_74xx = 0x00000003, 54 /* PowerPC 4xx MMU with software TLB */ 55 POWERPC_MMU_SOFT_4xx = 0x00000004, 56 /* PowerPC MMU in real mode only */ 57 POWERPC_MMU_REAL = 0x00000006, 58 /* Freescale MPC8xx MMU model */ 59 POWERPC_MMU_MPC8xx = 0x00000007, 60 /* BookE MMU model */ 61 POWERPC_MMU_BOOKE = 0x00000008, 62 /* BookE 2.06 MMU model */ 63 POWERPC_MMU_BOOKE206 = 0x00000009, 64 /* PowerPC 601 MMU model (specific BATs format) */ 65 POWERPC_MMU_601 = 0x0000000A, 66 #define POWERPC_MMU_64 0x00010000 67 /* 64 bits PowerPC MMU */ 68 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, 69 /* Architecture 2.03 and later (has LPCR) */ 70 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, 71 /* Architecture 2.06 variant */ 72 POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003, 73 /* Architecture 2.07 variant */ 74 POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004, 75 /* Architecture 3.00 variant */ 76 POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005, 77 }; 78 79 static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model) 80 { 81 return mmu_model & POWERPC_MMU_64; 82 } 83 84 /*****************************************************************************/ 85 /* Exception model */ 86 typedef enum powerpc_excp_t powerpc_excp_t; 87 enum powerpc_excp_t { 88 POWERPC_EXCP_UNKNOWN = 0, 89 /* Standard PowerPC exception model */ 90 POWERPC_EXCP_STD, 91 /* PowerPC 40x exception model */ 92 POWERPC_EXCP_40x, 93 /* PowerPC 601 exception model */ 94 POWERPC_EXCP_601, 95 /* PowerPC 602 exception model */ 96 POWERPC_EXCP_602, 97 /* PowerPC 603 exception model */ 98 POWERPC_EXCP_603, 99 /* PowerPC G2 exception model */ 100 POWERPC_EXCP_G2, 101 /* PowerPC 604 exception model */ 102 POWERPC_EXCP_604, 103 /* PowerPC 7x0 exception model */ 104 POWERPC_EXCP_7x0, 105 /* PowerPC 7x5 exception model */ 106 POWERPC_EXCP_7x5, 107 /* PowerPC 74xx exception model */ 108 POWERPC_EXCP_74xx, 109 /* BookE exception model */ 110 POWERPC_EXCP_BOOKE, 111 /* PowerPC 970 exception model */ 112 POWERPC_EXCP_970, 113 /* POWER7 exception model */ 114 POWERPC_EXCP_POWER7, 115 /* POWER8 exception model */ 116 POWERPC_EXCP_POWER8, 117 /* POWER9 exception model */ 118 POWERPC_EXCP_POWER9, 119 /* POWER10 exception model */ 120 POWERPC_EXCP_POWER10, 121 }; 122 123 /*****************************************************************************/ 124 /* PM instructions */ 125 typedef enum { 126 PPC_PM_DOZE, 127 PPC_PM_NAP, 128 PPC_PM_SLEEP, 129 PPC_PM_RVWINKLE, 130 PPC_PM_STOP, 131 } powerpc_pm_insn_t; 132 133 /*****************************************************************************/ 134 /* Input pins model */ 135 typedef enum powerpc_input_t powerpc_input_t; 136 enum powerpc_input_t { 137 PPC_FLAGS_INPUT_UNKNOWN = 0, 138 /* PowerPC 6xx bus */ 139 PPC_FLAGS_INPUT_6xx, 140 /* BookE bus */ 141 PPC_FLAGS_INPUT_BookE, 142 /* PowerPC 405 bus */ 143 PPC_FLAGS_INPUT_405, 144 /* PowerPC 970 bus */ 145 PPC_FLAGS_INPUT_970, 146 /* PowerPC POWER7 bus */ 147 PPC_FLAGS_INPUT_POWER7, 148 /* PowerPC POWER9 bus */ 149 PPC_FLAGS_INPUT_POWER9, 150 /* Freescale RCPU bus */ 151 PPC_FLAGS_INPUT_RCPU, 152 }; 153 154 typedef struct PPCHash64Options PPCHash64Options; 155 156 /** 157 * PowerPCCPUClass: 158 * @parent_realize: The parent class' realize handler. 159 * @parent_reset: The parent class' reset handler. 160 * 161 * A PowerPC CPU model. 162 */ 163 struct PowerPCCPUClass { 164 /*< private >*/ 165 CPUClass parent_class; 166 /*< public >*/ 167 168 DeviceRealize parent_realize; 169 DeviceUnrealize parent_unrealize; 170 DeviceReset parent_reset; 171 void (*parent_parse_features)(const char *type, char *str, Error **errp); 172 173 uint32_t pvr; 174 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr); 175 uint64_t pcr_mask; /* Available bits in PCR register */ 176 uint64_t pcr_supported; /* Bits for supported PowerISA versions */ 177 uint32_t svr; 178 uint64_t insns_flags; 179 uint64_t insns_flags2; 180 uint64_t msr_mask; 181 uint64_t lpcr_mask; /* Available bits in the LPCR */ 182 uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */ 183 powerpc_mmu_t mmu_model; 184 powerpc_excp_t excp_model; 185 powerpc_input_t bus_model; 186 uint32_t flags; 187 int bfd_mach; 188 uint32_t l1_dcache_size, l1_icache_size; 189 #ifndef CONFIG_USER_ONLY 190 unsigned int gdb_num_sprs; 191 const char *gdb_spr_xml; 192 #endif 193 const PPCHash64Options *hash64_opts; 194 struct ppc_radix_page_info *radix_page_info; 195 uint32_t lrg_decr_bits; 196 int n_host_threads; 197 void (*init_proc)(CPUPPCState *env); 198 int (*check_pow)(CPUPPCState *env); 199 }; 200 201 #ifndef CONFIG_USER_ONLY 202 typedef struct PPCTimebase { 203 uint64_t guest_timebase; 204 int64_t time_of_the_day_ns; 205 bool runstate_paused; 206 } PPCTimebase; 207 208 extern const VMStateDescription vmstate_ppc_timebase; 209 210 #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \ 211 .name = (stringify(_field)), \ 212 .version_id = (_version), \ 213 .size = sizeof(PPCTimebase), \ 214 .vmsd = &vmstate_ppc_timebase, \ 215 .flags = VMS_STRUCT, \ 216 .offset = vmstate_offset_value(_state, _field, PPCTimebase), \ 217 } 218 219 void cpu_ppc_clock_vm_state_change(void *opaque, bool running, 220 RunState state); 221 #endif 222 223 #endif 224