1 /* 2 * QEMU PowerPC CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 #ifndef QEMU_PPC_CPU_QOM_H 21 #define QEMU_PPC_CPU_QOM_H 22 23 #include "qom/cpu.h" 24 25 #ifdef TARGET_PPC64 26 #define TYPE_POWERPC_CPU "powerpc64-cpu" 27 #elif defined(TARGET_PPCEMB) 28 #define TYPE_POWERPC_CPU "embedded-powerpc-cpu" 29 #else 30 #define TYPE_POWERPC_CPU "powerpc-cpu" 31 #endif 32 33 #define POWERPC_CPU_CLASS(klass) \ 34 OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU) 35 #define POWERPC_CPU(obj) \ 36 OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU) 37 #define POWERPC_CPU_GET_CLASS(obj) \ 38 OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU) 39 40 typedef struct PowerPCCPU PowerPCCPU; 41 typedef struct CPUPPCState CPUPPCState; 42 typedef struct ppc_tb_t ppc_tb_t; 43 typedef struct ppc_dcr_t ppc_dcr_t; 44 45 /*****************************************************************************/ 46 /* MMU model */ 47 typedef enum powerpc_mmu_t powerpc_mmu_t; 48 enum powerpc_mmu_t { 49 POWERPC_MMU_UNKNOWN = 0x00000000, 50 /* Standard 32 bits PowerPC MMU */ 51 POWERPC_MMU_32B = 0x00000001, 52 /* PowerPC 6xx MMU with software TLB */ 53 POWERPC_MMU_SOFT_6xx = 0x00000002, 54 /* PowerPC 74xx MMU with software TLB */ 55 POWERPC_MMU_SOFT_74xx = 0x00000003, 56 /* PowerPC 4xx MMU with software TLB */ 57 POWERPC_MMU_SOFT_4xx = 0x00000004, 58 /* PowerPC 4xx MMU with software TLB and zones protections */ 59 POWERPC_MMU_SOFT_4xx_Z = 0x00000005, 60 /* PowerPC MMU in real mode only */ 61 POWERPC_MMU_REAL = 0x00000006, 62 /* Freescale MPC8xx MMU model */ 63 POWERPC_MMU_MPC8xx = 0x00000007, 64 /* BookE MMU model */ 65 POWERPC_MMU_BOOKE = 0x00000008, 66 /* BookE 2.06 MMU model */ 67 POWERPC_MMU_BOOKE206 = 0x00000009, 68 /* PowerPC 601 MMU model (specific BATs format) */ 69 POWERPC_MMU_601 = 0x0000000A, 70 #define POWERPC_MMU_64 0x00010000 71 #define POWERPC_MMU_1TSEG 0x00020000 72 #define POWERPC_MMU_AMR 0x00040000 73 #define POWERPC_MMU_64K 0x00080000 74 /* 64 bits PowerPC MMU */ 75 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, 76 /* Architecture 2.03 and later (has LPCR) */ 77 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, 78 /* Architecture 2.06 variant */ 79 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG 80 | POWERPC_MMU_64K 81 | POWERPC_MMU_AMR | 0x00000003, 82 /* Architecture 2.06 "degraded" (no 1T segments) */ 83 POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR 84 | 0x00000003, 85 /* Architecture 2.07 variant */ 86 POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG 87 | POWERPC_MMU_64K 88 | POWERPC_MMU_AMR | 0x00000004, 89 /* Architecture 2.07 "degraded" (no 1T segments) */ 90 POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR 91 | 0x00000004, 92 /* Architecture 3.00 variant */ 93 POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG 94 | POWERPC_MMU_64K 95 | POWERPC_MMU_AMR | 0x00000005, 96 }; 97 98 /*****************************************************************************/ 99 /* Exception model */ 100 typedef enum powerpc_excp_t powerpc_excp_t; 101 enum powerpc_excp_t { 102 POWERPC_EXCP_UNKNOWN = 0, 103 /* Standard PowerPC exception model */ 104 POWERPC_EXCP_STD, 105 /* PowerPC 40x exception model */ 106 POWERPC_EXCP_40x, 107 /* PowerPC 601 exception model */ 108 POWERPC_EXCP_601, 109 /* PowerPC 602 exception model */ 110 POWERPC_EXCP_602, 111 /* PowerPC 603 exception model */ 112 POWERPC_EXCP_603, 113 /* PowerPC 603e exception model */ 114 POWERPC_EXCP_603E, 115 /* PowerPC G2 exception model */ 116 POWERPC_EXCP_G2, 117 /* PowerPC 604 exception model */ 118 POWERPC_EXCP_604, 119 /* PowerPC 7x0 exception model */ 120 POWERPC_EXCP_7x0, 121 /* PowerPC 7x5 exception model */ 122 POWERPC_EXCP_7x5, 123 /* PowerPC 74xx exception model */ 124 POWERPC_EXCP_74xx, 125 /* BookE exception model */ 126 POWERPC_EXCP_BOOKE, 127 /* PowerPC 970 exception model */ 128 POWERPC_EXCP_970, 129 /* POWER7 exception model */ 130 POWERPC_EXCP_POWER7, 131 /* POWER8 exception model */ 132 POWERPC_EXCP_POWER8, 133 }; 134 135 /*****************************************************************************/ 136 /* PM instructions */ 137 typedef enum { 138 PPC_PM_DOZE, 139 PPC_PM_NAP, 140 PPC_PM_SLEEP, 141 PPC_PM_RVWINKLE, 142 } powerpc_pm_insn_t; 143 144 /*****************************************************************************/ 145 /* Input pins model */ 146 typedef enum powerpc_input_t powerpc_input_t; 147 enum powerpc_input_t { 148 PPC_FLAGS_INPUT_UNKNOWN = 0, 149 /* PowerPC 6xx bus */ 150 PPC_FLAGS_INPUT_6xx, 151 /* BookE bus */ 152 PPC_FLAGS_INPUT_BookE, 153 /* PowerPC 405 bus */ 154 PPC_FLAGS_INPUT_405, 155 /* PowerPC 970 bus */ 156 PPC_FLAGS_INPUT_970, 157 /* PowerPC POWER7 bus */ 158 PPC_FLAGS_INPUT_POWER7, 159 /* PowerPC 401 bus */ 160 PPC_FLAGS_INPUT_401, 161 /* Freescale RCPU bus */ 162 PPC_FLAGS_INPUT_RCPU, 163 }; 164 165 struct ppc_segment_page_sizes; 166 167 /** 168 * PowerPCCPUClass: 169 * @parent_realize: The parent class' realize handler. 170 * @parent_reset: The parent class' reset handler. 171 * 172 * A PowerPC CPU model. 173 */ 174 typedef struct PowerPCCPUClass { 175 /*< private >*/ 176 CPUClass parent_class; 177 /*< public >*/ 178 179 DeviceRealize parent_realize; 180 DeviceUnrealize parent_unrealize; 181 void (*parent_reset)(CPUState *cpu); 182 183 uint32_t pvr; 184 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr); 185 uint64_t pcr_mask; /* Available bits in PCR register */ 186 uint64_t pcr_supported; /* Bits for supported PowerISA versions */ 187 uint32_t svr; 188 uint64_t insns_flags; 189 uint64_t insns_flags2; 190 uint64_t msr_mask; 191 powerpc_mmu_t mmu_model; 192 powerpc_excp_t excp_model; 193 powerpc_input_t bus_model; 194 uint32_t flags; 195 int bfd_mach; 196 uint32_t l1_dcache_size, l1_icache_size; 197 const struct ppc_segment_page_sizes *sps; 198 void (*init_proc)(CPUPPCState *env); 199 int (*check_pow)(CPUPPCState *env); 200 int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx); 201 bool (*interrupts_big_endian)(PowerPCCPU *cpu); 202 } PowerPCCPUClass; 203 204 #ifndef CONFIG_USER_ONLY 205 typedef struct PPCTimebase { 206 uint64_t guest_timebase; 207 int64_t time_of_the_day_ns; 208 } PPCTimebase; 209 210 extern const struct VMStateDescription vmstate_ppc_timebase; 211 212 #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \ 213 .name = (stringify(_field)), \ 214 .version_id = (_version), \ 215 .size = sizeof(PPCTimebase), \ 216 .vmsd = &vmstate_ppc_timebase, \ 217 .flags = VMS_STRUCT, \ 218 .offset = vmstate_offset_value(_state, _field, PPCTimebase), \ 219 } 220 221 void cpu_ppc_clock_vm_state_change(void *opaque, int running, 222 RunState state); 223 #endif 224 225 #endif 226