1 /* 2 * QEMU PowerPC CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 #ifndef QEMU_PPC_CPU_QOM_H 21 #define QEMU_PPC_CPU_QOM_H 22 23 #include "hw/core/cpu.h" 24 #include "qom/object.h" 25 26 #ifdef TARGET_PPC64 27 #define TYPE_POWERPC_CPU "powerpc64-cpu" 28 #else 29 #define TYPE_POWERPC_CPU "powerpc-cpu" 30 #endif 31 32 OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass, 33 POWERPC_CPU) 34 35 typedef struct CPUArchState CPUPPCState; 36 typedef struct ppc_tb_t ppc_tb_t; 37 typedef struct ppc_dcr_t ppc_dcr_t; 38 39 /*****************************************************************************/ 40 /* MMU model */ 41 typedef enum powerpc_mmu_t powerpc_mmu_t; 42 enum powerpc_mmu_t { 43 POWERPC_MMU_UNKNOWN = 0x00000000, 44 /* Standard 32 bits PowerPC MMU */ 45 POWERPC_MMU_32B = 0x00000001, 46 /* PowerPC 6xx MMU with software TLB */ 47 POWERPC_MMU_SOFT_6xx = 0x00000002, 48 /* 49 * PowerPC 74xx MMU with software TLB (this has been 50 * disabled, see git history for more information. 51 * keywords: tlbld tlbli TLBMISS PTEHI PTELO) 52 */ 53 POWERPC_MMU_SOFT_74xx = 0x00000003, 54 /* PowerPC 4xx MMU with software TLB */ 55 POWERPC_MMU_SOFT_4xx = 0x00000004, 56 /* PowerPC MMU in real mode only */ 57 POWERPC_MMU_REAL = 0x00000006, 58 /* Freescale MPC8xx MMU model */ 59 POWERPC_MMU_MPC8xx = 0x00000007, 60 /* BookE MMU model */ 61 POWERPC_MMU_BOOKE = 0x00000008, 62 /* BookE 2.06 MMU model */ 63 POWERPC_MMU_BOOKE206 = 0x00000009, 64 #define POWERPC_MMU_64 0x00010000 65 /* 64 bits PowerPC MMU */ 66 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, 67 /* Architecture 2.03 and later (has LPCR) */ 68 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, 69 /* Architecture 2.06 variant */ 70 POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003, 71 /* Architecture 2.07 variant */ 72 POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004, 73 /* Architecture 3.00 variant */ 74 POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005, 75 }; 76 77 static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model) 78 { 79 return mmu_model & POWERPC_MMU_64; 80 } 81 82 /*****************************************************************************/ 83 /* Exception model */ 84 typedef enum powerpc_excp_t powerpc_excp_t; 85 enum powerpc_excp_t { 86 POWERPC_EXCP_UNKNOWN = 0, 87 /* Standard PowerPC exception model */ 88 POWERPC_EXCP_STD, 89 /* PowerPC 40x exception model */ 90 POWERPC_EXCP_40x, 91 /* PowerPC 603/604/G2 exception model */ 92 POWERPC_EXCP_6xx, 93 /* PowerPC 7xx exception model */ 94 POWERPC_EXCP_7xx, 95 /* PowerPC 74xx exception model */ 96 POWERPC_EXCP_74xx, 97 /* BookE exception model */ 98 POWERPC_EXCP_BOOKE, 99 /* PowerPC 970 exception model */ 100 POWERPC_EXCP_970, 101 /* POWER7 exception model */ 102 POWERPC_EXCP_POWER7, 103 /* POWER8 exception model */ 104 POWERPC_EXCP_POWER8, 105 /* POWER9 exception model */ 106 POWERPC_EXCP_POWER9, 107 /* POWER10 exception model */ 108 POWERPC_EXCP_POWER10, 109 }; 110 111 /*****************************************************************************/ 112 /* PM instructions */ 113 typedef enum { 114 PPC_PM_DOZE, 115 PPC_PM_NAP, 116 PPC_PM_SLEEP, 117 PPC_PM_RVWINKLE, 118 PPC_PM_STOP, 119 } powerpc_pm_insn_t; 120 121 /*****************************************************************************/ 122 /* Input pins model */ 123 typedef enum powerpc_input_t powerpc_input_t; 124 enum powerpc_input_t { 125 PPC_FLAGS_INPUT_UNKNOWN = 0, 126 /* PowerPC 6xx bus */ 127 PPC_FLAGS_INPUT_6xx, 128 /* BookE bus */ 129 PPC_FLAGS_INPUT_BookE, 130 /* PowerPC 405 bus */ 131 PPC_FLAGS_INPUT_405, 132 /* PowerPC 970 bus */ 133 PPC_FLAGS_INPUT_970, 134 /* PowerPC POWER7 bus */ 135 PPC_FLAGS_INPUT_POWER7, 136 /* PowerPC POWER9 bus */ 137 PPC_FLAGS_INPUT_POWER9, 138 /* Freescale RCPU bus */ 139 PPC_FLAGS_INPUT_RCPU, 140 }; 141 142 typedef struct PPCHash64Options PPCHash64Options; 143 144 /** 145 * PowerPCCPUClass: 146 * @parent_realize: The parent class' realize handler. 147 * @parent_reset: The parent class' reset handler. 148 * 149 * A PowerPC CPU model. 150 */ 151 struct PowerPCCPUClass { 152 /*< private >*/ 153 CPUClass parent_class; 154 /*< public >*/ 155 156 DeviceRealize parent_realize; 157 DeviceUnrealize parent_unrealize; 158 DeviceReset parent_reset; 159 void (*parent_parse_features)(const char *type, char *str, Error **errp); 160 161 uint32_t pvr; 162 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr); 163 uint64_t pcr_mask; /* Available bits in PCR register */ 164 uint64_t pcr_supported; /* Bits for supported PowerISA versions */ 165 uint32_t svr; 166 uint64_t insns_flags; 167 uint64_t insns_flags2; 168 uint64_t msr_mask; 169 uint64_t lpcr_mask; /* Available bits in the LPCR */ 170 uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */ 171 powerpc_mmu_t mmu_model; 172 powerpc_excp_t excp_model; 173 powerpc_input_t bus_model; 174 uint32_t flags; 175 int bfd_mach; 176 uint32_t l1_dcache_size, l1_icache_size; 177 #ifndef CONFIG_USER_ONLY 178 unsigned int gdb_num_sprs; 179 const char *gdb_spr_xml; 180 #endif 181 const PPCHash64Options *hash64_opts; 182 struct ppc_radix_page_info *radix_page_info; 183 uint32_t lrg_decr_bits; 184 int n_host_threads; 185 void (*init_proc)(CPUPPCState *env); 186 int (*check_pow)(CPUPPCState *env); 187 }; 188 189 #ifndef CONFIG_USER_ONLY 190 typedef struct PPCTimebase { 191 uint64_t guest_timebase; 192 int64_t time_of_the_day_ns; 193 bool runstate_paused; 194 } PPCTimebase; 195 196 extern const VMStateDescription vmstate_ppc_timebase; 197 198 #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \ 199 .name = (stringify(_field)), \ 200 .version_id = (_version), \ 201 .size = sizeof(PPCTimebase), \ 202 .vmsd = &vmstate_ppc_timebase, \ 203 .flags = VMS_STRUCT, \ 204 .offset = vmstate_offset_value(_state, _field, PPCTimebase), \ 205 } 206 207 void cpu_ppc_clock_vm_state_change(void *opaque, bool running, 208 RunState state); 209 #endif 210 211 #endif 212