1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * QEMU PowerPC CPU 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2012 SUSE LINUX Products GmbH 5fcf5ef2aSThomas Huth * 6fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 7fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 8fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 9fcf5ef2aSThomas Huth * version 2.1 of the License, or (at your option) any later version. 10fcf5ef2aSThomas Huth * 11fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 12fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 13fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14fcf5ef2aSThomas Huth * Lesser General Public License for more details. 15fcf5ef2aSThomas Huth * 16fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 17fcf5ef2aSThomas Huth * License along with this library; if not, see 18fcf5ef2aSThomas Huth * <http://www.gnu.org/licenses/lgpl-2.1.html> 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth #ifndef QEMU_PPC_CPU_QOM_H 21fcf5ef2aSThomas Huth #define QEMU_PPC_CPU_QOM_H 22fcf5ef2aSThomas Huth 23fcf5ef2aSThomas Huth #include "qom/cpu.h" 24fcf5ef2aSThomas Huth 25fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 26fcf5ef2aSThomas Huth #define TYPE_POWERPC_CPU "powerpc64-cpu" 27fcf5ef2aSThomas Huth #elif defined(TARGET_PPCEMB) 28fcf5ef2aSThomas Huth #define TYPE_POWERPC_CPU "embedded-powerpc-cpu" 29fcf5ef2aSThomas Huth #else 30fcf5ef2aSThomas Huth #define TYPE_POWERPC_CPU "powerpc-cpu" 31fcf5ef2aSThomas Huth #endif 32fcf5ef2aSThomas Huth 33fcf5ef2aSThomas Huth #define POWERPC_CPU_CLASS(klass) \ 34fcf5ef2aSThomas Huth OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU) 35fcf5ef2aSThomas Huth #define POWERPC_CPU(obj) \ 36fcf5ef2aSThomas Huth OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU) 37fcf5ef2aSThomas Huth #define POWERPC_CPU_GET_CLASS(obj) \ 38fcf5ef2aSThomas Huth OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU) 39fcf5ef2aSThomas Huth 40fcf5ef2aSThomas Huth typedef struct PowerPCCPU PowerPCCPU; 41fcf5ef2aSThomas Huth typedef struct CPUPPCState CPUPPCState; 42fcf5ef2aSThomas Huth typedef struct ppc_tb_t ppc_tb_t; 43fcf5ef2aSThomas Huth typedef struct ppc_dcr_t ppc_dcr_t; 44fcf5ef2aSThomas Huth 45fcf5ef2aSThomas Huth /*****************************************************************************/ 46fcf5ef2aSThomas Huth /* MMU model */ 47fcf5ef2aSThomas Huth typedef enum powerpc_mmu_t powerpc_mmu_t; 48fcf5ef2aSThomas Huth enum powerpc_mmu_t { 49fcf5ef2aSThomas Huth POWERPC_MMU_UNKNOWN = 0x00000000, 50fcf5ef2aSThomas Huth /* Standard 32 bits PowerPC MMU */ 51fcf5ef2aSThomas Huth POWERPC_MMU_32B = 0x00000001, 52fcf5ef2aSThomas Huth /* PowerPC 6xx MMU with software TLB */ 53fcf5ef2aSThomas Huth POWERPC_MMU_SOFT_6xx = 0x00000002, 54fcf5ef2aSThomas Huth /* PowerPC 74xx MMU with software TLB */ 55fcf5ef2aSThomas Huth POWERPC_MMU_SOFT_74xx = 0x00000003, 56fcf5ef2aSThomas Huth /* PowerPC 4xx MMU with software TLB */ 57fcf5ef2aSThomas Huth POWERPC_MMU_SOFT_4xx = 0x00000004, 58fcf5ef2aSThomas Huth /* PowerPC 4xx MMU with software TLB and zones protections */ 59fcf5ef2aSThomas Huth POWERPC_MMU_SOFT_4xx_Z = 0x00000005, 60fcf5ef2aSThomas Huth /* PowerPC MMU in real mode only */ 61fcf5ef2aSThomas Huth POWERPC_MMU_REAL = 0x00000006, 62fcf5ef2aSThomas Huth /* Freescale MPC8xx MMU model */ 63fcf5ef2aSThomas Huth POWERPC_MMU_MPC8xx = 0x00000007, 64fcf5ef2aSThomas Huth /* BookE MMU model */ 65fcf5ef2aSThomas Huth POWERPC_MMU_BOOKE = 0x00000008, 66fcf5ef2aSThomas Huth /* BookE 2.06 MMU model */ 67fcf5ef2aSThomas Huth POWERPC_MMU_BOOKE206 = 0x00000009, 68fcf5ef2aSThomas Huth /* PowerPC 601 MMU model (specific BATs format) */ 69fcf5ef2aSThomas Huth POWERPC_MMU_601 = 0x0000000A, 70fcf5ef2aSThomas Huth #define POWERPC_MMU_64 0x00010000 71fcf5ef2aSThomas Huth /* 64 bits PowerPC MMU */ 72fcf5ef2aSThomas Huth POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, 73fcf5ef2aSThomas Huth /* Architecture 2.03 and later (has LPCR) */ 74fcf5ef2aSThomas Huth POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, 75fcf5ef2aSThomas Huth /* Architecture 2.06 variant */ 7658969eeeSDavid Gibson POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003, 77fcf5ef2aSThomas Huth /* Architecture 2.07 variant */ 7858969eeeSDavid Gibson POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004, 7986cf1e9fSSuraj Jitindar Singh /* Architecture 3.00 variant */ 80*ca79b3b7SDavid Gibson POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005, 81fcf5ef2aSThomas Huth }; 82ec975e83SSam Bobroff #define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF)) 83ec975e83SSam Bobroff #define POWERPC_MMU_VER_64B POWERPC_MMU_VER(POWERPC_MMU_64B) 84ec975e83SSam Bobroff #define POWERPC_MMU_VER_2_03 POWERPC_MMU_VER(POWERPC_MMU_2_03) 85ec975e83SSam Bobroff #define POWERPC_MMU_VER_2_06 POWERPC_MMU_VER(POWERPC_MMU_2_06) 86ec975e83SSam Bobroff #define POWERPC_MMU_VER_2_07 POWERPC_MMU_VER(POWERPC_MMU_2_07) 87ec975e83SSam Bobroff #define POWERPC_MMU_VER_3_00 POWERPC_MMU_VER(POWERPC_MMU_3_00) 88fcf5ef2aSThomas Huth 89fcf5ef2aSThomas Huth /*****************************************************************************/ 90fcf5ef2aSThomas Huth /* Exception model */ 91fcf5ef2aSThomas Huth typedef enum powerpc_excp_t powerpc_excp_t; 92fcf5ef2aSThomas Huth enum powerpc_excp_t { 93fcf5ef2aSThomas Huth POWERPC_EXCP_UNKNOWN = 0, 94fcf5ef2aSThomas Huth /* Standard PowerPC exception model */ 95fcf5ef2aSThomas Huth POWERPC_EXCP_STD, 96fcf5ef2aSThomas Huth /* PowerPC 40x exception model */ 97fcf5ef2aSThomas Huth POWERPC_EXCP_40x, 98fcf5ef2aSThomas Huth /* PowerPC 601 exception model */ 99fcf5ef2aSThomas Huth POWERPC_EXCP_601, 100fcf5ef2aSThomas Huth /* PowerPC 602 exception model */ 101fcf5ef2aSThomas Huth POWERPC_EXCP_602, 102fcf5ef2aSThomas Huth /* PowerPC 603 exception model */ 103fcf5ef2aSThomas Huth POWERPC_EXCP_603, 104fcf5ef2aSThomas Huth /* PowerPC 603e exception model */ 105fcf5ef2aSThomas Huth POWERPC_EXCP_603E, 106fcf5ef2aSThomas Huth /* PowerPC G2 exception model */ 107fcf5ef2aSThomas Huth POWERPC_EXCP_G2, 108fcf5ef2aSThomas Huth /* PowerPC 604 exception model */ 109fcf5ef2aSThomas Huth POWERPC_EXCP_604, 110fcf5ef2aSThomas Huth /* PowerPC 7x0 exception model */ 111fcf5ef2aSThomas Huth POWERPC_EXCP_7x0, 112fcf5ef2aSThomas Huth /* PowerPC 7x5 exception model */ 113fcf5ef2aSThomas Huth POWERPC_EXCP_7x5, 114fcf5ef2aSThomas Huth /* PowerPC 74xx exception model */ 115fcf5ef2aSThomas Huth POWERPC_EXCP_74xx, 116fcf5ef2aSThomas Huth /* BookE exception model */ 117fcf5ef2aSThomas Huth POWERPC_EXCP_BOOKE, 118fcf5ef2aSThomas Huth /* PowerPC 970 exception model */ 119fcf5ef2aSThomas Huth POWERPC_EXCP_970, 120fcf5ef2aSThomas Huth /* POWER7 exception model */ 121fcf5ef2aSThomas Huth POWERPC_EXCP_POWER7, 122fcf5ef2aSThomas Huth /* POWER8 exception model */ 123fcf5ef2aSThomas Huth POWERPC_EXCP_POWER8, 124fcf5ef2aSThomas Huth }; 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth /*****************************************************************************/ 127fcf5ef2aSThomas Huth /* PM instructions */ 128fcf5ef2aSThomas Huth typedef enum { 129fcf5ef2aSThomas Huth PPC_PM_DOZE, 130fcf5ef2aSThomas Huth PPC_PM_NAP, 131fcf5ef2aSThomas Huth PPC_PM_SLEEP, 132fcf5ef2aSThomas Huth PPC_PM_RVWINKLE, 133fcf5ef2aSThomas Huth } powerpc_pm_insn_t; 134fcf5ef2aSThomas Huth 135fcf5ef2aSThomas Huth /*****************************************************************************/ 136fcf5ef2aSThomas Huth /* Input pins model */ 137fcf5ef2aSThomas Huth typedef enum powerpc_input_t powerpc_input_t; 138fcf5ef2aSThomas Huth enum powerpc_input_t { 139fcf5ef2aSThomas Huth PPC_FLAGS_INPUT_UNKNOWN = 0, 140fcf5ef2aSThomas Huth /* PowerPC 6xx bus */ 141fcf5ef2aSThomas Huth PPC_FLAGS_INPUT_6xx, 142fcf5ef2aSThomas Huth /* BookE bus */ 143fcf5ef2aSThomas Huth PPC_FLAGS_INPUT_BookE, 144fcf5ef2aSThomas Huth /* PowerPC 405 bus */ 145fcf5ef2aSThomas Huth PPC_FLAGS_INPUT_405, 146fcf5ef2aSThomas Huth /* PowerPC 970 bus */ 147fcf5ef2aSThomas Huth PPC_FLAGS_INPUT_970, 148fcf5ef2aSThomas Huth /* PowerPC POWER7 bus */ 149fcf5ef2aSThomas Huth PPC_FLAGS_INPUT_POWER7, 150fcf5ef2aSThomas Huth /* PowerPC 401 bus */ 151fcf5ef2aSThomas Huth PPC_FLAGS_INPUT_401, 152fcf5ef2aSThomas Huth /* Freescale RCPU bus */ 153fcf5ef2aSThomas Huth PPC_FLAGS_INPUT_RCPU, 154fcf5ef2aSThomas Huth }; 155fcf5ef2aSThomas Huth 156b07c59f7SDavid Gibson typedef struct PPCHash64Options PPCHash64Options; 157fcf5ef2aSThomas Huth 158fcf5ef2aSThomas Huth /** 159fcf5ef2aSThomas Huth * PowerPCCPUClass: 160fcf5ef2aSThomas Huth * @parent_realize: The parent class' realize handler. 161fcf5ef2aSThomas Huth * @parent_reset: The parent class' reset handler. 162fcf5ef2aSThomas Huth * 163fcf5ef2aSThomas Huth * A PowerPC CPU model. 164fcf5ef2aSThomas Huth */ 165fcf5ef2aSThomas Huth typedef struct PowerPCCPUClass { 166fcf5ef2aSThomas Huth /*< private >*/ 167fcf5ef2aSThomas Huth CPUClass parent_class; 168fcf5ef2aSThomas Huth /*< public >*/ 169fcf5ef2aSThomas Huth 170fcf5ef2aSThomas Huth DeviceRealize parent_realize; 171fcf5ef2aSThomas Huth DeviceUnrealize parent_unrealize; 172fcf5ef2aSThomas Huth void (*parent_reset)(CPUState *cpu); 173b8e99967SIgor Mammedov void (*parent_parse_features)(const char *type, char *str, Error **errp); 174fcf5ef2aSThomas Huth 175fcf5ef2aSThomas Huth uint32_t pvr; 176fcf5ef2aSThomas Huth bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr); 177fcf5ef2aSThomas Huth uint64_t pcr_mask; /* Available bits in PCR register */ 178fcf5ef2aSThomas Huth uint64_t pcr_supported; /* Bits for supported PowerISA versions */ 179fcf5ef2aSThomas Huth uint32_t svr; 180fcf5ef2aSThomas Huth uint64_t insns_flags; 181fcf5ef2aSThomas Huth uint64_t insns_flags2; 182fcf5ef2aSThomas Huth uint64_t msr_mask; 183403aacdbSCédric Le Goater uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */ 184fcf5ef2aSThomas Huth powerpc_mmu_t mmu_model; 185fcf5ef2aSThomas Huth powerpc_excp_t excp_model; 186fcf5ef2aSThomas Huth powerpc_input_t bus_model; 187fcf5ef2aSThomas Huth uint32_t flags; 188fcf5ef2aSThomas Huth int bfd_mach; 189fcf5ef2aSThomas Huth uint32_t l1_dcache_size, l1_icache_size; 190b07c59f7SDavid Gibson const PPCHash64Options *hash64_opts; 191c64abd1fSSam Bobroff struct ppc_radix_page_info *radix_page_info; 192fcf5ef2aSThomas Huth void (*init_proc)(CPUPPCState *env); 193fcf5ef2aSThomas Huth int (*check_pow)(CPUPPCState *env); 194fcf5ef2aSThomas Huth int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx); 195fcf5ef2aSThomas Huth bool (*interrupts_big_endian)(PowerPCCPU *cpu); 196fcf5ef2aSThomas Huth } PowerPCCPUClass; 197fcf5ef2aSThomas Huth 198fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 199fcf5ef2aSThomas Huth typedef struct PPCTimebase { 200fcf5ef2aSThomas Huth uint64_t guest_timebase; 201fcf5ef2aSThomas Huth int64_t time_of_the_day_ns; 202fcf5ef2aSThomas Huth } PPCTimebase; 203fcf5ef2aSThomas Huth 204fcf5ef2aSThomas Huth extern const struct VMStateDescription vmstate_ppc_timebase; 205fcf5ef2aSThomas Huth 206fcf5ef2aSThomas Huth #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \ 207fcf5ef2aSThomas Huth .name = (stringify(_field)), \ 208fcf5ef2aSThomas Huth .version_id = (_version), \ 209fcf5ef2aSThomas Huth .size = sizeof(PPCTimebase), \ 210fcf5ef2aSThomas Huth .vmsd = &vmstate_ppc_timebase, \ 211fcf5ef2aSThomas Huth .flags = VMS_STRUCT, \ 212fcf5ef2aSThomas Huth .offset = vmstate_offset_value(_state, _field, PPCTimebase), \ 213fcf5ef2aSThomas Huth } 21442043e4fSLaurent Vivier 21542043e4fSLaurent Vivier void cpu_ppc_clock_vm_state_change(void *opaque, int running, 21642043e4fSLaurent Vivier RunState state); 217fcf5ef2aSThomas Huth #endif 218fcf5ef2aSThomas Huth 219fcf5ef2aSThomas Huth #endif 220