1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * QEMU PowerPC CPU 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2012 SUSE LINUX Products GmbH 5fcf5ef2aSThomas Huth * 6fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 7fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 8fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 9fcf5ef2aSThomas Huth * version 2.1 of the License, or (at your option) any later version. 10fcf5ef2aSThomas Huth * 11fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 12fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 13fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14fcf5ef2aSThomas Huth * Lesser General Public License for more details. 15fcf5ef2aSThomas Huth * 16fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 17fcf5ef2aSThomas Huth * License along with this library; if not, see 18fcf5ef2aSThomas Huth * <http://www.gnu.org/licenses/lgpl-2.1.html> 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth #ifndef QEMU_PPC_CPU_QOM_H 21fcf5ef2aSThomas Huth #define QEMU_PPC_CPU_QOM_H 22fcf5ef2aSThomas Huth 23fcf5ef2aSThomas Huth #include "qom/cpu.h" 24fcf5ef2aSThomas Huth 25fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 26fcf5ef2aSThomas Huth #define TYPE_POWERPC_CPU "powerpc64-cpu" 27fcf5ef2aSThomas Huth #elif defined(TARGET_PPCEMB) 28fcf5ef2aSThomas Huth #define TYPE_POWERPC_CPU "embedded-powerpc-cpu" 29fcf5ef2aSThomas Huth #else 30fcf5ef2aSThomas Huth #define TYPE_POWERPC_CPU "powerpc-cpu" 31fcf5ef2aSThomas Huth #endif 32fcf5ef2aSThomas Huth 33fcf5ef2aSThomas Huth #define POWERPC_CPU_CLASS(klass) \ 34fcf5ef2aSThomas Huth OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU) 35fcf5ef2aSThomas Huth #define POWERPC_CPU(obj) \ 36fcf5ef2aSThomas Huth OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU) 37fcf5ef2aSThomas Huth #define POWERPC_CPU_GET_CLASS(obj) \ 38fcf5ef2aSThomas Huth OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU) 39fcf5ef2aSThomas Huth 40fcf5ef2aSThomas Huth typedef struct PowerPCCPU PowerPCCPU; 41fcf5ef2aSThomas Huth typedef struct CPUPPCState CPUPPCState; 42fcf5ef2aSThomas Huth typedef struct ppc_tb_t ppc_tb_t; 43fcf5ef2aSThomas Huth typedef struct ppc_dcr_t ppc_dcr_t; 44fcf5ef2aSThomas Huth 45fcf5ef2aSThomas Huth /*****************************************************************************/ 46fcf5ef2aSThomas Huth /* MMU model */ 47fcf5ef2aSThomas Huth typedef enum powerpc_mmu_t powerpc_mmu_t; 48fcf5ef2aSThomas Huth enum powerpc_mmu_t { 49fcf5ef2aSThomas Huth POWERPC_MMU_UNKNOWN = 0x00000000, 50fcf5ef2aSThomas Huth /* Standard 32 bits PowerPC MMU */ 51fcf5ef2aSThomas Huth POWERPC_MMU_32B = 0x00000001, 52fcf5ef2aSThomas Huth /* PowerPC 6xx MMU with software TLB */ 53fcf5ef2aSThomas Huth POWERPC_MMU_SOFT_6xx = 0x00000002, 54fcf5ef2aSThomas Huth /* PowerPC 74xx MMU with software TLB */ 55fcf5ef2aSThomas Huth POWERPC_MMU_SOFT_74xx = 0x00000003, 56fcf5ef2aSThomas Huth /* PowerPC 4xx MMU with software TLB */ 57fcf5ef2aSThomas Huth POWERPC_MMU_SOFT_4xx = 0x00000004, 58fcf5ef2aSThomas Huth /* PowerPC 4xx MMU with software TLB and zones protections */ 59fcf5ef2aSThomas Huth POWERPC_MMU_SOFT_4xx_Z = 0x00000005, 60fcf5ef2aSThomas Huth /* PowerPC MMU in real mode only */ 61fcf5ef2aSThomas Huth POWERPC_MMU_REAL = 0x00000006, 62fcf5ef2aSThomas Huth /* Freescale MPC8xx MMU model */ 63fcf5ef2aSThomas Huth POWERPC_MMU_MPC8xx = 0x00000007, 64fcf5ef2aSThomas Huth /* BookE MMU model */ 65fcf5ef2aSThomas Huth POWERPC_MMU_BOOKE = 0x00000008, 66fcf5ef2aSThomas Huth /* BookE 2.06 MMU model */ 67fcf5ef2aSThomas Huth POWERPC_MMU_BOOKE206 = 0x00000009, 68fcf5ef2aSThomas Huth /* PowerPC 601 MMU model (specific BATs format) */ 69fcf5ef2aSThomas Huth POWERPC_MMU_601 = 0x0000000A, 70fcf5ef2aSThomas Huth #define POWERPC_MMU_64 0x00010000 71fcf5ef2aSThomas Huth #define POWERPC_MMU_1TSEG 0x00020000 72fcf5ef2aSThomas Huth #define POWERPC_MMU_AMR 0x00040000 73fcf5ef2aSThomas Huth #define POWERPC_MMU_64K 0x00080000 74*0922f1e4SDavid Gibson #define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */ 75fcf5ef2aSThomas Huth /* 64 bits PowerPC MMU */ 76fcf5ef2aSThomas Huth POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, 77fcf5ef2aSThomas Huth /* Architecture 2.03 and later (has LPCR) */ 78fcf5ef2aSThomas Huth POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, 79fcf5ef2aSThomas Huth /* Architecture 2.06 variant */ 80fcf5ef2aSThomas Huth POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG 81fcf5ef2aSThomas Huth | POWERPC_MMU_64K 82fcf5ef2aSThomas Huth | POWERPC_MMU_AMR | 0x00000003, 83fcf5ef2aSThomas Huth /* Architecture 2.06 "degraded" (no 1T segments) */ 84fcf5ef2aSThomas Huth POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR 85fcf5ef2aSThomas Huth | 0x00000003, 86fcf5ef2aSThomas Huth /* Architecture 2.07 variant */ 87fcf5ef2aSThomas Huth POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG 88fcf5ef2aSThomas Huth | POWERPC_MMU_64K 89fcf5ef2aSThomas Huth | POWERPC_MMU_AMR | 0x00000004, 90fcf5ef2aSThomas Huth /* Architecture 2.07 "degraded" (no 1T segments) */ 91fcf5ef2aSThomas Huth POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR 92fcf5ef2aSThomas Huth | 0x00000004, 9386cf1e9fSSuraj Jitindar Singh /* Architecture 3.00 variant */ 9486cf1e9fSSuraj Jitindar Singh POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG 9586cf1e9fSSuraj Jitindar Singh | POWERPC_MMU_64K 96*0922f1e4SDavid Gibson | POWERPC_MMU_AMR | POWERPC_MMU_V3 97*0922f1e4SDavid Gibson | 0x00000005, 98fcf5ef2aSThomas Huth }; 99fcf5ef2aSThomas Huth 100fcf5ef2aSThomas Huth /*****************************************************************************/ 101fcf5ef2aSThomas Huth /* Exception model */ 102fcf5ef2aSThomas Huth typedef enum powerpc_excp_t powerpc_excp_t; 103fcf5ef2aSThomas Huth enum powerpc_excp_t { 104fcf5ef2aSThomas Huth POWERPC_EXCP_UNKNOWN = 0, 105fcf5ef2aSThomas Huth /* Standard PowerPC exception model */ 106fcf5ef2aSThomas Huth POWERPC_EXCP_STD, 107fcf5ef2aSThomas Huth /* PowerPC 40x exception model */ 108fcf5ef2aSThomas Huth POWERPC_EXCP_40x, 109fcf5ef2aSThomas Huth /* PowerPC 601 exception model */ 110fcf5ef2aSThomas Huth POWERPC_EXCP_601, 111fcf5ef2aSThomas Huth /* PowerPC 602 exception model */ 112fcf5ef2aSThomas Huth POWERPC_EXCP_602, 113fcf5ef2aSThomas Huth /* PowerPC 603 exception model */ 114fcf5ef2aSThomas Huth POWERPC_EXCP_603, 115fcf5ef2aSThomas Huth /* PowerPC 603e exception model */ 116fcf5ef2aSThomas Huth POWERPC_EXCP_603E, 117fcf5ef2aSThomas Huth /* PowerPC G2 exception model */ 118fcf5ef2aSThomas Huth POWERPC_EXCP_G2, 119fcf5ef2aSThomas Huth /* PowerPC 604 exception model */ 120fcf5ef2aSThomas Huth POWERPC_EXCP_604, 121fcf5ef2aSThomas Huth /* PowerPC 7x0 exception model */ 122fcf5ef2aSThomas Huth POWERPC_EXCP_7x0, 123fcf5ef2aSThomas Huth /* PowerPC 7x5 exception model */ 124fcf5ef2aSThomas Huth POWERPC_EXCP_7x5, 125fcf5ef2aSThomas Huth /* PowerPC 74xx exception model */ 126fcf5ef2aSThomas Huth POWERPC_EXCP_74xx, 127fcf5ef2aSThomas Huth /* BookE exception model */ 128fcf5ef2aSThomas Huth POWERPC_EXCP_BOOKE, 129fcf5ef2aSThomas Huth /* PowerPC 970 exception model */ 130fcf5ef2aSThomas Huth POWERPC_EXCP_970, 131fcf5ef2aSThomas Huth /* POWER7 exception model */ 132fcf5ef2aSThomas Huth POWERPC_EXCP_POWER7, 133fcf5ef2aSThomas Huth /* POWER8 exception model */ 134fcf5ef2aSThomas Huth POWERPC_EXCP_POWER8, 135fcf5ef2aSThomas Huth }; 136fcf5ef2aSThomas Huth 137fcf5ef2aSThomas Huth /*****************************************************************************/ 138fcf5ef2aSThomas Huth /* PM instructions */ 139fcf5ef2aSThomas Huth typedef enum { 140fcf5ef2aSThomas Huth PPC_PM_DOZE, 141fcf5ef2aSThomas Huth PPC_PM_NAP, 142fcf5ef2aSThomas Huth PPC_PM_SLEEP, 143fcf5ef2aSThomas Huth PPC_PM_RVWINKLE, 144fcf5ef2aSThomas Huth } powerpc_pm_insn_t; 145fcf5ef2aSThomas Huth 146fcf5ef2aSThomas Huth /*****************************************************************************/ 147fcf5ef2aSThomas Huth /* Input pins model */ 148fcf5ef2aSThomas Huth typedef enum powerpc_input_t powerpc_input_t; 149fcf5ef2aSThomas Huth enum powerpc_input_t { 150fcf5ef2aSThomas Huth PPC_FLAGS_INPUT_UNKNOWN = 0, 151fcf5ef2aSThomas Huth /* PowerPC 6xx bus */ 152fcf5ef2aSThomas Huth PPC_FLAGS_INPUT_6xx, 153fcf5ef2aSThomas Huth /* BookE bus */ 154fcf5ef2aSThomas Huth PPC_FLAGS_INPUT_BookE, 155fcf5ef2aSThomas Huth /* PowerPC 405 bus */ 156fcf5ef2aSThomas Huth PPC_FLAGS_INPUT_405, 157fcf5ef2aSThomas Huth /* PowerPC 970 bus */ 158fcf5ef2aSThomas Huth PPC_FLAGS_INPUT_970, 159fcf5ef2aSThomas Huth /* PowerPC POWER7 bus */ 160fcf5ef2aSThomas Huth PPC_FLAGS_INPUT_POWER7, 161fcf5ef2aSThomas Huth /* PowerPC 401 bus */ 162fcf5ef2aSThomas Huth PPC_FLAGS_INPUT_401, 163fcf5ef2aSThomas Huth /* Freescale RCPU bus */ 164fcf5ef2aSThomas Huth PPC_FLAGS_INPUT_RCPU, 165fcf5ef2aSThomas Huth }; 166fcf5ef2aSThomas Huth 167fcf5ef2aSThomas Huth struct ppc_segment_page_sizes; 168fcf5ef2aSThomas Huth 169fcf5ef2aSThomas Huth /** 170fcf5ef2aSThomas Huth * PowerPCCPUClass: 171fcf5ef2aSThomas Huth * @parent_realize: The parent class' realize handler. 172fcf5ef2aSThomas Huth * @parent_reset: The parent class' reset handler. 173fcf5ef2aSThomas Huth * 174fcf5ef2aSThomas Huth * A PowerPC CPU model. 175fcf5ef2aSThomas Huth */ 176fcf5ef2aSThomas Huth typedef struct PowerPCCPUClass { 177fcf5ef2aSThomas Huth /*< private >*/ 178fcf5ef2aSThomas Huth CPUClass parent_class; 179fcf5ef2aSThomas Huth /*< public >*/ 180fcf5ef2aSThomas Huth 181fcf5ef2aSThomas Huth DeviceRealize parent_realize; 182fcf5ef2aSThomas Huth DeviceUnrealize parent_unrealize; 183fcf5ef2aSThomas Huth void (*parent_reset)(CPUState *cpu); 184fcf5ef2aSThomas Huth 185fcf5ef2aSThomas Huth uint32_t pvr; 186fcf5ef2aSThomas Huth bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr); 187fcf5ef2aSThomas Huth uint64_t pcr_mask; /* Available bits in PCR register */ 188fcf5ef2aSThomas Huth uint64_t pcr_supported; /* Bits for supported PowerISA versions */ 189fcf5ef2aSThomas Huth uint32_t svr; 190fcf5ef2aSThomas Huth uint64_t insns_flags; 191fcf5ef2aSThomas Huth uint64_t insns_flags2; 192fcf5ef2aSThomas Huth uint64_t msr_mask; 193fcf5ef2aSThomas Huth powerpc_mmu_t mmu_model; 194fcf5ef2aSThomas Huth powerpc_excp_t excp_model; 195fcf5ef2aSThomas Huth powerpc_input_t bus_model; 196fcf5ef2aSThomas Huth uint32_t flags; 197fcf5ef2aSThomas Huth int bfd_mach; 198fcf5ef2aSThomas Huth uint32_t l1_dcache_size, l1_icache_size; 199fcf5ef2aSThomas Huth const struct ppc_segment_page_sizes *sps; 200fcf5ef2aSThomas Huth void (*init_proc)(CPUPPCState *env); 201fcf5ef2aSThomas Huth int (*check_pow)(CPUPPCState *env); 202fcf5ef2aSThomas Huth int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx); 203fcf5ef2aSThomas Huth bool (*interrupts_big_endian)(PowerPCCPU *cpu); 204fcf5ef2aSThomas Huth } PowerPCCPUClass; 205fcf5ef2aSThomas Huth 206fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 207fcf5ef2aSThomas Huth typedef struct PPCTimebase { 208fcf5ef2aSThomas Huth uint64_t guest_timebase; 209fcf5ef2aSThomas Huth int64_t time_of_the_day_ns; 210fcf5ef2aSThomas Huth } PPCTimebase; 211fcf5ef2aSThomas Huth 212fcf5ef2aSThomas Huth extern const struct VMStateDescription vmstate_ppc_timebase; 213fcf5ef2aSThomas Huth 214fcf5ef2aSThomas Huth #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \ 215fcf5ef2aSThomas Huth .name = (stringify(_field)), \ 216fcf5ef2aSThomas Huth .version_id = (_version), \ 217fcf5ef2aSThomas Huth .size = sizeof(PPCTimebase), \ 218fcf5ef2aSThomas Huth .vmsd = &vmstate_ppc_timebase, \ 219fcf5ef2aSThomas Huth .flags = VMS_STRUCT, \ 220fcf5ef2aSThomas Huth .offset = vmstate_offset_value(_state, _field, PPCTimebase), \ 221fcf5ef2aSThomas Huth } 22242043e4fSLaurent Vivier 22342043e4fSLaurent Vivier void cpu_ppc_clock_vm_state_change(void *opaque, int running, 22442043e4fSLaurent Vivier RunState state); 225fcf5ef2aSThomas Huth #endif 226fcf5ef2aSThomas Huth 227fcf5ef2aSThomas Huth #endif 228