1 /* 2 * OpenRISC translation 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * Feng Gao <gf91597@gmail.com> 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "disas/disas.h" 25 #include "tcg/tcg-op.h" 26 #include "qemu/log.h" 27 #include "qemu/bitops.h" 28 #include "qemu/qemu-print.h" 29 #include "exec/cpu_ldst.h" 30 #include "exec/translator.h" 31 32 #include "exec/helper-proto.h" 33 #include "exec/helper-gen.h" 34 35 #include "exec/log.h" 36 37 #define HELPER_H "helper.h" 38 #include "exec/helper-info.c.inc" 39 #undef HELPER_H 40 41 42 /* is_jmp field values */ 43 #define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */ 44 #define DISAS_JUMP DISAS_TARGET_1 /* exit via jmp_pc/jmp_pc_imm */ 45 46 typedef struct DisasContext { 47 DisasContextBase base; 48 uint32_t mem_idx; 49 uint32_t tb_flags; 50 uint32_t delayed_branch; 51 uint32_t cpucfgr; 52 uint32_t avr; 53 54 /* If not -1, jmp_pc contains this value and so is a direct jump. */ 55 target_ulong jmp_pc_imm; 56 57 /* The temporary corresponding to register 0 for this compilation. */ 58 TCGv R0; 59 /* The constant zero. */ 60 TCGv zero; 61 } DisasContext; 62 63 static inline bool is_user(DisasContext *dc) 64 { 65 #ifdef CONFIG_USER_ONLY 66 return true; 67 #else 68 return !(dc->tb_flags & TB_FLAGS_SM); 69 #endif 70 } 71 72 /* Include the auto-generated decoder. */ 73 #include "decode-insns.c.inc" 74 75 static TCGv cpu_sr; 76 static TCGv cpu_regs[32]; 77 static TCGv cpu_pc; 78 static TCGv jmp_pc; /* l.jr/l.jalr temp pc */ 79 static TCGv cpu_ppc; 80 static TCGv cpu_sr_f; /* bf/bnf, F flag taken */ 81 static TCGv cpu_sr_cy; /* carry (unsigned overflow) */ 82 static TCGv cpu_sr_ov; /* signed overflow */ 83 static TCGv cpu_lock_addr; 84 static TCGv cpu_lock_value; 85 static TCGv_i32 fpcsr; 86 static TCGv_i64 cpu_mac; /* MACHI:MACLO */ 87 static TCGv_i32 cpu_dflag; 88 89 void openrisc_translate_init(void) 90 { 91 static const char * const regnames[] = { 92 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 93 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 94 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 95 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 96 }; 97 int i; 98 99 cpu_sr = tcg_global_mem_new(cpu_env, 100 offsetof(CPUOpenRISCState, sr), "sr"); 101 cpu_dflag = tcg_global_mem_new_i32(cpu_env, 102 offsetof(CPUOpenRISCState, dflag), 103 "dflag"); 104 cpu_pc = tcg_global_mem_new(cpu_env, 105 offsetof(CPUOpenRISCState, pc), "pc"); 106 cpu_ppc = tcg_global_mem_new(cpu_env, 107 offsetof(CPUOpenRISCState, ppc), "ppc"); 108 jmp_pc = tcg_global_mem_new(cpu_env, 109 offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc"); 110 cpu_sr_f = tcg_global_mem_new(cpu_env, 111 offsetof(CPUOpenRISCState, sr_f), "sr_f"); 112 cpu_sr_cy = tcg_global_mem_new(cpu_env, 113 offsetof(CPUOpenRISCState, sr_cy), "sr_cy"); 114 cpu_sr_ov = tcg_global_mem_new(cpu_env, 115 offsetof(CPUOpenRISCState, sr_ov), "sr_ov"); 116 cpu_lock_addr = tcg_global_mem_new(cpu_env, 117 offsetof(CPUOpenRISCState, lock_addr), 118 "lock_addr"); 119 cpu_lock_value = tcg_global_mem_new(cpu_env, 120 offsetof(CPUOpenRISCState, lock_value), 121 "lock_value"); 122 fpcsr = tcg_global_mem_new_i32(cpu_env, 123 offsetof(CPUOpenRISCState, fpcsr), 124 "fpcsr"); 125 cpu_mac = tcg_global_mem_new_i64(cpu_env, 126 offsetof(CPUOpenRISCState, mac), 127 "mac"); 128 for (i = 0; i < 32; i++) { 129 cpu_regs[i] = tcg_global_mem_new(cpu_env, 130 offsetof(CPUOpenRISCState, 131 shadow_gpr[0][i]), 132 regnames[i]); 133 } 134 } 135 136 static void gen_exception(DisasContext *dc, unsigned int excp) 137 { 138 gen_helper_exception(cpu_env, tcg_constant_i32(excp)); 139 } 140 141 static void gen_illegal_exception(DisasContext *dc) 142 { 143 tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); 144 gen_exception(dc, EXCP_ILLEGAL); 145 dc->base.is_jmp = DISAS_NORETURN; 146 } 147 148 static bool check_v1_3(DisasContext *dc) 149 { 150 return dc->avr >= 0x01030000; 151 } 152 153 static bool check_of32s(DisasContext *dc) 154 { 155 return dc->cpucfgr & CPUCFGR_OF32S; 156 } 157 158 static bool check_of64a32s(DisasContext *dc) 159 { 160 return dc->cpucfgr & CPUCFGR_OF64A32S; 161 } 162 163 static TCGv cpu_R(DisasContext *dc, int reg) 164 { 165 if (reg == 0) { 166 return dc->R0; 167 } else { 168 return cpu_regs[reg]; 169 } 170 } 171 172 /* 173 * We're about to write to REG. On the off-chance that the user is 174 * writing to R0, re-instate the architectural register. 175 */ 176 static void check_r0_write(DisasContext *dc, int reg) 177 { 178 if (unlikely(reg == 0)) { 179 dc->R0 = cpu_regs[0]; 180 } 181 } 182 183 static void gen_ove_cy(DisasContext *dc) 184 { 185 if (dc->tb_flags & SR_OVE) { 186 gen_helper_ove_cy(cpu_env); 187 } 188 } 189 190 static void gen_ove_ov(DisasContext *dc) 191 { 192 if (dc->tb_flags & SR_OVE) { 193 gen_helper_ove_ov(cpu_env); 194 } 195 } 196 197 static void gen_ove_cyov(DisasContext *dc) 198 { 199 if (dc->tb_flags & SR_OVE) { 200 gen_helper_ove_cyov(cpu_env); 201 } 202 } 203 204 static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) 205 { 206 TCGv t0 = tcg_temp_new(); 207 TCGv res = tcg_temp_new(); 208 209 tcg_gen_add2_tl(res, cpu_sr_cy, srca, dc->zero, srcb, dc->zero); 210 tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); 211 tcg_gen_xor_tl(t0, res, srcb); 212 tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); 213 214 tcg_gen_mov_tl(dest, res); 215 216 gen_ove_cyov(dc); 217 } 218 219 static void gen_addc(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) 220 { 221 TCGv t0 = tcg_temp_new(); 222 TCGv res = tcg_temp_new(); 223 224 tcg_gen_add2_tl(res, cpu_sr_cy, srca, dc->zero, cpu_sr_cy, dc->zero); 225 tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, dc->zero); 226 tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); 227 tcg_gen_xor_tl(t0, res, srcb); 228 tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); 229 230 tcg_gen_mov_tl(dest, res); 231 232 gen_ove_cyov(dc); 233 } 234 235 static void gen_sub(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) 236 { 237 TCGv res = tcg_temp_new(); 238 239 tcg_gen_sub_tl(res, srca, srcb); 240 tcg_gen_xor_tl(cpu_sr_cy, srca, srcb); 241 tcg_gen_xor_tl(cpu_sr_ov, res, srcb); 242 tcg_gen_and_tl(cpu_sr_ov, cpu_sr_ov, cpu_sr_cy); 243 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_cy, srca, srcb); 244 245 tcg_gen_mov_tl(dest, res); 246 247 gen_ove_cyov(dc); 248 } 249 250 static void gen_mul(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) 251 { 252 TCGv t0 = tcg_temp_new(); 253 254 tcg_gen_muls2_tl(dest, cpu_sr_ov, srca, srcb); 255 tcg_gen_sari_tl(t0, dest, TARGET_LONG_BITS - 1); 256 tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_ov, cpu_sr_ov, t0); 257 258 tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); 259 gen_ove_ov(dc); 260 } 261 262 static void gen_mulu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) 263 { 264 tcg_gen_muls2_tl(dest, cpu_sr_cy, srca, srcb); 265 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_cy, cpu_sr_cy, 0); 266 267 gen_ove_cy(dc); 268 } 269 270 static void gen_div(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) 271 { 272 TCGv t0 = tcg_temp_new(); 273 274 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_ov, srcb, 0); 275 /* The result of divide-by-zero is undefined. 276 Supress the host-side exception by dividing by 1. */ 277 tcg_gen_or_tl(t0, srcb, cpu_sr_ov); 278 tcg_gen_div_tl(dest, srca, t0); 279 280 tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); 281 gen_ove_ov(dc); 282 } 283 284 static void gen_divu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) 285 { 286 TCGv t0 = tcg_temp_new(); 287 288 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_cy, srcb, 0); 289 /* The result of divide-by-zero is undefined. 290 Supress the host-side exception by dividing by 1. */ 291 tcg_gen_or_tl(t0, srcb, cpu_sr_cy); 292 tcg_gen_divu_tl(dest, srca, t0); 293 294 gen_ove_cy(dc); 295 } 296 297 static void gen_muld(DisasContext *dc, TCGv srca, TCGv srcb) 298 { 299 TCGv_i64 t1 = tcg_temp_new_i64(); 300 TCGv_i64 t2 = tcg_temp_new_i64(); 301 302 tcg_gen_ext_tl_i64(t1, srca); 303 tcg_gen_ext_tl_i64(t2, srcb); 304 if (TARGET_LONG_BITS == 32) { 305 tcg_gen_mul_i64(cpu_mac, t1, t2); 306 tcg_gen_movi_tl(cpu_sr_ov, 0); 307 } else { 308 TCGv_i64 high = tcg_temp_new_i64(); 309 310 tcg_gen_muls2_i64(cpu_mac, high, t1, t2); 311 tcg_gen_sari_i64(t1, cpu_mac, 63); 312 tcg_gen_setcond_i64(TCG_COND_NE, t1, t1, high); 313 tcg_gen_trunc_i64_tl(cpu_sr_ov, t1); 314 tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); 315 316 gen_ove_ov(dc); 317 } 318 } 319 320 static void gen_muldu(DisasContext *dc, TCGv srca, TCGv srcb) 321 { 322 TCGv_i64 t1 = tcg_temp_new_i64(); 323 TCGv_i64 t2 = tcg_temp_new_i64(); 324 325 tcg_gen_extu_tl_i64(t1, srca); 326 tcg_gen_extu_tl_i64(t2, srcb); 327 if (TARGET_LONG_BITS == 32) { 328 tcg_gen_mul_i64(cpu_mac, t1, t2); 329 tcg_gen_movi_tl(cpu_sr_cy, 0); 330 } else { 331 TCGv_i64 high = tcg_temp_new_i64(); 332 333 tcg_gen_mulu2_i64(cpu_mac, high, t1, t2); 334 tcg_gen_setcondi_i64(TCG_COND_NE, high, high, 0); 335 tcg_gen_trunc_i64_tl(cpu_sr_cy, high); 336 337 gen_ove_cy(dc); 338 } 339 } 340 341 static void gen_mac(DisasContext *dc, TCGv srca, TCGv srcb) 342 { 343 TCGv_i64 t1 = tcg_temp_new_i64(); 344 TCGv_i64 t2 = tcg_temp_new_i64(); 345 346 tcg_gen_ext_tl_i64(t1, srca); 347 tcg_gen_ext_tl_i64(t2, srcb); 348 tcg_gen_mul_i64(t1, t1, t2); 349 350 /* Note that overflow is only computed during addition stage. */ 351 tcg_gen_xor_i64(t2, cpu_mac, t1); 352 tcg_gen_add_i64(cpu_mac, cpu_mac, t1); 353 tcg_gen_xor_i64(t1, t1, cpu_mac); 354 tcg_gen_andc_i64(t1, t1, t2); 355 356 #if TARGET_LONG_BITS == 32 357 tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); 358 #else 359 tcg_gen_mov_i64(cpu_sr_ov, t1); 360 #endif 361 362 gen_ove_ov(dc); 363 } 364 365 static void gen_macu(DisasContext *dc, TCGv srca, TCGv srcb) 366 { 367 TCGv_i64 t1 = tcg_temp_new_i64(); 368 TCGv_i64 t2 = tcg_temp_new_i64(); 369 370 tcg_gen_extu_tl_i64(t1, srca); 371 tcg_gen_extu_tl_i64(t2, srcb); 372 tcg_gen_mul_i64(t1, t1, t2); 373 374 /* Note that overflow is only computed during addition stage. */ 375 tcg_gen_add_i64(cpu_mac, cpu_mac, t1); 376 tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1); 377 tcg_gen_trunc_i64_tl(cpu_sr_cy, t1); 378 379 gen_ove_cy(dc); 380 } 381 382 static void gen_msb(DisasContext *dc, TCGv srca, TCGv srcb) 383 { 384 TCGv_i64 t1 = tcg_temp_new_i64(); 385 TCGv_i64 t2 = tcg_temp_new_i64(); 386 387 tcg_gen_ext_tl_i64(t1, srca); 388 tcg_gen_ext_tl_i64(t2, srcb); 389 tcg_gen_mul_i64(t1, t1, t2); 390 391 /* Note that overflow is only computed during subtraction stage. */ 392 tcg_gen_xor_i64(t2, cpu_mac, t1); 393 tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); 394 tcg_gen_xor_i64(t1, t1, cpu_mac); 395 tcg_gen_and_i64(t1, t1, t2); 396 397 #if TARGET_LONG_BITS == 32 398 tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); 399 #else 400 tcg_gen_mov_i64(cpu_sr_ov, t1); 401 #endif 402 403 gen_ove_ov(dc); 404 } 405 406 static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb) 407 { 408 TCGv_i64 t1 = tcg_temp_new_i64(); 409 TCGv_i64 t2 = tcg_temp_new_i64(); 410 411 tcg_gen_extu_tl_i64(t1, srca); 412 tcg_gen_extu_tl_i64(t2, srcb); 413 tcg_gen_mul_i64(t1, t1, t2); 414 415 /* Note that overflow is only computed during subtraction stage. */ 416 tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1); 417 tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); 418 tcg_gen_trunc_i64_tl(cpu_sr_cy, t2); 419 420 gen_ove_cy(dc); 421 } 422 423 static bool trans_l_add(DisasContext *dc, arg_dab *a) 424 { 425 check_r0_write(dc, a->d); 426 gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); 427 return true; 428 } 429 430 static bool trans_l_addc(DisasContext *dc, arg_dab *a) 431 { 432 check_r0_write(dc, a->d); 433 gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); 434 return true; 435 } 436 437 static bool trans_l_sub(DisasContext *dc, arg_dab *a) 438 { 439 check_r0_write(dc, a->d); 440 gen_sub(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); 441 return true; 442 } 443 444 static bool trans_l_and(DisasContext *dc, arg_dab *a) 445 { 446 check_r0_write(dc, a->d); 447 tcg_gen_and_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); 448 return true; 449 } 450 451 static bool trans_l_or(DisasContext *dc, arg_dab *a) 452 { 453 check_r0_write(dc, a->d); 454 tcg_gen_or_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); 455 return true; 456 } 457 458 static bool trans_l_xor(DisasContext *dc, arg_dab *a) 459 { 460 check_r0_write(dc, a->d); 461 tcg_gen_xor_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); 462 return true; 463 } 464 465 static bool trans_l_sll(DisasContext *dc, arg_dab *a) 466 { 467 check_r0_write(dc, a->d); 468 tcg_gen_shl_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); 469 return true; 470 } 471 472 static bool trans_l_srl(DisasContext *dc, arg_dab *a) 473 { 474 check_r0_write(dc, a->d); 475 tcg_gen_shr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); 476 return true; 477 } 478 479 static bool trans_l_sra(DisasContext *dc, arg_dab *a) 480 { 481 check_r0_write(dc, a->d); 482 tcg_gen_sar_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); 483 return true; 484 } 485 486 static bool trans_l_ror(DisasContext *dc, arg_dab *a) 487 { 488 check_r0_write(dc, a->d); 489 tcg_gen_rotr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); 490 return true; 491 } 492 493 static bool trans_l_exths(DisasContext *dc, arg_da *a) 494 { 495 check_r0_write(dc, a->d); 496 tcg_gen_ext16s_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); 497 return true; 498 } 499 500 static bool trans_l_extbs(DisasContext *dc, arg_da *a) 501 { 502 check_r0_write(dc, a->d); 503 tcg_gen_ext8s_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); 504 return true; 505 } 506 507 static bool trans_l_exthz(DisasContext *dc, arg_da *a) 508 { 509 check_r0_write(dc, a->d); 510 tcg_gen_ext16u_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); 511 return true; 512 } 513 514 static bool trans_l_extbz(DisasContext *dc, arg_da *a) 515 { 516 check_r0_write(dc, a->d); 517 tcg_gen_ext8u_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); 518 return true; 519 } 520 521 static bool trans_l_cmov(DisasContext *dc, arg_dab *a) 522 { 523 check_r0_write(dc, a->d); 524 tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, dc->zero, 525 cpu_R(dc, a->a), cpu_R(dc, a->b)); 526 return true; 527 } 528 529 static bool trans_l_ff1(DisasContext *dc, arg_da *a) 530 { 531 check_r0_write(dc, a->d); 532 tcg_gen_ctzi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), -1); 533 tcg_gen_addi_tl(cpu_R(dc, a->d), cpu_R(dc, a->d), 1); 534 return true; 535 } 536 537 static bool trans_l_fl1(DisasContext *dc, arg_da *a) 538 { 539 check_r0_write(dc, a->d); 540 tcg_gen_clzi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), TARGET_LONG_BITS); 541 tcg_gen_subfi_tl(cpu_R(dc, a->d), TARGET_LONG_BITS, cpu_R(dc, a->d)); 542 return true; 543 } 544 545 static bool trans_l_mul(DisasContext *dc, arg_dab *a) 546 { 547 check_r0_write(dc, a->d); 548 gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); 549 return true; 550 } 551 552 static bool trans_l_mulu(DisasContext *dc, arg_dab *a) 553 { 554 check_r0_write(dc, a->d); 555 gen_mulu(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); 556 return true; 557 } 558 559 static bool trans_l_div(DisasContext *dc, arg_dab *a) 560 { 561 check_r0_write(dc, a->d); 562 gen_div(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); 563 return true; 564 } 565 566 static bool trans_l_divu(DisasContext *dc, arg_dab *a) 567 { 568 check_r0_write(dc, a->d); 569 gen_divu(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); 570 return true; 571 } 572 573 static bool trans_l_muld(DisasContext *dc, arg_ab *a) 574 { 575 gen_muld(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); 576 return true; 577 } 578 579 static bool trans_l_muldu(DisasContext *dc, arg_ab *a) 580 { 581 gen_muldu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); 582 return true; 583 } 584 585 static bool trans_l_j(DisasContext *dc, arg_l_j *a) 586 { 587 target_ulong tmp_pc = dc->base.pc_next + a->n * 4; 588 589 tcg_gen_movi_tl(jmp_pc, tmp_pc); 590 dc->jmp_pc_imm = tmp_pc; 591 dc->delayed_branch = 2; 592 return true; 593 } 594 595 static bool trans_l_jal(DisasContext *dc, arg_l_jal *a) 596 { 597 target_ulong tmp_pc = dc->base.pc_next + a->n * 4; 598 target_ulong ret_pc = dc->base.pc_next + 8; 599 600 tcg_gen_movi_tl(cpu_regs[9], ret_pc); 601 /* Optimize jal being used to load the PC for PIC. */ 602 if (tmp_pc != ret_pc) { 603 tcg_gen_movi_tl(jmp_pc, tmp_pc); 604 dc->jmp_pc_imm = tmp_pc; 605 dc->delayed_branch = 2; 606 } 607 return true; 608 } 609 610 static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond) 611 { 612 target_ulong tmp_pc = dc->base.pc_next + a->n * 4; 613 TCGv t_next = tcg_constant_tl(dc->base.pc_next + 8); 614 TCGv t_true = tcg_constant_tl(tmp_pc); 615 616 tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, dc->zero, t_true, t_next); 617 dc->delayed_branch = 2; 618 } 619 620 static bool trans_l_bf(DisasContext *dc, arg_l_bf *a) 621 { 622 do_bf(dc, a, TCG_COND_NE); 623 return true; 624 } 625 626 static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a) 627 { 628 do_bf(dc, a, TCG_COND_EQ); 629 return true; 630 } 631 632 static bool trans_l_jr(DisasContext *dc, arg_l_jr *a) 633 { 634 tcg_gen_mov_tl(jmp_pc, cpu_R(dc, a->b)); 635 dc->delayed_branch = 2; 636 return true; 637 } 638 639 static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a) 640 { 641 tcg_gen_mov_tl(jmp_pc, cpu_R(dc, a->b)); 642 tcg_gen_movi_tl(cpu_regs[9], dc->base.pc_next + 8); 643 dc->delayed_branch = 2; 644 return true; 645 } 646 647 static bool trans_l_lwa(DisasContext *dc, arg_load *a) 648 { 649 TCGv ea; 650 651 check_r0_write(dc, a->d); 652 ea = tcg_temp_new(); 653 tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); 654 tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, MO_TEUL); 655 tcg_gen_mov_tl(cpu_lock_addr, ea); 656 tcg_gen_mov_tl(cpu_lock_value, cpu_R(dc, a->d)); 657 return true; 658 } 659 660 static void do_load(DisasContext *dc, arg_load *a, MemOp mop) 661 { 662 TCGv ea; 663 664 check_r0_write(dc, a->d); 665 ea = tcg_temp_new(); 666 tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); 667 tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, mop); 668 } 669 670 static bool trans_l_lwz(DisasContext *dc, arg_load *a) 671 { 672 do_load(dc, a, MO_TEUL); 673 return true; 674 } 675 676 static bool trans_l_lws(DisasContext *dc, arg_load *a) 677 { 678 do_load(dc, a, MO_TESL); 679 return true; 680 } 681 682 static bool trans_l_lbz(DisasContext *dc, arg_load *a) 683 { 684 do_load(dc, a, MO_UB); 685 return true; 686 } 687 688 static bool trans_l_lbs(DisasContext *dc, arg_load *a) 689 { 690 do_load(dc, a, MO_SB); 691 return true; 692 } 693 694 static bool trans_l_lhz(DisasContext *dc, arg_load *a) 695 { 696 do_load(dc, a, MO_TEUW); 697 return true; 698 } 699 700 static bool trans_l_lhs(DisasContext *dc, arg_load *a) 701 { 702 do_load(dc, a, MO_TESW); 703 return true; 704 } 705 706 static bool trans_l_swa(DisasContext *dc, arg_store *a) 707 { 708 TCGv ea, val; 709 TCGLabel *lab_fail, *lab_done; 710 711 ea = tcg_temp_new(); 712 tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); 713 714 lab_fail = gen_new_label(); 715 lab_done = gen_new_label(); 716 tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); 717 718 val = tcg_temp_new(); 719 tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, 720 cpu_R(dc, a->b), dc->mem_idx, MO_TEUL); 721 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); 722 723 tcg_gen_br(lab_done); 724 725 gen_set_label(lab_fail); 726 tcg_gen_movi_tl(cpu_sr_f, 0); 727 728 gen_set_label(lab_done); 729 tcg_gen_movi_tl(cpu_lock_addr, -1); 730 return true; 731 } 732 733 static void do_store(DisasContext *dc, arg_store *a, MemOp mop) 734 { 735 TCGv t0 = tcg_temp_new(); 736 tcg_gen_addi_tl(t0, cpu_R(dc, a->a), a->i); 737 tcg_gen_qemu_st_tl(cpu_R(dc, a->b), t0, dc->mem_idx, mop); 738 } 739 740 static bool trans_l_sw(DisasContext *dc, arg_store *a) 741 { 742 do_store(dc, a, MO_TEUL); 743 return true; 744 } 745 746 static bool trans_l_sb(DisasContext *dc, arg_store *a) 747 { 748 do_store(dc, a, MO_UB); 749 return true; 750 } 751 752 static bool trans_l_sh(DisasContext *dc, arg_store *a) 753 { 754 do_store(dc, a, MO_TEUW); 755 return true; 756 } 757 758 static bool trans_l_nop(DisasContext *dc, arg_l_nop *a) 759 { 760 return true; 761 } 762 763 static bool trans_l_adrp(DisasContext *dc, arg_l_adrp *a) 764 { 765 if (!check_v1_3(dc)) { 766 return false; 767 } 768 check_r0_write(dc, a->d); 769 770 tcg_gen_movi_i32(cpu_R(dc, a->d), 771 (dc->base.pc_next & TARGET_PAGE_MASK) + 772 ((target_long)a->i << TARGET_PAGE_BITS)); 773 return true; 774 } 775 776 static bool trans_l_addi(DisasContext *dc, arg_rri *a) 777 { 778 check_r0_write(dc, a->d); 779 gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i)); 780 return true; 781 } 782 783 static bool trans_l_addic(DisasContext *dc, arg_rri *a) 784 { 785 check_r0_write(dc, a->d); 786 gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i)); 787 return true; 788 } 789 790 static bool trans_l_muli(DisasContext *dc, arg_rri *a) 791 { 792 check_r0_write(dc, a->d); 793 gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i)); 794 return true; 795 } 796 797 static bool trans_l_maci(DisasContext *dc, arg_l_maci *a) 798 { 799 gen_mac(dc, cpu_R(dc, a->a), tcg_constant_tl(a->i)); 800 return true; 801 } 802 803 static bool trans_l_andi(DisasContext *dc, arg_rrk *a) 804 { 805 check_r0_write(dc, a->d); 806 tcg_gen_andi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->k); 807 return true; 808 } 809 810 static bool trans_l_ori(DisasContext *dc, arg_rrk *a) 811 { 812 check_r0_write(dc, a->d); 813 tcg_gen_ori_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->k); 814 return true; 815 } 816 817 static bool trans_l_xori(DisasContext *dc, arg_rri *a) 818 { 819 check_r0_write(dc, a->d); 820 tcg_gen_xori_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->i); 821 return true; 822 } 823 824 static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a) 825 { 826 TCGv spr = tcg_temp_new(); 827 828 check_r0_write(dc, a->d); 829 830 if (translator_io_start(&dc->base)) { 831 if (dc->delayed_branch) { 832 tcg_gen_mov_tl(cpu_pc, jmp_pc); 833 tcg_gen_discard_tl(jmp_pc); 834 } else { 835 tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); 836 } 837 dc->base.is_jmp = DISAS_EXIT; 838 } 839 840 tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); 841 gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr); 842 return true; 843 } 844 845 static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) 846 { 847 TCGv spr = tcg_temp_new(); 848 849 translator_io_start(&dc->base); 850 851 /* 852 * For SR, we will need to exit the TB to recognize the new 853 * exception state. For NPC, in theory this counts as a branch 854 * (although the SPR only exists for use by an ICE). Save all 855 * of the cpu state first, allowing it to be overwritten. 856 */ 857 if (dc->delayed_branch) { 858 tcg_gen_mov_tl(cpu_pc, jmp_pc); 859 tcg_gen_discard_tl(jmp_pc); 860 } else { 861 tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); 862 } 863 dc->base.is_jmp = DISAS_EXIT; 864 865 tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); 866 gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b)); 867 return true; 868 } 869 870 static bool trans_l_mac(DisasContext *dc, arg_ab *a) 871 { 872 gen_mac(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); 873 return true; 874 } 875 876 static bool trans_l_msb(DisasContext *dc, arg_ab *a) 877 { 878 gen_msb(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); 879 return true; 880 } 881 882 static bool trans_l_macu(DisasContext *dc, arg_ab *a) 883 { 884 gen_macu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); 885 return true; 886 } 887 888 static bool trans_l_msbu(DisasContext *dc, arg_ab *a) 889 { 890 gen_msbu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); 891 return true; 892 } 893 894 static bool trans_l_slli(DisasContext *dc, arg_dal *a) 895 { 896 check_r0_write(dc, a->d); 897 tcg_gen_shli_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), 898 a->l & (TARGET_LONG_BITS - 1)); 899 return true; 900 } 901 902 static bool trans_l_srli(DisasContext *dc, arg_dal *a) 903 { 904 check_r0_write(dc, a->d); 905 tcg_gen_shri_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), 906 a->l & (TARGET_LONG_BITS - 1)); 907 return true; 908 } 909 910 static bool trans_l_srai(DisasContext *dc, arg_dal *a) 911 { 912 check_r0_write(dc, a->d); 913 tcg_gen_sari_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), 914 a->l & (TARGET_LONG_BITS - 1)); 915 return true; 916 } 917 918 static bool trans_l_rori(DisasContext *dc, arg_dal *a) 919 { 920 check_r0_write(dc, a->d); 921 tcg_gen_rotri_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), 922 a->l & (TARGET_LONG_BITS - 1)); 923 return true; 924 } 925 926 static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a) 927 { 928 check_r0_write(dc, a->d); 929 tcg_gen_movi_tl(cpu_R(dc, a->d), a->k << 16); 930 return true; 931 } 932 933 static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a) 934 { 935 check_r0_write(dc, a->d); 936 tcg_gen_trunc_i64_tl(cpu_R(dc, a->d), cpu_mac); 937 tcg_gen_movi_i64(cpu_mac, 0); 938 return true; 939 } 940 941 static bool trans_l_sfeq(DisasContext *dc, arg_ab *a) 942 { 943 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, 944 cpu_R(dc, a->a), cpu_R(dc, a->b)); 945 return true; 946 } 947 948 static bool trans_l_sfne(DisasContext *dc, arg_ab *a) 949 { 950 tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, 951 cpu_R(dc, a->a), cpu_R(dc, a->b)); 952 return true; 953 } 954 955 static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a) 956 { 957 tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, 958 cpu_R(dc, a->a), cpu_R(dc, a->b)); 959 return true; 960 } 961 962 static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a) 963 { 964 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, 965 cpu_R(dc, a->a), cpu_R(dc, a->b)); 966 return true; 967 } 968 969 static bool trans_l_sfltu(DisasContext *dc, arg_ab *a) 970 { 971 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, 972 cpu_R(dc, a->a), cpu_R(dc, a->b)); 973 return true; 974 } 975 976 static bool trans_l_sfleu(DisasContext *dc, arg_ab *a) 977 { 978 tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, 979 cpu_R(dc, a->a), cpu_R(dc, a->b)); 980 return true; 981 } 982 983 static bool trans_l_sfgts(DisasContext *dc, arg_ab *a) 984 { 985 tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, 986 cpu_R(dc, a->a), cpu_R(dc, a->b)); 987 return true; 988 } 989 990 static bool trans_l_sfges(DisasContext *dc, arg_ab *a) 991 { 992 tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, 993 cpu_R(dc, a->a), cpu_R(dc, a->b)); 994 return true; 995 } 996 997 static bool trans_l_sflts(DisasContext *dc, arg_ab *a) 998 { 999 tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, 1000 cpu_R(dc, a->a), cpu_R(dc, a->b)); 1001 return true; 1002 } 1003 1004 static bool trans_l_sfles(DisasContext *dc, arg_ab *a) 1005 { 1006 tcg_gen_setcond_tl(TCG_COND_LE, 1007 cpu_sr_f, cpu_R(dc, a->a), cpu_R(dc, a->b)); 1008 return true; 1009 } 1010 1011 static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a) 1012 { 1013 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R(dc, a->a), a->i); 1014 return true; 1015 } 1016 1017 static bool trans_l_sfnei(DisasContext *dc, arg_ai *a) 1018 { 1019 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R(dc, a->a), a->i); 1020 return true; 1021 } 1022 1023 static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a) 1024 { 1025 tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R(dc, a->a), a->i); 1026 return true; 1027 } 1028 1029 static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a) 1030 { 1031 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R(dc, a->a), a->i); 1032 return true; 1033 } 1034 1035 static bool trans_l_sfltui(DisasContext *dc, arg_ai *a) 1036 { 1037 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R(dc, a->a), a->i); 1038 return true; 1039 } 1040 1041 static bool trans_l_sfleui(DisasContext *dc, arg_ai *a) 1042 { 1043 tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R(dc, a->a), a->i); 1044 return true; 1045 } 1046 1047 static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a) 1048 { 1049 tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R(dc, a->a), a->i); 1050 return true; 1051 } 1052 1053 static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a) 1054 { 1055 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R(dc, a->a), a->i); 1056 return true; 1057 } 1058 1059 static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a) 1060 { 1061 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R(dc, a->a), a->i); 1062 return true; 1063 } 1064 1065 static bool trans_l_sflesi(DisasContext *dc, arg_ai *a) 1066 { 1067 tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R(dc, a->a), a->i); 1068 return true; 1069 } 1070 1071 static bool trans_l_sys(DisasContext *dc, arg_l_sys *a) 1072 { 1073 tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); 1074 gen_exception(dc, EXCP_SYSCALL); 1075 dc->base.is_jmp = DISAS_NORETURN; 1076 return true; 1077 } 1078 1079 static bool trans_l_trap(DisasContext *dc, arg_l_trap *a) 1080 { 1081 tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); 1082 gen_exception(dc, EXCP_TRAP); 1083 dc->base.is_jmp = DISAS_NORETURN; 1084 return true; 1085 } 1086 1087 static bool trans_l_msync(DisasContext *dc, arg_l_msync *a) 1088 { 1089 tcg_gen_mb(TCG_MO_ALL); 1090 return true; 1091 } 1092 1093 static bool trans_l_psync(DisasContext *dc, arg_l_psync *a) 1094 { 1095 return true; 1096 } 1097 1098 static bool trans_l_csync(DisasContext *dc, arg_l_csync *a) 1099 { 1100 return true; 1101 } 1102 1103 static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a) 1104 { 1105 if (is_user(dc)) { 1106 gen_illegal_exception(dc); 1107 } else { 1108 gen_helper_rfe(cpu_env); 1109 dc->base.is_jmp = DISAS_EXIT; 1110 } 1111 return true; 1112 } 1113 1114 static bool do_fp2(DisasContext *dc, arg_da *a, 1115 void (*fn)(TCGv, TCGv_env, TCGv)) 1116 { 1117 if (!check_of32s(dc)) { 1118 return false; 1119 } 1120 check_r0_write(dc, a->d); 1121 fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a)); 1122 gen_helper_update_fpcsr(cpu_env); 1123 return true; 1124 } 1125 1126 static bool do_fp3(DisasContext *dc, arg_dab *a, 1127 void (*fn)(TCGv, TCGv_env, TCGv, TCGv)) 1128 { 1129 if (!check_of32s(dc)) { 1130 return false; 1131 } 1132 check_r0_write(dc, a->d); 1133 fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); 1134 gen_helper_update_fpcsr(cpu_env); 1135 return true; 1136 } 1137 1138 static bool do_fpcmp(DisasContext *dc, arg_ab *a, 1139 void (*fn)(TCGv, TCGv_env, TCGv, TCGv), 1140 bool inv, bool swap) 1141 { 1142 if (!check_of32s(dc)) { 1143 return false; 1144 } 1145 if (swap) { 1146 fn(cpu_sr_f, cpu_env, cpu_R(dc, a->b), cpu_R(dc, a->a)); 1147 } else { 1148 fn(cpu_sr_f, cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); 1149 } 1150 if (inv) { 1151 tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); 1152 } 1153 gen_helper_update_fpcsr(cpu_env); 1154 return true; 1155 } 1156 1157 static bool trans_lf_add_s(DisasContext *dc, arg_dab *a) 1158 { 1159 return do_fp3(dc, a, gen_helper_float_add_s); 1160 } 1161 1162 static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a) 1163 { 1164 return do_fp3(dc, a, gen_helper_float_sub_s); 1165 } 1166 1167 static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a) 1168 { 1169 return do_fp3(dc, a, gen_helper_float_mul_s); 1170 } 1171 1172 static bool trans_lf_div_s(DisasContext *dc, arg_dab *a) 1173 { 1174 return do_fp3(dc, a, gen_helper_float_div_s); 1175 } 1176 1177 static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a) 1178 { 1179 return do_fp3(dc, a, gen_helper_float_rem_s); 1180 return true; 1181 } 1182 1183 static bool trans_lf_itof_s(DisasContext *dc, arg_da *a) 1184 { 1185 return do_fp2(dc, a, gen_helper_itofs); 1186 } 1187 1188 static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a) 1189 { 1190 return do_fp2(dc, a, gen_helper_ftois); 1191 } 1192 1193 static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a) 1194 { 1195 if (!check_of32s(dc)) { 1196 return false; 1197 } 1198 check_r0_write(dc, a->d); 1199 gen_helper_float_madd_s(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), 1200 cpu_R(dc, a->a), cpu_R(dc, a->b)); 1201 gen_helper_update_fpcsr(cpu_env); 1202 return true; 1203 } 1204 1205 static bool trans_lf_sfeq_s(DisasContext *dc, arg_ab *a) 1206 { 1207 return do_fpcmp(dc, a, gen_helper_float_eq_s, false, false); 1208 } 1209 1210 static bool trans_lf_sfne_s(DisasContext *dc, arg_ab *a) 1211 { 1212 return do_fpcmp(dc, a, gen_helper_float_eq_s, true, false); 1213 } 1214 1215 static bool trans_lf_sfgt_s(DisasContext *dc, arg_ab *a) 1216 { 1217 return do_fpcmp(dc, a, gen_helper_float_lt_s, false, true); 1218 } 1219 1220 static bool trans_lf_sfge_s(DisasContext *dc, arg_ab *a) 1221 { 1222 return do_fpcmp(dc, a, gen_helper_float_le_s, false, true); 1223 } 1224 1225 static bool trans_lf_sflt_s(DisasContext *dc, arg_ab *a) 1226 { 1227 return do_fpcmp(dc, a, gen_helper_float_lt_s, false, false); 1228 } 1229 1230 static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a) 1231 { 1232 return do_fpcmp(dc, a, gen_helper_float_le_s, false, false); 1233 } 1234 1235 static bool trans_lf_sfueq_s(DisasContext *dc, arg_ab *a) 1236 { 1237 if (!check_v1_3(dc)) { 1238 return false; 1239 } 1240 return do_fpcmp(dc, a, gen_helper_float_ueq_s, false, false); 1241 } 1242 1243 static bool trans_lf_sfult_s(DisasContext *dc, arg_ab *a) 1244 { 1245 if (!check_v1_3(dc)) { 1246 return false; 1247 } 1248 return do_fpcmp(dc, a, gen_helper_float_ult_s, false, false); 1249 } 1250 1251 static bool trans_lf_sfugt_s(DisasContext *dc, arg_ab *a) 1252 { 1253 if (!check_v1_3(dc)) { 1254 return false; 1255 } 1256 return do_fpcmp(dc, a, gen_helper_float_ult_s, false, true); 1257 } 1258 1259 static bool trans_lf_sfule_s(DisasContext *dc, arg_ab *a) 1260 { 1261 if (!check_v1_3(dc)) { 1262 return false; 1263 } 1264 return do_fpcmp(dc, a, gen_helper_float_ule_s, false, false); 1265 } 1266 1267 static bool trans_lf_sfuge_s(DisasContext *dc, arg_ab *a) 1268 { 1269 if (!check_v1_3(dc)) { 1270 return false; 1271 } 1272 return do_fpcmp(dc, a, gen_helper_float_ule_s, false, true); 1273 } 1274 1275 static bool trans_lf_sfun_s(DisasContext *dc, arg_ab *a) 1276 { 1277 if (!check_v1_3(dc)) { 1278 return false; 1279 } 1280 return do_fpcmp(dc, a, gen_helper_float_un_s, false, false); 1281 } 1282 1283 static bool check_pair(DisasContext *dc, int r, int p) 1284 { 1285 return r + 1 + p < 32; 1286 } 1287 1288 static void load_pair(DisasContext *dc, TCGv_i64 t, int r, int p) 1289 { 1290 tcg_gen_concat_i32_i64(t, cpu_R(dc, r + 1 + p), cpu_R(dc, r)); 1291 } 1292 1293 static void save_pair(DisasContext *dc, TCGv_i64 t, int r, int p) 1294 { 1295 tcg_gen_extr_i64_i32(cpu_R(dc, r + 1 + p), cpu_R(dc, r), t); 1296 } 1297 1298 static bool do_dp3(DisasContext *dc, arg_dab_pair *a, 1299 void (*fn)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64)) 1300 { 1301 TCGv_i64 t0, t1; 1302 1303 if (!check_of64a32s(dc) || 1304 !check_pair(dc, a->a, a->ap) || 1305 !check_pair(dc, a->b, a->bp) || 1306 !check_pair(dc, a->d, a->dp)) { 1307 return false; 1308 } 1309 check_r0_write(dc, a->d); 1310 1311 t0 = tcg_temp_new_i64(); 1312 t1 = tcg_temp_new_i64(); 1313 load_pair(dc, t0, a->a, a->ap); 1314 load_pair(dc, t1, a->b, a->bp); 1315 fn(t0, cpu_env, t0, t1); 1316 save_pair(dc, t0, a->d, a->dp); 1317 1318 gen_helper_update_fpcsr(cpu_env); 1319 return true; 1320 } 1321 1322 static bool do_dp2(DisasContext *dc, arg_da_pair *a, 1323 void (*fn)(TCGv_i64, TCGv_env, TCGv_i64)) 1324 { 1325 TCGv_i64 t0; 1326 1327 if (!check_of64a32s(dc) || 1328 !check_pair(dc, a->a, a->ap) || 1329 !check_pair(dc, a->d, a->dp)) { 1330 return false; 1331 } 1332 check_r0_write(dc, a->d); 1333 1334 t0 = tcg_temp_new_i64(); 1335 load_pair(dc, t0, a->a, a->ap); 1336 fn(t0, cpu_env, t0); 1337 save_pair(dc, t0, a->d, a->dp); 1338 1339 gen_helper_update_fpcsr(cpu_env); 1340 return true; 1341 } 1342 1343 static bool do_dpcmp(DisasContext *dc, arg_ab_pair *a, 1344 void (*fn)(TCGv, TCGv_env, TCGv_i64, TCGv_i64), 1345 bool inv, bool swap) 1346 { 1347 TCGv_i64 t0, t1; 1348 1349 if (!check_of64a32s(dc) || 1350 !check_pair(dc, a->a, a->ap) || 1351 !check_pair(dc, a->b, a->bp)) { 1352 return false; 1353 } 1354 1355 t0 = tcg_temp_new_i64(); 1356 t1 = tcg_temp_new_i64(); 1357 load_pair(dc, t0, a->a, a->ap); 1358 load_pair(dc, t1, a->b, a->bp); 1359 if (swap) { 1360 fn(cpu_sr_f, cpu_env, t1, t0); 1361 } else { 1362 fn(cpu_sr_f, cpu_env, t0, t1); 1363 } 1364 1365 if (inv) { 1366 tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); 1367 } 1368 gen_helper_update_fpcsr(cpu_env); 1369 return true; 1370 } 1371 1372 static bool trans_lf_add_d(DisasContext *dc, arg_dab_pair *a) 1373 { 1374 return do_dp3(dc, a, gen_helper_float_add_d); 1375 } 1376 1377 static bool trans_lf_sub_d(DisasContext *dc, arg_dab_pair *a) 1378 { 1379 return do_dp3(dc, a, gen_helper_float_sub_d); 1380 } 1381 1382 static bool trans_lf_mul_d(DisasContext *dc, arg_dab_pair *a) 1383 { 1384 return do_dp3(dc, a, gen_helper_float_mul_d); 1385 } 1386 1387 static bool trans_lf_div_d(DisasContext *dc, arg_dab_pair *a) 1388 { 1389 return do_dp3(dc, a, gen_helper_float_div_d); 1390 } 1391 1392 static bool trans_lf_rem_d(DisasContext *dc, arg_dab_pair *a) 1393 { 1394 return do_dp3(dc, a, gen_helper_float_rem_d); 1395 } 1396 1397 static bool trans_lf_itof_d(DisasContext *dc, arg_da_pair *a) 1398 { 1399 return do_dp2(dc, a, gen_helper_itofd); 1400 } 1401 1402 static bool trans_lf_ftoi_d(DisasContext *dc, arg_da_pair *a) 1403 { 1404 return do_dp2(dc, a, gen_helper_ftoid); 1405 } 1406 1407 static bool trans_lf_stod_d(DisasContext *dc, arg_lf_stod_d *a) 1408 { 1409 TCGv_i64 t0; 1410 1411 if (!check_of64a32s(dc) || 1412 !check_pair(dc, a->d, a->dp)) { 1413 return false; 1414 } 1415 check_r0_write(dc, a->d); 1416 1417 t0 = tcg_temp_new_i64(); 1418 gen_helper_stod(t0, cpu_env, cpu_R(dc, a->a)); 1419 save_pair(dc, t0, a->d, a->dp); 1420 1421 gen_helper_update_fpcsr(cpu_env); 1422 return true; 1423 } 1424 1425 static bool trans_lf_dtos_d(DisasContext *dc, arg_lf_dtos_d *a) 1426 { 1427 TCGv_i64 t0; 1428 1429 if (!check_of64a32s(dc) || 1430 !check_pair(dc, a->a, a->ap)) { 1431 return false; 1432 } 1433 check_r0_write(dc, a->d); 1434 1435 t0 = tcg_temp_new_i64(); 1436 load_pair(dc, t0, a->a, a->ap); 1437 gen_helper_dtos(cpu_R(dc, a->d), cpu_env, t0); 1438 1439 gen_helper_update_fpcsr(cpu_env); 1440 return true; 1441 } 1442 1443 static bool trans_lf_madd_d(DisasContext *dc, arg_dab_pair *a) 1444 { 1445 TCGv_i64 t0, t1, t2; 1446 1447 if (!check_of64a32s(dc) || 1448 !check_pair(dc, a->a, a->ap) || 1449 !check_pair(dc, a->b, a->bp) || 1450 !check_pair(dc, a->d, a->dp)) { 1451 return false; 1452 } 1453 check_r0_write(dc, a->d); 1454 1455 t0 = tcg_temp_new_i64(); 1456 t1 = tcg_temp_new_i64(); 1457 t2 = tcg_temp_new_i64(); 1458 load_pair(dc, t0, a->d, a->dp); 1459 load_pair(dc, t1, a->a, a->ap); 1460 load_pair(dc, t2, a->b, a->bp); 1461 gen_helper_float_madd_d(t0, cpu_env, t0, t1, t2); 1462 save_pair(dc, t0, a->d, a->dp); 1463 1464 gen_helper_update_fpcsr(cpu_env); 1465 return true; 1466 } 1467 1468 static bool trans_lf_sfeq_d(DisasContext *dc, arg_ab_pair *a) 1469 { 1470 return do_dpcmp(dc, a, gen_helper_float_eq_d, false, false); 1471 } 1472 1473 static bool trans_lf_sfne_d(DisasContext *dc, arg_ab_pair *a) 1474 { 1475 return do_dpcmp(dc, a, gen_helper_float_eq_d, true, false); 1476 } 1477 1478 static bool trans_lf_sfgt_d(DisasContext *dc, arg_ab_pair *a) 1479 { 1480 return do_dpcmp(dc, a, gen_helper_float_lt_d, false, true); 1481 } 1482 1483 static bool trans_lf_sfge_d(DisasContext *dc, arg_ab_pair *a) 1484 { 1485 return do_dpcmp(dc, a, gen_helper_float_le_d, false, true); 1486 } 1487 1488 static bool trans_lf_sflt_d(DisasContext *dc, arg_ab_pair *a) 1489 { 1490 return do_dpcmp(dc, a, gen_helper_float_lt_d, false, false); 1491 } 1492 1493 static bool trans_lf_sfle_d(DisasContext *dc, arg_ab_pair *a) 1494 { 1495 return do_dpcmp(dc, a, gen_helper_float_le_d, false, false); 1496 } 1497 1498 static bool trans_lf_sfueq_d(DisasContext *dc, arg_ab_pair *a) 1499 { 1500 return do_dpcmp(dc, a, gen_helper_float_ueq_d, false, false); 1501 } 1502 1503 static bool trans_lf_sfule_d(DisasContext *dc, arg_ab_pair *a) 1504 { 1505 return do_dpcmp(dc, a, gen_helper_float_ule_d, false, false); 1506 } 1507 1508 static bool trans_lf_sfuge_d(DisasContext *dc, arg_ab_pair *a) 1509 { 1510 return do_dpcmp(dc, a, gen_helper_float_ule_d, false, true); 1511 } 1512 1513 static bool trans_lf_sfult_d(DisasContext *dc, arg_ab_pair *a) 1514 { 1515 return do_dpcmp(dc, a, gen_helper_float_ult_d, false, false); 1516 } 1517 1518 static bool trans_lf_sfugt_d(DisasContext *dc, arg_ab_pair *a) 1519 { 1520 return do_dpcmp(dc, a, gen_helper_float_ult_d, false, true); 1521 } 1522 1523 static bool trans_lf_sfun_d(DisasContext *dc, arg_ab_pair *a) 1524 { 1525 return do_dpcmp(dc, a, gen_helper_float_un_d, false, false); 1526 } 1527 1528 static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) 1529 { 1530 DisasContext *dc = container_of(dcb, DisasContext, base); 1531 CPUOpenRISCState *env = cs->env_ptr; 1532 int bound; 1533 1534 dc->mem_idx = cpu_mmu_index(env, false); 1535 dc->tb_flags = dc->base.tb->flags; 1536 dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0; 1537 dc->cpucfgr = env->cpucfgr; 1538 dc->avr = env->avr; 1539 dc->jmp_pc_imm = -1; 1540 1541 bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; 1542 dc->base.max_insns = MIN(dc->base.max_insns, bound); 1543 } 1544 1545 static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs) 1546 { 1547 DisasContext *dc = container_of(db, DisasContext, base); 1548 1549 /* Allow the TCG optimizer to see that R0 == 0, 1550 when it's true, which is the common case. */ 1551 dc->zero = tcg_constant_tl(0); 1552 if (dc->tb_flags & TB_FLAGS_R0_0) { 1553 dc->R0 = dc->zero; 1554 } else { 1555 dc->R0 = cpu_regs[0]; 1556 } 1557 } 1558 1559 static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 1560 { 1561 DisasContext *dc = container_of(dcbase, DisasContext, base); 1562 1563 tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0) 1564 | (dc->base.num_insns > 1 ? 2 : 0)); 1565 } 1566 1567 static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 1568 { 1569 DisasContext *dc = container_of(dcbase, DisasContext, base); 1570 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 1571 uint32_t insn = translator_ldl(&cpu->env, &dc->base, dc->base.pc_next); 1572 1573 if (!decode(dc, insn)) { 1574 gen_illegal_exception(dc); 1575 } 1576 dc->base.pc_next += 4; 1577 1578 /* When exiting the delay slot normally, exit via jmp_pc. 1579 * For DISAS_NORETURN, we have raised an exception and already exited. 1580 * For DISAS_EXIT, we found l.rfe in a delay slot. There's nothing 1581 * in the manual saying this is illegal, but it surely it should. 1582 * At least or1ksim overrides pcnext and ignores the branch. 1583 */ 1584 if (dc->delayed_branch 1585 && --dc->delayed_branch == 0 1586 && dc->base.is_jmp == DISAS_NEXT) { 1587 dc->base.is_jmp = DISAS_JUMP; 1588 } 1589 } 1590 1591 static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 1592 { 1593 DisasContext *dc = container_of(dcbase, DisasContext, base); 1594 target_ulong jmp_dest; 1595 1596 /* If we have already exited the TB, nothing following has effect. */ 1597 if (dc->base.is_jmp == DISAS_NORETURN) { 1598 return; 1599 } 1600 1601 /* Adjust the delayed branch state for the next TB. */ 1602 if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) { 1603 tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0); 1604 } 1605 1606 /* For DISAS_TOO_MANY, jump to the next insn. */ 1607 jmp_dest = dc->base.pc_next; 1608 tcg_gen_movi_tl(cpu_ppc, jmp_dest - 4); 1609 1610 switch (dc->base.is_jmp) { 1611 case DISAS_JUMP: 1612 jmp_dest = dc->jmp_pc_imm; 1613 if (jmp_dest == -1) { 1614 /* The jump destination is indirect/computed; use jmp_pc. */ 1615 tcg_gen_mov_tl(cpu_pc, jmp_pc); 1616 tcg_gen_discard_tl(jmp_pc); 1617 tcg_gen_lookup_and_goto_ptr(); 1618 break; 1619 } 1620 /* The jump destination is direct; use jmp_pc_imm. 1621 However, we will have stored into jmp_pc as well; 1622 we know now that it wasn't needed. */ 1623 tcg_gen_discard_tl(jmp_pc); 1624 /* fallthru */ 1625 1626 case DISAS_TOO_MANY: 1627 if (translator_use_goto_tb(&dc->base, jmp_dest)) { 1628 tcg_gen_goto_tb(0); 1629 tcg_gen_movi_tl(cpu_pc, jmp_dest); 1630 tcg_gen_exit_tb(dc->base.tb, 0); 1631 break; 1632 } 1633 tcg_gen_movi_tl(cpu_pc, jmp_dest); 1634 tcg_gen_lookup_and_goto_ptr(); 1635 break; 1636 1637 case DISAS_EXIT: 1638 tcg_gen_exit_tb(NULL, 0); 1639 break; 1640 default: 1641 g_assert_not_reached(); 1642 } 1643 } 1644 1645 static void openrisc_tr_disas_log(const DisasContextBase *dcbase, 1646 CPUState *cs, FILE *logfile) 1647 { 1648 DisasContext *s = container_of(dcbase, DisasContext, base); 1649 1650 fprintf(logfile, "IN: %s\n", lookup_symbol(s->base.pc_first)); 1651 target_disas(logfile, cs, s->base.pc_first, s->base.tb->size); 1652 } 1653 1654 static const TranslatorOps openrisc_tr_ops = { 1655 .init_disas_context = openrisc_tr_init_disas_context, 1656 .tb_start = openrisc_tr_tb_start, 1657 .insn_start = openrisc_tr_insn_start, 1658 .translate_insn = openrisc_tr_translate_insn, 1659 .tb_stop = openrisc_tr_tb_stop, 1660 .disas_log = openrisc_tr_disas_log, 1661 }; 1662 1663 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 1664 target_ulong pc, void *host_pc) 1665 { 1666 DisasContext ctx; 1667 1668 translator_loop(cs, tb, max_insns, pc, host_pc, 1669 &openrisc_tr_ops, &ctx.base); 1670 } 1671 1672 void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1673 { 1674 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 1675 CPUOpenRISCState *env = &cpu->env; 1676 int i; 1677 1678 qemu_fprintf(f, "PC=%08x\n", env->pc); 1679 for (i = 0; i < 32; ++i) { 1680 qemu_fprintf(f, "R%02d=%08x%c", i, cpu_get_gpr(env, i), 1681 (i % 4) == 3 ? '\n' : ' '); 1682 } 1683 } 1684