1 /* 2 * OpenRISC system instructions helper routines 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * Zhizhou Zhang <etouzh@gmail.com> 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "exec/helper-proto.h" 25 #include "exception.h" 26 #ifndef CONFIG_USER_ONLY 27 #include "hw/boards.h" 28 #endif 29 30 #define TO_SPR(group, number) (((group) << 11) + (number)) 31 32 void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) 33 { 34 #ifndef CONFIG_USER_ONLY 35 OpenRISCCPU *cpu = env_archcpu(env); 36 CPUState *cs = env_cpu(env); 37 target_ulong mr; 38 int idx; 39 #endif 40 41 switch (spr) { 42 #ifndef CONFIG_USER_ONLY 43 case TO_SPR(0, 11): /* EVBAR */ 44 env->evbar = rb; 45 break; 46 47 case TO_SPR(0, 16): /* NPC */ 48 cpu_restore_state(cs, GETPC(), true); 49 /* ??? Mirror or1ksim in not trashing delayed branch state 50 when "jumping" to the current instruction. */ 51 if (env->pc != rb) { 52 env->pc = rb; 53 env->dflag = 0; 54 cpu_loop_exit(cs); 55 } 56 break; 57 58 case TO_SPR(0, 17): /* SR */ 59 cpu_set_sr(env, rb); 60 break; 61 62 case TO_SPR(0, 32): /* EPCR */ 63 env->epcr = rb; 64 break; 65 66 case TO_SPR(0, 48): /* EEAR */ 67 env->eear = rb; 68 break; 69 70 case TO_SPR(0, 64): /* ESR */ 71 env->esr = rb; 72 break; 73 74 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ 75 idx = (spr - 1024); 76 env->shadow_gpr[idx / 32][idx % 32] = rb; 77 break; 78 79 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ 80 idx = spr - TO_SPR(1, 512); 81 mr = env->tlb.dtlb[idx].mr; 82 if (mr & 1) { 83 tlb_flush_page(cs, mr & TARGET_PAGE_MASK); 84 } 85 if (rb & 1) { 86 tlb_flush_page(cs, rb & TARGET_PAGE_MASK); 87 } 88 env->tlb.dtlb[idx].mr = rb; 89 break; 90 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ 91 idx = spr - TO_SPR(1, 640); 92 env->tlb.dtlb[idx].tr = rb; 93 break; 94 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ 95 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ 96 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ 97 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ 98 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ 99 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ 100 break; 101 102 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ 103 idx = spr - TO_SPR(2, 512); 104 mr = env->tlb.itlb[idx].mr; 105 if (mr & 1) { 106 tlb_flush_page(cs, mr & TARGET_PAGE_MASK); 107 } 108 if (rb & 1) { 109 tlb_flush_page(cs, rb & TARGET_PAGE_MASK); 110 } 111 env->tlb.itlb[idx].mr = rb; 112 break; 113 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ 114 idx = spr - TO_SPR(2, 640); 115 env->tlb.itlb[idx].tr = rb; 116 break; 117 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ 118 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ 119 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ 120 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ 121 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ 122 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ 123 break; 124 125 case TO_SPR(5, 1): /* MACLO */ 126 env->mac = deposit64(env->mac, 0, 32, rb); 127 break; 128 case TO_SPR(5, 2): /* MACHI */ 129 env->mac = deposit64(env->mac, 32, 32, rb); 130 break; 131 case TO_SPR(8, 0): /* PMR */ 132 env->pmr = rb; 133 if (env->pmr & PMR_DME || env->pmr & PMR_SME) { 134 cpu_restore_state(cs, GETPC(), true); 135 env->pc += 4; 136 cs->halted = 1; 137 raise_exception(cpu, EXCP_HALTED); 138 } 139 break; 140 case TO_SPR(9, 0): /* PICMR */ 141 env->picmr = rb; 142 qemu_mutex_lock_iothread(); 143 if (env->picsr & env->picmr) { 144 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 145 } else { 146 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 147 } 148 qemu_mutex_unlock_iothread(); 149 break; 150 case TO_SPR(9, 2): /* PICSR */ 151 env->picsr &= ~rb; 152 break; 153 case TO_SPR(10, 0): /* TTMR */ 154 { 155 qemu_mutex_lock_iothread(); 156 if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) { 157 switch (rb & TTMR_M) { 158 case TIMER_NONE: 159 cpu_openrisc_count_stop(cpu); 160 break; 161 case TIMER_INTR: 162 case TIMER_SHOT: 163 case TIMER_CONT: 164 cpu_openrisc_count_start(cpu); 165 break; 166 default: 167 break; 168 } 169 } 170 171 int ip = env->ttmr & TTMR_IP; 172 173 if (rb & TTMR_IP) { /* Keep IP bit. */ 174 env->ttmr = (rb & ~TTMR_IP) | ip; 175 } else { /* Clear IP bit. */ 176 env->ttmr = rb & ~TTMR_IP; 177 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER; 178 } 179 cpu_openrisc_timer_update(cpu); 180 qemu_mutex_unlock_iothread(); 181 } 182 break; 183 184 case TO_SPR(10, 1): /* TTCR */ 185 qemu_mutex_lock_iothread(); 186 cpu_openrisc_count_set(cpu, rb); 187 cpu_openrisc_timer_update(cpu); 188 qemu_mutex_unlock_iothread(); 189 break; 190 #endif 191 192 case TO_SPR(0, 20): /* FPCSR */ 193 cpu_set_fpcsr(env, rb); 194 break; 195 } 196 } 197 198 target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, 199 target_ulong spr) 200 { 201 #ifndef CONFIG_USER_ONLY 202 MachineState *ms = MACHINE(qdev_get_machine()); 203 OpenRISCCPU *cpu = env_archcpu(env); 204 CPUState *cs = env_cpu(env); 205 int idx; 206 #endif 207 208 switch (spr) { 209 #ifndef CONFIG_USER_ONLY 210 case TO_SPR(0, 0): /* VR */ 211 return env->vr; 212 213 case TO_SPR(0, 1): /* UPR */ 214 return env->upr; 215 216 case TO_SPR(0, 2): /* CPUCFGR */ 217 return env->cpucfgr; 218 219 case TO_SPR(0, 3): /* DMMUCFGR */ 220 return env->dmmucfgr; 221 222 case TO_SPR(0, 4): /* IMMUCFGR */ 223 return env->immucfgr; 224 225 case TO_SPR(0, 9): /* VR2 */ 226 return env->vr2; 227 228 case TO_SPR(0, 10): /* AVR */ 229 return env->avr; 230 231 case TO_SPR(0, 11): /* EVBAR */ 232 return env->evbar; 233 234 case TO_SPR(0, 16): /* NPC (equals PC) */ 235 cpu_restore_state(cs, GETPC(), false); 236 return env->pc; 237 238 case TO_SPR(0, 17): /* SR */ 239 return cpu_get_sr(env); 240 241 case TO_SPR(0, 18): /* PPC */ 242 cpu_restore_state(cs, GETPC(), false); 243 return env->ppc; 244 245 case TO_SPR(0, 32): /* EPCR */ 246 return env->epcr; 247 248 case TO_SPR(0, 48): /* EEAR */ 249 return env->eear; 250 251 case TO_SPR(0, 64): /* ESR */ 252 return env->esr; 253 254 case TO_SPR(0, 128): /* COREID */ 255 return cpu->parent_obj.cpu_index; 256 257 case TO_SPR(0, 129): /* NUMCORES */ 258 return ms->smp.max_cpus; 259 260 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ 261 idx = (spr - 1024); 262 return env->shadow_gpr[idx / 32][idx % 32]; 263 264 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ 265 idx = spr - TO_SPR(1, 512); 266 return env->tlb.dtlb[idx].mr; 267 268 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ 269 idx = spr - TO_SPR(1, 640); 270 return env->tlb.dtlb[idx].tr; 271 272 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ 273 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ 274 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ 275 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ 276 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ 277 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ 278 break; 279 280 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ 281 idx = spr - TO_SPR(2, 512); 282 return env->tlb.itlb[idx].mr; 283 284 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ 285 idx = spr - TO_SPR(2, 640); 286 return env->tlb.itlb[idx].tr; 287 288 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ 289 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ 290 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ 291 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ 292 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ 293 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ 294 break; 295 296 case TO_SPR(5, 1): /* MACLO */ 297 return (uint32_t)env->mac; 298 break; 299 case TO_SPR(5, 2): /* MACHI */ 300 return env->mac >> 32; 301 break; 302 303 case TO_SPR(8, 0): /* PMR */ 304 return env->pmr; 305 306 case TO_SPR(9, 0): /* PICMR */ 307 return env->picmr; 308 309 case TO_SPR(9, 2): /* PICSR */ 310 return env->picsr; 311 312 case TO_SPR(10, 0): /* TTMR */ 313 return env->ttmr; 314 315 case TO_SPR(10, 1): /* TTCR */ 316 qemu_mutex_lock_iothread(); 317 cpu_openrisc_count_update(cpu); 318 qemu_mutex_unlock_iothread(); 319 return cpu_openrisc_count_get(cpu); 320 #endif 321 322 case TO_SPR(0, 20): /* FPCSR */ 323 return env->fpcsr; 324 } 325 326 /* for rd is passed in, if rd unchanged, just keep it back. */ 327 return rd; 328 } 329