1 /* 2 * OpenRISC system instructions helper routines 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * Zhizhou Zhang <etouzh@gmail.com> 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "exec/helper-proto.h" 25 #include "exception.h" 26 #ifndef CONFIG_USER_ONLY 27 #include "hw/boards.h" 28 #endif 29 30 #define TO_SPR(group, number) (((group) << 11) + (number)) 31 32 static inline bool is_user(CPUOpenRISCState *env) 33 { 34 #ifdef CONFIG_USER_ONLY 35 return true; 36 #else 37 return (env->sr & SR_SM) == 0; 38 #endif 39 } 40 41 void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) 42 { 43 OpenRISCCPU *cpu = env_archcpu(env); 44 #ifndef CONFIG_USER_ONLY 45 CPUState *cs = env_cpu(env); 46 target_ulong mr; 47 int idx; 48 #endif 49 50 /* Handle user accessible SPRs first. */ 51 switch (spr) { 52 case TO_SPR(0, 20): /* FPCSR */ 53 cpu_set_fpcsr(env, rb); 54 return; 55 } 56 57 if (is_user(env)) { 58 raise_exception(cpu, EXCP_ILLEGAL); 59 } 60 61 #ifndef CONFIG_USER_ONLY 62 switch (spr) { 63 case TO_SPR(0, 11): /* EVBAR */ 64 env->evbar = rb; 65 break; 66 67 case TO_SPR(0, 16): /* NPC */ 68 cpu_restore_state(cs, GETPC()); 69 /* ??? Mirror or1ksim in not trashing delayed branch state 70 when "jumping" to the current instruction. */ 71 if (env->pc != rb) { 72 env->pc = rb; 73 env->dflag = 0; 74 } 75 cpu_loop_exit(cs); 76 break; 77 78 case TO_SPR(0, 17): /* SR */ 79 cpu_set_sr(env, rb); 80 break; 81 82 case TO_SPR(0, 32): /* EPCR */ 83 env->epcr = rb; 84 break; 85 86 case TO_SPR(0, 48): /* EEAR */ 87 env->eear = rb; 88 break; 89 90 case TO_SPR(0, 64): /* ESR */ 91 env->esr = rb; 92 break; 93 94 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ 95 idx = (spr - 1024); 96 env->shadow_gpr[idx / 32][idx % 32] = rb; 97 break; 98 99 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ 100 idx = spr - TO_SPR(1, 512); 101 mr = env->tlb.dtlb[idx].mr; 102 if (mr & 1) { 103 tlb_flush_page(cs, mr & TARGET_PAGE_MASK); 104 } 105 if (rb & 1) { 106 tlb_flush_page(cs, rb & TARGET_PAGE_MASK); 107 } 108 env->tlb.dtlb[idx].mr = rb; 109 break; 110 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ 111 idx = spr - TO_SPR(1, 640); 112 env->tlb.dtlb[idx].tr = rb; 113 break; 114 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ 115 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ 116 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ 117 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ 118 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ 119 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ 120 break; 121 122 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ 123 idx = spr - TO_SPR(2, 512); 124 mr = env->tlb.itlb[idx].mr; 125 if (mr & 1) { 126 tlb_flush_page(cs, mr & TARGET_PAGE_MASK); 127 } 128 if (rb & 1) { 129 tlb_flush_page(cs, rb & TARGET_PAGE_MASK); 130 } 131 env->tlb.itlb[idx].mr = rb; 132 break; 133 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ 134 idx = spr - TO_SPR(2, 640); 135 env->tlb.itlb[idx].tr = rb; 136 break; 137 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ 138 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ 139 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ 140 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ 141 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ 142 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ 143 break; 144 145 case TO_SPR(5, 1): /* MACLO */ 146 env->mac = deposit64(env->mac, 0, 32, rb); 147 break; 148 case TO_SPR(5, 2): /* MACHI */ 149 env->mac = deposit64(env->mac, 32, 32, rb); 150 break; 151 case TO_SPR(8, 0): /* PMR */ 152 env->pmr = rb; 153 if (env->pmr & PMR_DME || env->pmr & PMR_SME) { 154 cpu_restore_state(cs, GETPC()); 155 env->pc += 4; 156 cs->halted = 1; 157 raise_exception(cpu, EXCP_HALTED); 158 } 159 break; 160 case TO_SPR(9, 0): /* PICMR */ 161 env->picmr = rb; 162 qemu_mutex_lock_iothread(); 163 if (env->picsr & env->picmr) { 164 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 165 } else { 166 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 167 } 168 qemu_mutex_unlock_iothread(); 169 break; 170 case TO_SPR(9, 2): /* PICSR */ 171 env->picsr &= ~rb; 172 break; 173 case TO_SPR(10, 0): /* TTMR */ 174 { 175 qemu_mutex_lock_iothread(); 176 if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) { 177 switch (rb & TTMR_M) { 178 case TIMER_NONE: 179 cpu_openrisc_count_stop(cpu); 180 break; 181 case TIMER_INTR: 182 case TIMER_SHOT: 183 case TIMER_CONT: 184 cpu_openrisc_count_start(cpu); 185 break; 186 default: 187 break; 188 } 189 } 190 191 int ip = env->ttmr & TTMR_IP; 192 193 if (rb & TTMR_IP) { /* Keep IP bit. */ 194 env->ttmr = (rb & ~TTMR_IP) | ip; 195 } else { /* Clear IP bit. */ 196 env->ttmr = rb & ~TTMR_IP; 197 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER; 198 } 199 cpu_openrisc_timer_update(cpu); 200 qemu_mutex_unlock_iothread(); 201 } 202 break; 203 204 case TO_SPR(10, 1): /* TTCR */ 205 qemu_mutex_lock_iothread(); 206 cpu_openrisc_count_set(cpu, rb); 207 cpu_openrisc_timer_update(cpu); 208 qemu_mutex_unlock_iothread(); 209 break; 210 } 211 #endif 212 } 213 214 target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, 215 target_ulong spr) 216 { 217 OpenRISCCPU *cpu = env_archcpu(env); 218 #ifndef CONFIG_USER_ONLY 219 uint64_t data[TARGET_INSN_START_WORDS]; 220 MachineState *ms = MACHINE(qdev_get_machine()); 221 CPUState *cs = env_cpu(env); 222 int idx; 223 #endif 224 225 /* Handle user accessible SPRs first. */ 226 switch (spr) { 227 case TO_SPR(0, 20): /* FPCSR */ 228 return env->fpcsr; 229 } 230 231 if (is_user(env)) { 232 raise_exception(cpu, EXCP_ILLEGAL); 233 } 234 235 #ifndef CONFIG_USER_ONLY 236 switch (spr) { 237 case TO_SPR(0, 0): /* VR */ 238 return env->vr; 239 240 case TO_SPR(0, 1): /* UPR */ 241 return env->upr; 242 243 case TO_SPR(0, 2): /* CPUCFGR */ 244 return env->cpucfgr; 245 246 case TO_SPR(0, 3): /* DMMUCFGR */ 247 return env->dmmucfgr; 248 249 case TO_SPR(0, 4): /* IMMUCFGR */ 250 return env->immucfgr; 251 252 case TO_SPR(0, 9): /* VR2 */ 253 return env->vr2; 254 255 case TO_SPR(0, 10): /* AVR */ 256 return env->avr; 257 258 case TO_SPR(0, 11): /* EVBAR */ 259 return env->evbar; 260 261 case TO_SPR(0, 16): /* NPC (equals PC) */ 262 if (cpu_unwind_state_data(cs, GETPC(), data)) { 263 return data[0]; 264 } 265 return env->pc; 266 267 case TO_SPR(0, 17): /* SR */ 268 return cpu_get_sr(env); 269 270 case TO_SPR(0, 18): /* PPC */ 271 if (cpu_unwind_state_data(cs, GETPC(), data)) { 272 if (data[1] & 2) { 273 return data[0] - 4; 274 } 275 } 276 return env->ppc; 277 278 case TO_SPR(0, 32): /* EPCR */ 279 return env->epcr; 280 281 case TO_SPR(0, 48): /* EEAR */ 282 return env->eear; 283 284 case TO_SPR(0, 64): /* ESR */ 285 return env->esr; 286 287 case TO_SPR(0, 128): /* COREID */ 288 return cpu->parent_obj.cpu_index; 289 290 case TO_SPR(0, 129): /* NUMCORES */ 291 return ms->smp.max_cpus; 292 293 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ 294 idx = (spr - 1024); 295 return env->shadow_gpr[idx / 32][idx % 32]; 296 297 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ 298 idx = spr - TO_SPR(1, 512); 299 return env->tlb.dtlb[idx].mr; 300 301 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ 302 idx = spr - TO_SPR(1, 640); 303 return env->tlb.dtlb[idx].tr; 304 305 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ 306 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ 307 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ 308 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ 309 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ 310 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ 311 break; 312 313 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ 314 idx = spr - TO_SPR(2, 512); 315 return env->tlb.itlb[idx].mr; 316 317 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ 318 idx = spr - TO_SPR(2, 640); 319 return env->tlb.itlb[idx].tr; 320 321 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ 322 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ 323 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ 324 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ 325 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ 326 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ 327 break; 328 329 case TO_SPR(5, 1): /* MACLO */ 330 return (uint32_t)env->mac; 331 break; 332 case TO_SPR(5, 2): /* MACHI */ 333 return env->mac >> 32; 334 break; 335 336 case TO_SPR(8, 0): /* PMR */ 337 return env->pmr; 338 339 case TO_SPR(9, 0): /* PICMR */ 340 return env->picmr; 341 342 case TO_SPR(9, 2): /* PICSR */ 343 return env->picsr; 344 345 case TO_SPR(10, 0): /* TTMR */ 346 return env->ttmr; 347 348 case TO_SPR(10, 1): /* TTCR */ 349 qemu_mutex_lock_iothread(); 350 cpu_openrisc_count_update(cpu); 351 qemu_mutex_unlock_iothread(); 352 return cpu_openrisc_count_get(cpu); 353 } 354 #endif 355 356 /* for rd is passed in, if rd unchanged, just keep it back. */ 357 return rd; 358 } 359