1 /* 2 * OpenRISC system instructions helper routines 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * Zhizhou Zhang <etouzh@gmail.com> 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "exec/helper-proto.h" 25 #include "exception.h" 26 #ifndef CONFIG_USER_ONLY 27 #include "hw/boards.h" 28 #endif 29 #include "tcg/insn-start-words.h" 30 31 #define TO_SPR(group, number) (((group) << 11) + (number)) 32 33 static inline bool is_user(CPUOpenRISCState *env) 34 { 35 #ifdef CONFIG_USER_ONLY 36 return true; 37 #else 38 return (env->sr & SR_SM) == 0; 39 #endif 40 } 41 42 void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) 43 { 44 OpenRISCCPU *cpu = env_archcpu(env); 45 #ifndef CONFIG_USER_ONLY 46 CPUState *cs = env_cpu(env); 47 target_ulong mr; 48 int idx; 49 #endif 50 51 /* Handle user accessible SPRs first. */ 52 switch (spr) { 53 case TO_SPR(0, 20): /* FPCSR */ 54 cpu_set_fpcsr(env, rb); 55 return; 56 } 57 58 if (is_user(env)) { 59 raise_exception(cpu, EXCP_ILLEGAL); 60 } 61 62 #ifndef CONFIG_USER_ONLY 63 switch (spr) { 64 case TO_SPR(0, 11): /* EVBAR */ 65 env->evbar = rb; 66 break; 67 68 case TO_SPR(0, 16): /* NPC */ 69 cpu_restore_state(cs, GETPC()); 70 /* ??? Mirror or1ksim in not trashing delayed branch state 71 when "jumping" to the current instruction. */ 72 if (env->pc != rb) { 73 env->pc = rb; 74 env->dflag = 0; 75 } 76 cpu_loop_exit(cs); 77 break; 78 79 case TO_SPR(0, 17): /* SR */ 80 cpu_set_sr(env, rb); 81 break; 82 83 case TO_SPR(0, 32): /* EPCR */ 84 env->epcr = rb; 85 break; 86 87 case TO_SPR(0, 48): /* EEAR */ 88 env->eear = rb; 89 break; 90 91 case TO_SPR(0, 64): /* ESR */ 92 env->esr = rb; 93 break; 94 95 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ 96 idx = (spr - 1024); 97 env->shadow_gpr[idx / 32][idx % 32] = rb; 98 break; 99 100 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ 101 idx = spr - TO_SPR(1, 512); 102 mr = env->tlb.dtlb[idx].mr; 103 if (mr & 1) { 104 tlb_flush_page(cs, mr & TARGET_PAGE_MASK); 105 } 106 if (rb & 1) { 107 tlb_flush_page(cs, rb & TARGET_PAGE_MASK); 108 } 109 env->tlb.dtlb[idx].mr = rb; 110 break; 111 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ 112 idx = spr - TO_SPR(1, 640); 113 env->tlb.dtlb[idx].tr = rb; 114 break; 115 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ 116 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ 117 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ 118 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ 119 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ 120 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ 121 break; 122 123 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ 124 idx = spr - TO_SPR(2, 512); 125 mr = env->tlb.itlb[idx].mr; 126 if (mr & 1) { 127 tlb_flush_page(cs, mr & TARGET_PAGE_MASK); 128 } 129 if (rb & 1) { 130 tlb_flush_page(cs, rb & TARGET_PAGE_MASK); 131 } 132 env->tlb.itlb[idx].mr = rb; 133 break; 134 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ 135 idx = spr - TO_SPR(2, 640); 136 env->tlb.itlb[idx].tr = rb; 137 break; 138 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ 139 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ 140 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ 141 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ 142 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ 143 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ 144 break; 145 146 case TO_SPR(5, 1): /* MACLO */ 147 env->mac = deposit64(env->mac, 0, 32, rb); 148 break; 149 case TO_SPR(5, 2): /* MACHI */ 150 env->mac = deposit64(env->mac, 32, 32, rb); 151 break; 152 case TO_SPR(8, 0): /* PMR */ 153 env->pmr = rb; 154 if (env->pmr & PMR_DME || env->pmr & PMR_SME) { 155 cpu_restore_state(cs, GETPC()); 156 env->pc += 4; 157 cs->halted = 1; 158 raise_exception(cpu, EXCP_HALTED); 159 } 160 break; 161 case TO_SPR(9, 0): /* PICMR */ 162 env->picmr = rb; 163 qemu_mutex_lock_iothread(); 164 if (env->picsr & env->picmr) { 165 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 166 } else { 167 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 168 } 169 qemu_mutex_unlock_iothread(); 170 break; 171 case TO_SPR(9, 2): /* PICSR */ 172 env->picsr &= ~rb; 173 break; 174 case TO_SPR(10, 0): /* TTMR */ 175 { 176 qemu_mutex_lock_iothread(); 177 if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) { 178 switch (rb & TTMR_M) { 179 case TIMER_NONE: 180 cpu_openrisc_count_stop(cpu); 181 break; 182 case TIMER_INTR: 183 case TIMER_SHOT: 184 case TIMER_CONT: 185 cpu_openrisc_count_start(cpu); 186 break; 187 default: 188 break; 189 } 190 } 191 192 int ip = env->ttmr & TTMR_IP; 193 194 if (rb & TTMR_IP) { /* Keep IP bit. */ 195 env->ttmr = (rb & ~TTMR_IP) | ip; 196 } else { /* Clear IP bit. */ 197 env->ttmr = rb & ~TTMR_IP; 198 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER; 199 } 200 cpu_openrisc_timer_update(cpu); 201 qemu_mutex_unlock_iothread(); 202 } 203 break; 204 205 case TO_SPR(10, 1): /* TTCR */ 206 qemu_mutex_lock_iothread(); 207 cpu_openrisc_count_set(cpu, rb); 208 cpu_openrisc_timer_update(cpu); 209 qemu_mutex_unlock_iothread(); 210 break; 211 } 212 #endif 213 } 214 215 target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, 216 target_ulong spr) 217 { 218 OpenRISCCPU *cpu = env_archcpu(env); 219 #ifndef CONFIG_USER_ONLY 220 uint64_t data[TARGET_INSN_START_WORDS]; 221 MachineState *ms = MACHINE(qdev_get_machine()); 222 CPUState *cs = env_cpu(env); 223 int idx; 224 #endif 225 226 /* Handle user accessible SPRs first. */ 227 switch (spr) { 228 case TO_SPR(0, 20): /* FPCSR */ 229 return env->fpcsr; 230 } 231 232 if (is_user(env)) { 233 raise_exception(cpu, EXCP_ILLEGAL); 234 } 235 236 #ifndef CONFIG_USER_ONLY 237 switch (spr) { 238 case TO_SPR(0, 0): /* VR */ 239 return env->vr; 240 241 case TO_SPR(0, 1): /* UPR */ 242 return env->upr; 243 244 case TO_SPR(0, 2): /* CPUCFGR */ 245 return env->cpucfgr; 246 247 case TO_SPR(0, 3): /* DMMUCFGR */ 248 return env->dmmucfgr; 249 250 case TO_SPR(0, 4): /* IMMUCFGR */ 251 return env->immucfgr; 252 253 case TO_SPR(0, 9): /* VR2 */ 254 return env->vr2; 255 256 case TO_SPR(0, 10): /* AVR */ 257 return env->avr; 258 259 case TO_SPR(0, 11): /* EVBAR */ 260 return env->evbar; 261 262 case TO_SPR(0, 16): /* NPC (equals PC) */ 263 if (cpu_unwind_state_data(cs, GETPC(), data)) { 264 return data[0]; 265 } 266 return env->pc; 267 268 case TO_SPR(0, 17): /* SR */ 269 return cpu_get_sr(env); 270 271 case TO_SPR(0, 18): /* PPC */ 272 if (cpu_unwind_state_data(cs, GETPC(), data)) { 273 if (data[1] & 2) { 274 return data[0] - 4; 275 } 276 } 277 return env->ppc; 278 279 case TO_SPR(0, 32): /* EPCR */ 280 return env->epcr; 281 282 case TO_SPR(0, 48): /* EEAR */ 283 return env->eear; 284 285 case TO_SPR(0, 64): /* ESR */ 286 return env->esr; 287 288 case TO_SPR(0, 128): /* COREID */ 289 return cpu->parent_obj.cpu_index; 290 291 case TO_SPR(0, 129): /* NUMCORES */ 292 return ms->smp.max_cpus; 293 294 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ 295 idx = (spr - 1024); 296 return env->shadow_gpr[idx / 32][idx % 32]; 297 298 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ 299 idx = spr - TO_SPR(1, 512); 300 return env->tlb.dtlb[idx].mr; 301 302 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ 303 idx = spr - TO_SPR(1, 640); 304 return env->tlb.dtlb[idx].tr; 305 306 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ 307 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ 308 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ 309 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ 310 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ 311 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ 312 break; 313 314 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ 315 idx = spr - TO_SPR(2, 512); 316 return env->tlb.itlb[idx].mr; 317 318 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ 319 idx = spr - TO_SPR(2, 640); 320 return env->tlb.itlb[idx].tr; 321 322 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ 323 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ 324 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ 325 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ 326 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ 327 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ 328 break; 329 330 case TO_SPR(5, 1): /* MACLO */ 331 return (uint32_t)env->mac; 332 break; 333 case TO_SPR(5, 2): /* MACHI */ 334 return env->mac >> 32; 335 break; 336 337 case TO_SPR(8, 0): /* PMR */ 338 return env->pmr; 339 340 case TO_SPR(9, 0): /* PICMR */ 341 return env->picmr; 342 343 case TO_SPR(9, 2): /* PICSR */ 344 return env->picsr; 345 346 case TO_SPR(10, 0): /* TTMR */ 347 return env->ttmr; 348 349 case TO_SPR(10, 1): /* TTCR */ 350 qemu_mutex_lock_iothread(); 351 cpu_openrisc_count_update(cpu); 352 qemu_mutex_unlock_iothread(); 353 return cpu_openrisc_count_get(cpu); 354 } 355 #endif 356 357 /* for rd is passed in, if rd unchanged, just keep it back. */ 358 return rd; 359 } 360