1 /* 2 * OpenRISC interrupt. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "gdbstub/helpers.h" 25 #include "qemu/host-utils.h" 26 #ifndef CONFIG_USER_ONLY 27 #include "hw/loader.h" 28 #endif 29 30 void openrisc_cpu_do_interrupt(CPUState *cs) 31 { 32 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 33 CPUOpenRISCState *env = &cpu->env; 34 int exception = cs->exception_index; 35 36 env->epcr = env->pc; 37 38 /* When we have an illegal instruction the error effective address 39 shall be set to the illegal instruction address. */ 40 if (exception == EXCP_ILLEGAL) { 41 env->eear = env->pc; 42 } 43 44 /* During exceptions esr is populared with the pre-exception sr. */ 45 env->esr = cpu_get_sr(env); 46 /* In parallel sr is updated to disable mmu, interrupts, timers and 47 set the delay slot exception flag. */ 48 env->sr &= ~SR_DME; 49 env->sr &= ~SR_IME; 50 env->sr |= SR_SM; 51 env->sr &= ~SR_IEE; 52 env->sr &= ~SR_TEE; 53 env->pmr &= ~PMR_DME; 54 env->pmr &= ~PMR_SME; 55 env->lock_addr = -1; 56 57 /* Set/clear dsx to indicate if we are in a delay slot exception. */ 58 if (env->dflag) { 59 env->dflag = 0; 60 env->sr |= SR_DSX; 61 env->epcr -= 4; 62 } else { 63 env->sr &= ~SR_DSX; 64 if (exception == EXCP_SYSCALL || exception == EXCP_FPE) { 65 env->epcr += 4; 66 } 67 } 68 69 if (exception > 0 && exception < EXCP_NR) { 70 static const char * const int_name[EXCP_NR] = { 71 [EXCP_RESET] = "RESET", 72 [EXCP_BUSERR] = "BUSERR (bus error)", 73 [EXCP_DPF] = "DFP (data protection fault)", 74 [EXCP_IPF] = "IPF (code protection fault)", 75 [EXCP_TICK] = "TICK (timer interrupt)", 76 [EXCP_ALIGN] = "ALIGN", 77 [EXCP_ILLEGAL] = "ILLEGAL", 78 [EXCP_INT] = "INT (device interrupt)", 79 [EXCP_DTLBMISS] = "DTLBMISS (data tlb miss)", 80 [EXCP_ITLBMISS] = "ITLBMISS (code tlb miss)", 81 [EXCP_RANGE] = "RANGE", 82 [EXCP_SYSCALL] = "SYSCALL", 83 [EXCP_FPE] = "FPE", 84 [EXCP_TRAP] = "TRAP", 85 }; 86 87 qemu_log_mask(CPU_LOG_INT, "CPU: %d INT: %s\n", 88 cs->cpu_index, 89 int_name[exception]); 90 91 hwaddr vect_pc = exception << 8; 92 if (env->cpucfgr & CPUCFGR_EVBARP) { 93 vect_pc |= env->evbar; 94 } 95 if (env->sr & SR_EPH) { 96 vect_pc |= 0xf0000000; 97 } 98 env->pc = vect_pc; 99 } else { 100 cpu_abort(cs, "Unhandled exception 0x%x\n", exception); 101 } 102 103 cs->exception_index = -1; 104 } 105 106 bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 107 { 108 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 109 CPUOpenRISCState *env = &cpu->env; 110 int idx = -1; 111 112 if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) { 113 idx = EXCP_INT; 114 } 115 if ((interrupt_request & CPU_INTERRUPT_TIMER) && (env->sr & SR_TEE)) { 116 idx = EXCP_TICK; 117 } 118 if (idx >= 0) { 119 cs->exception_index = idx; 120 openrisc_cpu_do_interrupt(cs); 121 return true; 122 } 123 return false; 124 } 125