xref: /openbmc/qemu/target/openrisc/insns.decode (revision 6ad216ab)
1#
2# OpenRISC instruction decode definitions.
3#
4# Copyright (c) 2018 Richard Henderson <rth@twiddle.net>
5#
6# This library is free software; you can redistribute it and/or
7# modify it under the terms of the GNU Lesser General Public
8# License as published by the Free Software Foundation; either
9# version 2 of the License, or (at your option) any later version.
10#
11# This library is distributed in the hope that it will be useful,
12# but WITHOUT ANY WARRANTY; without even the implied warranty of
13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14# Lesser General Public License for more details.
15#
16# You should have received a copy of the GNU Lesser General Public
17# License along with this library; if not, see <http://www.gnu.org/licenses/>.
18#
19
20&dab            d a b
21&da             d a
22&ab             a b
23
24####
25# System Instructions
26####
27
28l_sys           001000 0000000000 k:16
29l_trap          001000 0100000000 k:16
30l_msync         001000 1000000000 00000000 00000000
31l_psync         001000 1010000000 00000000 00000000
32l_csync         001000 1100000000 00000000 00000000
33
34l_rfe           001001 ----- ----- -------- --------
35
36####
37# Branch Instructions
38####
39
40l_j             000000 n:s26
41l_jal           000001 n:s26
42l_bnf           000011 n:s26
43l_bf            000100 n:s26
44
45l_jr            010001 ---------- b:5 -----------
46l_jalr          010010 ---------- b:5 -----------
47
48####
49# Memory Instructions
50####
51
52&load           d a i
53@load           ...... d:5 a:5 i:s16                    &load
54
55%store_i        21:s5 0:11
56&store          a b i
57@store          ...... ..... a:5 b:5 ...........        &store i=%store_i
58
59l_lwa           011011 ..... ..... ........ ........    @load
60l_lwz           100001 ..... ..... ........ ........    @load
61l_lws           100010 ..... ..... ........ ........    @load
62l_lbz           100011 ..... ..... ........ ........    @load
63l_lbs           100100 ..... ..... ........ ........    @load
64l_lhz           100101 ..... ..... ........ ........    @load
65l_lhs           100110 ..... ..... ........ ........    @load
66
67l_swa           110011 ..... ..... ..... ...........    @store
68l_sw            110101 ..... ..... ..... ...........    @store
69l_sb            110110 ..... ..... ..... ...........    @store
70l_sh            110111 ..... ..... ..... ...........    @store
71
72####
73# Immediate Operand Instructions
74####
75
76%mtspr_k        21:5 0:11
77
78&rri            d a i
79&rrk            d a k
80@rri            ...... d:5 a:5 i:s16                    &rri
81@rrk            ...... d:5 a:5 k:16                     &rrk
82
83l_nop           000101 01--- ----- k:16
84
85l_addi          100111 ..... ..... ........ ........    @rri
86l_addic         101000 ..... ..... ........ ........    @rri
87l_andi          101001 ..... ..... ........ ........    @rrk
88l_ori           101010 ..... ..... ........ ........    @rrk
89l_xori          101011 ..... ..... ........ ........    @rri
90l_muli          101100 ..... ..... ........ ........    @rri
91
92l_mfspr         101101 ..... ..... ........ ........    @rrk
93l_mtspr         110000 ..... a:5 b:5 ...........        k=%mtspr_k
94
95l_maci          010011 ----- a:5 i:s16
96
97####
98# Arithmetic Instructions
99####
100
101l_exths         111000 d:5 a:5 ----- - 0000 -- 1100
102l_extbs         111000 d:5 a:5 ----- - 0001 -- 1100
103l_exthz         111000 d:5 a:5 ----- - 0010 -- 1100
104l_extbz         111000 d:5 a:5 ----- - 0011 -- 1100
105
106l_add           111000 d:5 a:5 b:5   - 00 ---- 0000
107l_addc          111000 d:5 a:5 b:5   - 00 ---- 0001
108l_sub           111000 d:5 a:5 b:5   - 00 ---- 0010
109l_and           111000 d:5 a:5 b:5   - 00 ---- 0011
110l_or            111000 d:5 a:5 b:5   - 00 ---- 0100
111l_xor           111000 d:5 a:5 b:5   - 00 ---- 0101
112l_cmov          111000 d:5 a:5 b:5   - 00 ---- 1110
113l_ff1           111000 d:5 a:5 ----- - 00 ---- 1111
114l_fl1           111000 d:5 a:5 ----- - 01 ---- 1111
115
116l_sll           111000 d:5 a:5 b:5   - 0000 -- 1000
117l_srl           111000 d:5 a:5 b:5   - 0001 -- 1000
118l_sra           111000 d:5 a:5 b:5   - 0010 -- 1000
119l_ror           111000 d:5 a:5 b:5   - 0011 -- 1000
120
121l_mul           111000 d:5 a:5 b:5   - 11 ---- 0110
122l_mulu          111000 d:5 a:5 b:5   - 11 ---- 1011
123l_div           111000 d:5 a:5 b:5   - 11 ---- 1001
124l_divu          111000 d:5 a:5 b:5   - 11 ---- 1010
125
126l_muld          111000 ----- a:5 b:5 - 11 ---- 0111
127l_muldu         111000 ----- a:5 b:5 - 11 ---- 1100
128