1 /* 2 * OpenRISC virtual CPU header. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef OPENRISC_CPU_H 21 #define OPENRISC_CPU_H 22 23 #include "exec/cpu-defs.h" 24 #include "hw/core/cpu.h" 25 #include "qom/object.h" 26 27 #define TYPE_OPENRISC_CPU "or1k-cpu" 28 29 OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU) 30 31 /** 32 * OpenRISCCPUClass: 33 * @parent_realize: The parent class' realize handler. 34 * @parent_reset: The parent class' reset handler. 35 * 36 * A OpenRISC CPU model. 37 */ 38 struct OpenRISCCPUClass { 39 /*< private >*/ 40 CPUClass parent_class; 41 /*< public >*/ 42 43 DeviceRealize parent_realize; 44 DeviceReset parent_reset; 45 }; 46 47 #define TARGET_INSN_START_EXTRA_WORDS 1 48 49 enum { 50 MMU_NOMMU_IDX = 0, 51 MMU_SUPERVISOR_IDX = 1, 52 MMU_USER_IDX = 2, 53 }; 54 55 #define SET_FP_CAUSE(reg, v) do {\ 56 (reg) = ((reg) & ~(0x3f << 12)) | \ 57 ((v & 0x3f) << 12);\ 58 } while (0) 59 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 60 #define UPDATE_FP_FLAGS(reg, v) do {\ 61 (reg) |= ((v & 0x1f) << 2);\ 62 } while (0) 63 64 /* Interrupt */ 65 #define NR_IRQS 32 66 67 /* Unit presece register */ 68 enum { 69 UPR_UP = (1 << 0), 70 UPR_DCP = (1 << 1), 71 UPR_ICP = (1 << 2), 72 UPR_DMP = (1 << 3), 73 UPR_IMP = (1 << 4), 74 UPR_MP = (1 << 5), 75 UPR_DUP = (1 << 6), 76 UPR_PCUR = (1 << 7), 77 UPR_PMP = (1 << 8), 78 UPR_PICP = (1 << 9), 79 UPR_TTP = (1 << 10), 80 UPR_CUP = (255 << 24), 81 }; 82 83 /* CPU configure register */ 84 enum { 85 CPUCFGR_NSGF = (15 << 0), 86 CPUCFGR_CGF = (1 << 4), 87 CPUCFGR_OB32S = (1 << 5), 88 CPUCFGR_OB64S = (1 << 6), 89 CPUCFGR_OF32S = (1 << 7), 90 CPUCFGR_OF64S = (1 << 8), 91 CPUCFGR_OV64S = (1 << 9), 92 CPUCFGR_ND = (1 << 10), 93 CPUCFGR_AVRP = (1 << 11), 94 CPUCFGR_EVBARP = (1 << 12), 95 CPUCFGR_ISRP = (1 << 13), 96 CPUCFGR_AECSRP = (1 << 14), 97 CPUCFGR_OF64A32S = (1 << 15), 98 }; 99 100 /* DMMU configure register */ 101 enum { 102 DMMUCFGR_NTW = (3 << 0), 103 DMMUCFGR_NTS = (7 << 2), 104 DMMUCFGR_NAE = (7 << 5), 105 DMMUCFGR_CRI = (1 << 8), 106 DMMUCFGR_PRI = (1 << 9), 107 DMMUCFGR_TEIRI = (1 << 10), 108 DMMUCFGR_HTR = (1 << 11), 109 }; 110 111 /* IMMU configure register */ 112 enum { 113 IMMUCFGR_NTW = (3 << 0), 114 IMMUCFGR_NTS = (7 << 2), 115 IMMUCFGR_NAE = (7 << 5), 116 IMMUCFGR_CRI = (1 << 8), 117 IMMUCFGR_PRI = (1 << 9), 118 IMMUCFGR_TEIRI = (1 << 10), 119 IMMUCFGR_HTR = (1 << 11), 120 }; 121 122 /* Power management register */ 123 enum { 124 PMR_SDF = (15 << 0), 125 PMR_DME = (1 << 4), 126 PMR_SME = (1 << 5), 127 PMR_DCGE = (1 << 6), 128 PMR_SUME = (1 << 7), 129 }; 130 131 /* Float point control status register */ 132 enum { 133 FPCSR_FPEE = 1, 134 FPCSR_RM = (3 << 1), 135 FPCSR_OVF = (1 << 3), 136 FPCSR_UNF = (1 << 4), 137 FPCSR_SNF = (1 << 5), 138 FPCSR_QNF = (1 << 6), 139 FPCSR_ZF = (1 << 7), 140 FPCSR_IXF = (1 << 8), 141 FPCSR_IVF = (1 << 9), 142 FPCSR_INF = (1 << 10), 143 FPCSR_DZF = (1 << 11), 144 }; 145 146 /* Exceptions indices */ 147 enum { 148 EXCP_RESET = 0x1, 149 EXCP_BUSERR = 0x2, 150 EXCP_DPF = 0x3, 151 EXCP_IPF = 0x4, 152 EXCP_TICK = 0x5, 153 EXCP_ALIGN = 0x6, 154 EXCP_ILLEGAL = 0x7, 155 EXCP_INT = 0x8, 156 EXCP_DTLBMISS = 0x9, 157 EXCP_ITLBMISS = 0xa, 158 EXCP_RANGE = 0xb, 159 EXCP_SYSCALL = 0xc, 160 EXCP_FPE = 0xd, 161 EXCP_TRAP = 0xe, 162 EXCP_NR, 163 }; 164 165 /* Supervisor register */ 166 enum { 167 SR_SM = (1 << 0), 168 SR_TEE = (1 << 1), 169 SR_IEE = (1 << 2), 170 SR_DCE = (1 << 3), 171 SR_ICE = (1 << 4), 172 SR_DME = (1 << 5), 173 SR_IME = (1 << 6), 174 SR_LEE = (1 << 7), 175 SR_CE = (1 << 8), 176 SR_F = (1 << 9), 177 SR_CY = (1 << 10), 178 SR_OV = (1 << 11), 179 SR_OVE = (1 << 12), 180 SR_DSX = (1 << 13), 181 SR_EPH = (1 << 14), 182 SR_FO = (1 << 15), 183 SR_SUMRA = (1 << 16), 184 SR_SCE = (1 << 17), 185 }; 186 187 /* Tick Timer Mode Register */ 188 enum { 189 TTMR_TP = (0xfffffff), 190 TTMR_IP = (1 << 28), 191 TTMR_IE = (1 << 29), 192 TTMR_M = (3 << 30), 193 }; 194 195 /* Timer Mode */ 196 enum { 197 TIMER_NONE = (0 << 30), 198 TIMER_INTR = (1 << 30), 199 TIMER_SHOT = (2 << 30), 200 TIMER_CONT = (3 << 30), 201 }; 202 203 /* TLB size */ 204 enum { 205 TLB_SIZE = 128, 206 TLB_MASK = TLB_SIZE - 1, 207 }; 208 209 /* TLB prot */ 210 enum { 211 URE = (1 << 6), 212 UWE = (1 << 7), 213 SRE = (1 << 8), 214 SWE = (1 << 9), 215 216 SXE = (1 << 6), 217 UXE = (1 << 7), 218 }; 219 220 typedef struct OpenRISCTLBEntry { 221 uint32_t mr; 222 uint32_t tr; 223 } OpenRISCTLBEntry; 224 225 #ifndef CONFIG_USER_ONLY 226 typedef struct CPUOpenRISCTLBContext { 227 OpenRISCTLBEntry itlb[TLB_SIZE]; 228 OpenRISCTLBEntry dtlb[TLB_SIZE]; 229 230 int (*cpu_openrisc_map_address_code)(OpenRISCCPU *cpu, 231 hwaddr *physical, 232 int *prot, 233 target_ulong address, int rw); 234 int (*cpu_openrisc_map_address_data)(OpenRISCCPU *cpu, 235 hwaddr *physical, 236 int *prot, 237 target_ulong address, int rw); 238 } CPUOpenRISCTLBContext; 239 #endif 240 241 typedef struct CPUArchState { 242 target_ulong shadow_gpr[16][32]; /* Shadow registers */ 243 244 target_ulong pc; /* Program counter */ 245 target_ulong ppc; /* Prev PC */ 246 target_ulong jmp_pc; /* Jump PC */ 247 248 uint64_t mac; /* Multiply registers MACHI:MACLO */ 249 250 target_ulong epcr; /* Exception PC register */ 251 target_ulong eear; /* Exception EA register */ 252 253 target_ulong sr_f; /* the SR_F bit, values 0, 1. */ 254 target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */ 255 target_long sr_ov; /* the SR_OV bit (in the sign bit only) */ 256 uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */ 257 uint32_t esr; /* Exception supervisor register */ 258 uint32_t evbar; /* Exception vector base address register */ 259 uint32_t pmr; /* Power Management Register */ 260 uint32_t fpcsr; /* Float register */ 261 float_status fp_status; 262 263 target_ulong lock_addr; 264 target_ulong lock_value; 265 266 uint32_t dflag; /* In delay slot (boolean) */ 267 268 #ifndef CONFIG_USER_ONLY 269 CPUOpenRISCTLBContext tlb; 270 #endif 271 272 /* Fields up to this point are cleared by a CPU reset */ 273 struct {} end_reset_fields; 274 275 /* Fields from here on are preserved across CPU reset. */ 276 uint32_t vr; /* Version register */ 277 uint32_t vr2; /* Version register 2 */ 278 uint32_t avr; /* Architecture version register */ 279 uint32_t upr; /* Unit presence register */ 280 uint32_t cpucfgr; /* CPU configure register */ 281 uint32_t dmmucfgr; /* DMMU configure register */ 282 uint32_t immucfgr; /* IMMU configure register */ 283 284 #ifndef CONFIG_USER_ONLY 285 QEMUTimer *timer; 286 uint32_t ttmr; /* Timer tick mode register */ 287 int is_counting; 288 289 uint32_t picmr; /* Interrupt mask register */ 290 uint32_t picsr; /* Interrupt contrl register*/ 291 #endif 292 } CPUOpenRISCState; 293 294 /** 295 * OpenRISCCPU: 296 * @env: #CPUOpenRISCState 297 * 298 * A OpenRISC CPU. 299 */ 300 struct ArchCPU { 301 /*< private >*/ 302 CPUState parent_obj; 303 /*< public >*/ 304 305 CPUNegativeOffsetState neg; 306 CPUOpenRISCState env; 307 }; 308 309 310 void cpu_openrisc_list(void); 311 void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 312 hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 313 int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 314 int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 315 void openrisc_translate_init(void); 316 int print_insn_or1k(bfd_vma addr, disassemble_info *info); 317 318 #define cpu_list cpu_openrisc_list 319 320 #ifndef CONFIG_USER_ONLY 321 bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 322 MMUAccessType access_type, int mmu_idx, 323 bool probe, uintptr_t retaddr); 324 325 extern const VMStateDescription vmstate_openrisc_cpu; 326 327 void openrisc_cpu_do_interrupt(CPUState *cpu); 328 bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); 329 330 /* hw/openrisc_pic.c */ 331 void cpu_openrisc_pic_init(OpenRISCCPU *cpu); 332 333 /* hw/openrisc_timer.c */ 334 void cpu_openrisc_clock_init(OpenRISCCPU *cpu); 335 uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu); 336 void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val); 337 void cpu_openrisc_count_update(OpenRISCCPU *cpu); 338 void cpu_openrisc_timer_update(OpenRISCCPU *cpu); 339 void cpu_openrisc_count_start(OpenRISCCPU *cpu); 340 void cpu_openrisc_count_stop(OpenRISCCPU *cpu); 341 #endif 342 343 #define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU 344 #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX 345 #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU 346 347 #include "exec/cpu-all.h" 348 349 #define TB_FLAGS_SM SR_SM 350 #define TB_FLAGS_DME SR_DME 351 #define TB_FLAGS_IME SR_IME 352 #define TB_FLAGS_OVE SR_OVE 353 #define TB_FLAGS_DFLAG 2 /* reuse SR_TEE */ 354 #define TB_FLAGS_R0_0 4 /* reuse SR_IEE */ 355 356 static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i) 357 { 358 return env->shadow_gpr[0][i]; 359 } 360 361 static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val) 362 { 363 env->shadow_gpr[0][i] = val; 364 } 365 366 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, 367 target_ulong *pc, 368 target_ulong *cs_base, uint32_t *flags) 369 { 370 *pc = env->pc; 371 *cs_base = 0; 372 *flags = (env->dflag ? TB_FLAGS_DFLAG : 0) 373 | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) 374 | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); 375 } 376 377 static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) 378 { 379 int ret = MMU_NOMMU_IDX; /* mmu is disabled */ 380 381 if (env->sr & (ifetch ? SR_IME : SR_DME)) { 382 /* The mmu is enabled; test supervisor state. */ 383 ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; 384 } 385 386 return ret; 387 } 388 389 static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) 390 { 391 return (env->sr 392 + env->sr_f * SR_F 393 + env->sr_cy * SR_CY 394 + (env->sr_ov < 0) * SR_OV); 395 } 396 397 static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val) 398 { 399 env->sr_f = (val & SR_F) != 0; 400 env->sr_cy = (val & SR_CY) != 0; 401 env->sr_ov = (val & SR_OV ? -1 : 0); 402 env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO; 403 } 404 405 void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val); 406 407 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 408 409 #endif /* OPENRISC_CPU_H */ 410