1 /* 2 * OpenRISC virtual CPU header. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef OPENRISC_CPU_H 21 #define OPENRISC_CPU_H 22 23 #include "qemu-common.h" 24 #include "exec/cpu-defs.h" 25 #include "qom/cpu.h" 26 27 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */ 28 struct OpenRISCCPU; 29 30 #define TYPE_OPENRISC_CPU "or1k-cpu" 31 32 #define OPENRISC_CPU_CLASS(klass) \ 33 OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU) 34 #define OPENRISC_CPU(obj) \ 35 OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU) 36 #define OPENRISC_CPU_GET_CLASS(obj) \ 37 OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU) 38 39 /** 40 * OpenRISCCPUClass: 41 * @parent_realize: The parent class' realize handler. 42 * @parent_reset: The parent class' reset handler. 43 * 44 * A OpenRISC CPU model. 45 */ 46 typedef struct OpenRISCCPUClass { 47 /*< private >*/ 48 CPUClass parent_class; 49 /*< public >*/ 50 51 DeviceRealize parent_realize; 52 void (*parent_reset)(CPUState *cpu); 53 } OpenRISCCPUClass; 54 55 #define TARGET_INSN_START_EXTRA_WORDS 1 56 57 enum { 58 MMU_NOMMU_IDX = 0, 59 MMU_SUPERVISOR_IDX = 1, 60 MMU_USER_IDX = 2, 61 }; 62 63 #define SET_FP_CAUSE(reg, v) do {\ 64 (reg) = ((reg) & ~(0x3f << 12)) | \ 65 ((v & 0x3f) << 12);\ 66 } while (0) 67 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 68 #define UPDATE_FP_FLAGS(reg, v) do {\ 69 (reg) |= ((v & 0x1f) << 2);\ 70 } while (0) 71 72 /* Version Register */ 73 #define SPR_VR 0xFFFF003F 74 75 /* Interrupt */ 76 #define NR_IRQS 32 77 78 /* Unit presece register */ 79 enum { 80 UPR_UP = (1 << 0), 81 UPR_DCP = (1 << 1), 82 UPR_ICP = (1 << 2), 83 UPR_DMP = (1 << 3), 84 UPR_IMP = (1 << 4), 85 UPR_MP = (1 << 5), 86 UPR_DUP = (1 << 6), 87 UPR_PCUR = (1 << 7), 88 UPR_PMP = (1 << 8), 89 UPR_PICP = (1 << 9), 90 UPR_TTP = (1 << 10), 91 UPR_CUP = (255 << 24), 92 }; 93 94 /* CPU configure register */ 95 enum { 96 CPUCFGR_NSGF = (15 << 0), 97 CPUCFGR_CGF = (1 << 4), 98 CPUCFGR_OB32S = (1 << 5), 99 CPUCFGR_OB64S = (1 << 6), 100 CPUCFGR_OF32S = (1 << 7), 101 CPUCFGR_OF64S = (1 << 8), 102 CPUCFGR_OV64S = (1 << 9), 103 /* CPUCFGR_ND = (1 << 10), */ 104 /* CPUCFGR_AVRP = (1 << 11), */ 105 CPUCFGR_EVBARP = (1 << 12), 106 /* CPUCFGR_ISRP = (1 << 13), */ 107 /* CPUCFGR_AECSRP = (1 << 14), */ 108 }; 109 110 /* DMMU configure register */ 111 enum { 112 DMMUCFGR_NTW = (3 << 0), 113 DMMUCFGR_NTS = (7 << 2), 114 DMMUCFGR_NAE = (7 << 5), 115 DMMUCFGR_CRI = (1 << 8), 116 DMMUCFGR_PRI = (1 << 9), 117 DMMUCFGR_TEIRI = (1 << 10), 118 DMMUCFGR_HTR = (1 << 11), 119 }; 120 121 /* IMMU configure register */ 122 enum { 123 IMMUCFGR_NTW = (3 << 0), 124 IMMUCFGR_NTS = (7 << 2), 125 IMMUCFGR_NAE = (7 << 5), 126 IMMUCFGR_CRI = (1 << 8), 127 IMMUCFGR_PRI = (1 << 9), 128 IMMUCFGR_TEIRI = (1 << 10), 129 IMMUCFGR_HTR = (1 << 11), 130 }; 131 132 /* Power management register */ 133 enum { 134 PMR_SDF = (15 << 0), 135 PMR_DME = (1 << 4), 136 PMR_SME = (1 << 5), 137 PMR_DCGE = (1 << 6), 138 PMR_SUME = (1 << 7), 139 }; 140 141 /* Float point control status register */ 142 enum { 143 FPCSR_FPEE = 1, 144 FPCSR_RM = (3 << 1), 145 FPCSR_OVF = (1 << 3), 146 FPCSR_UNF = (1 << 4), 147 FPCSR_SNF = (1 << 5), 148 FPCSR_QNF = (1 << 6), 149 FPCSR_ZF = (1 << 7), 150 FPCSR_IXF = (1 << 8), 151 FPCSR_IVF = (1 << 9), 152 FPCSR_INF = (1 << 10), 153 FPCSR_DZF = (1 << 11), 154 }; 155 156 /* Exceptions indices */ 157 enum { 158 EXCP_RESET = 0x1, 159 EXCP_BUSERR = 0x2, 160 EXCP_DPF = 0x3, 161 EXCP_IPF = 0x4, 162 EXCP_TICK = 0x5, 163 EXCP_ALIGN = 0x6, 164 EXCP_ILLEGAL = 0x7, 165 EXCP_INT = 0x8, 166 EXCP_DTLBMISS = 0x9, 167 EXCP_ITLBMISS = 0xa, 168 EXCP_RANGE = 0xb, 169 EXCP_SYSCALL = 0xc, 170 EXCP_FPE = 0xd, 171 EXCP_TRAP = 0xe, 172 EXCP_NR, 173 }; 174 175 /* Supervisor register */ 176 enum { 177 SR_SM = (1 << 0), 178 SR_TEE = (1 << 1), 179 SR_IEE = (1 << 2), 180 SR_DCE = (1 << 3), 181 SR_ICE = (1 << 4), 182 SR_DME = (1 << 5), 183 SR_IME = (1 << 6), 184 SR_LEE = (1 << 7), 185 SR_CE = (1 << 8), 186 SR_F = (1 << 9), 187 SR_CY = (1 << 10), 188 SR_OV = (1 << 11), 189 SR_OVE = (1 << 12), 190 SR_DSX = (1 << 13), 191 SR_EPH = (1 << 14), 192 SR_FO = (1 << 15), 193 SR_SUMRA = (1 << 16), 194 SR_SCE = (1 << 17), 195 }; 196 197 /* Tick Timer Mode Register */ 198 enum { 199 TTMR_TP = (0xfffffff), 200 TTMR_IP = (1 << 28), 201 TTMR_IE = (1 << 29), 202 TTMR_M = (3 << 30), 203 }; 204 205 /* Timer Mode */ 206 enum { 207 TIMER_NONE = (0 << 30), 208 TIMER_INTR = (1 << 30), 209 TIMER_SHOT = (2 << 30), 210 TIMER_CONT = (3 << 30), 211 }; 212 213 /* TLB size */ 214 enum { 215 TLB_SIZE = 128, 216 TLB_MASK = TLB_SIZE - 1, 217 }; 218 219 /* TLB prot */ 220 enum { 221 URE = (1 << 6), 222 UWE = (1 << 7), 223 SRE = (1 << 8), 224 SWE = (1 << 9), 225 226 SXE = (1 << 6), 227 UXE = (1 << 7), 228 }; 229 230 typedef struct OpenRISCTLBEntry { 231 uint32_t mr; 232 uint32_t tr; 233 } OpenRISCTLBEntry; 234 235 #ifndef CONFIG_USER_ONLY 236 typedef struct CPUOpenRISCTLBContext { 237 OpenRISCTLBEntry itlb[TLB_SIZE]; 238 OpenRISCTLBEntry dtlb[TLB_SIZE]; 239 240 int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, 241 hwaddr *physical, 242 int *prot, 243 target_ulong address, int rw); 244 int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu, 245 hwaddr *physical, 246 int *prot, 247 target_ulong address, int rw); 248 } CPUOpenRISCTLBContext; 249 #endif 250 251 typedef struct CPUOpenRISCState { 252 target_ulong shadow_gpr[16][32]; /* Shadow registers */ 253 254 target_ulong pc; /* Program counter */ 255 target_ulong ppc; /* Prev PC */ 256 target_ulong jmp_pc; /* Jump PC */ 257 258 uint64_t mac; /* Multiply registers MACHI:MACLO */ 259 260 target_ulong epcr; /* Exception PC register */ 261 target_ulong eear; /* Exception EA register */ 262 263 target_ulong sr_f; /* the SR_F bit, values 0, 1. */ 264 target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */ 265 target_long sr_ov; /* the SR_OV bit (in the sign bit only) */ 266 uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */ 267 uint32_t vr; /* Version register */ 268 uint32_t upr; /* Unit presence register */ 269 uint32_t dmmucfgr; /* DMMU configure register */ 270 uint32_t immucfgr; /* IMMU configure register */ 271 uint32_t esr; /* Exception supervisor register */ 272 uint32_t evbar; /* Exception vector base address register */ 273 uint32_t pmr; /* Power Management Register */ 274 uint32_t fpcsr; /* Float register */ 275 float_status fp_status; 276 277 target_ulong lock_addr; 278 target_ulong lock_value; 279 280 uint32_t dflag; /* In delay slot (boolean) */ 281 282 #ifndef CONFIG_USER_ONLY 283 CPUOpenRISCTLBContext tlb; 284 #endif 285 286 /* Fields up to this point are cleared by a CPU reset */ 287 struct {} end_reset_fields; 288 289 CPU_COMMON 290 291 /* Fields from here on are preserved across CPU reset. */ 292 uint32_t cpucfgr; /* CPU configure register */ 293 294 #ifndef CONFIG_USER_ONLY 295 QEMUTimer *timer; 296 uint32_t ttmr; /* Timer tick mode register */ 297 int is_counting; 298 299 uint32_t picmr; /* Interrupt mask register */ 300 uint32_t picsr; /* Interrupt contrl register*/ 301 #endif 302 void *irq[32]; /* Interrupt irq input */ 303 } CPUOpenRISCState; 304 305 /** 306 * OpenRISCCPU: 307 * @env: #CPUOpenRISCState 308 * 309 * A OpenRISC CPU. 310 */ 311 typedef struct OpenRISCCPU { 312 /*< private >*/ 313 CPUState parent_obj; 314 /*< public >*/ 315 316 CPUOpenRISCState env; 317 318 } OpenRISCCPU; 319 320 321 void cpu_openrisc_list(void); 322 void openrisc_cpu_do_interrupt(CPUState *cpu); 323 bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); 324 void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 325 hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 326 int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 327 int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 328 void openrisc_translate_init(void); 329 bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 330 MMUAccessType access_type, int mmu_idx, 331 bool probe, uintptr_t retaddr); 332 int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); 333 int print_insn_or1k(bfd_vma addr, disassemble_info *info); 334 335 #define cpu_list cpu_openrisc_list 336 #define cpu_signal_handler cpu_openrisc_signal_handler 337 338 #ifndef CONFIG_USER_ONLY 339 extern const struct VMStateDescription vmstate_openrisc_cpu; 340 341 /* hw/openrisc_pic.c */ 342 void cpu_openrisc_pic_init(OpenRISCCPU *cpu); 343 344 /* hw/openrisc_timer.c */ 345 void cpu_openrisc_clock_init(OpenRISCCPU *cpu); 346 uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu); 347 void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val); 348 void cpu_openrisc_count_update(OpenRISCCPU *cpu); 349 void cpu_openrisc_timer_update(OpenRISCCPU *cpu); 350 void cpu_openrisc_count_start(OpenRISCCPU *cpu); 351 void cpu_openrisc_count_stop(OpenRISCCPU *cpu); 352 #endif 353 354 #define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU 355 #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX 356 #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU 357 358 typedef CPUOpenRISCState CPUArchState; 359 typedef OpenRISCCPU ArchCPU; 360 361 #include "exec/cpu-all.h" 362 363 #define TB_FLAGS_SM SR_SM 364 #define TB_FLAGS_DME SR_DME 365 #define TB_FLAGS_IME SR_IME 366 #define TB_FLAGS_OVE SR_OVE 367 #define TB_FLAGS_DFLAG 2 /* reuse SR_TEE */ 368 #define TB_FLAGS_R0_0 4 /* reuse SR_IEE */ 369 370 static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i) 371 { 372 return env->shadow_gpr[0][i]; 373 } 374 375 static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val) 376 { 377 env->shadow_gpr[0][i] = val; 378 } 379 380 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, 381 target_ulong *pc, 382 target_ulong *cs_base, uint32_t *flags) 383 { 384 *pc = env->pc; 385 *cs_base = 0; 386 *flags = (env->dflag ? TB_FLAGS_DFLAG : 0) 387 | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) 388 | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); 389 } 390 391 static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) 392 { 393 int ret = MMU_NOMMU_IDX; /* mmu is disabled */ 394 395 if (env->sr & (ifetch ? SR_IME : SR_DME)) { 396 /* The mmu is enabled; test supervisor state. */ 397 ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; 398 } 399 400 return ret; 401 } 402 403 static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) 404 { 405 return (env->sr 406 + env->sr_f * SR_F 407 + env->sr_cy * SR_CY 408 + (env->sr_ov < 0) * SR_OV); 409 } 410 411 static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val) 412 { 413 env->sr_f = (val & SR_F) != 0; 414 env->sr_cy = (val & SR_CY) != 0; 415 env->sr_ov = (val & SR_OV ? -1 : 0); 416 env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO; 417 } 418 419 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 420 421 #endif /* OPENRISC_CPU_H */ 422