1 /* 2 * OpenRISC virtual CPU header. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef OPENRISC_CPU_H 21 #define OPENRISC_CPU_H 22 23 #include "cpu-qom.h" 24 #include "exec/cpu-defs.h" 25 #include "fpu/softfloat-types.h" 26 27 #define TCG_GUEST_DEFAULT_MO (0) 28 29 /** 30 * OpenRISCCPUClass: 31 * @parent_realize: The parent class' realize handler. 32 * @parent_phases: The parent class' reset phase handlers. 33 * 34 * A OpenRISC CPU model. 35 */ 36 struct OpenRISCCPUClass { 37 CPUClass parent_class; 38 39 DeviceRealize parent_realize; 40 ResettablePhases parent_phases; 41 }; 42 43 #define TARGET_INSN_START_EXTRA_WORDS 1 44 45 enum { 46 MMU_NOMMU_IDX = 0, 47 MMU_SUPERVISOR_IDX = 1, 48 MMU_USER_IDX = 2, 49 }; 50 51 #define SET_FP_CAUSE(reg, v) do {\ 52 (reg) = ((reg) & ~(0x3f << 12)) | \ 53 ((v & 0x3f) << 12);\ 54 } while (0) 55 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 56 #define UPDATE_FP_FLAGS(reg, v) do {\ 57 (reg) |= ((v & 0x1f) << 2);\ 58 } while (0) 59 60 /* Interrupt */ 61 #define NR_IRQS 32 62 63 /* Unit presece register */ 64 enum { 65 UPR_UP = (1 << 0), 66 UPR_DCP = (1 << 1), 67 UPR_ICP = (1 << 2), 68 UPR_DMP = (1 << 3), 69 UPR_IMP = (1 << 4), 70 UPR_MP = (1 << 5), 71 UPR_DUP = (1 << 6), 72 UPR_PCUR = (1 << 7), 73 UPR_PMP = (1 << 8), 74 UPR_PICP = (1 << 9), 75 UPR_TTP = (1 << 10), 76 UPR_CUP = (255 << 24), 77 }; 78 79 /* CPU configure register */ 80 enum { 81 CPUCFGR_NSGF = (15 << 0), 82 CPUCFGR_CGF = (1 << 4), 83 CPUCFGR_OB32S = (1 << 5), 84 CPUCFGR_OB64S = (1 << 6), 85 CPUCFGR_OF32S = (1 << 7), 86 CPUCFGR_OF64S = (1 << 8), 87 CPUCFGR_OV64S = (1 << 9), 88 CPUCFGR_ND = (1 << 10), 89 CPUCFGR_AVRP = (1 << 11), 90 CPUCFGR_EVBARP = (1 << 12), 91 CPUCFGR_ISRP = (1 << 13), 92 CPUCFGR_AECSRP = (1 << 14), 93 CPUCFGR_OF64A32S = (1 << 15), 94 }; 95 96 /* DMMU configure register */ 97 enum { 98 DMMUCFGR_NTW = (3 << 0), 99 DMMUCFGR_NTS = (7 << 2), 100 DMMUCFGR_NAE = (7 << 5), 101 DMMUCFGR_CRI = (1 << 8), 102 DMMUCFGR_PRI = (1 << 9), 103 DMMUCFGR_TEIRI = (1 << 10), 104 DMMUCFGR_HTR = (1 << 11), 105 }; 106 107 /* IMMU configure register */ 108 enum { 109 IMMUCFGR_NTW = (3 << 0), 110 IMMUCFGR_NTS = (7 << 2), 111 IMMUCFGR_NAE = (7 << 5), 112 IMMUCFGR_CRI = (1 << 8), 113 IMMUCFGR_PRI = (1 << 9), 114 IMMUCFGR_TEIRI = (1 << 10), 115 IMMUCFGR_HTR = (1 << 11), 116 }; 117 118 /* Power management register */ 119 enum { 120 PMR_SDF = (15 << 0), 121 PMR_DME = (1 << 4), 122 PMR_SME = (1 << 5), 123 PMR_DCGE = (1 << 6), 124 PMR_SUME = (1 << 7), 125 }; 126 127 /* Float point control status register */ 128 enum { 129 FPCSR_FPEE = 1, 130 FPCSR_RM = (3 << 1), 131 FPCSR_OVF = (1 << 3), 132 FPCSR_UNF = (1 << 4), 133 FPCSR_SNF = (1 << 5), 134 FPCSR_QNF = (1 << 6), 135 FPCSR_ZF = (1 << 7), 136 FPCSR_IXF = (1 << 8), 137 FPCSR_IVF = (1 << 9), 138 FPCSR_INF = (1 << 10), 139 FPCSR_DZF = (1 << 11), 140 }; 141 142 /* Exceptions indices */ 143 enum { 144 EXCP_RESET = 0x1, 145 EXCP_BUSERR = 0x2, 146 EXCP_DPF = 0x3, 147 EXCP_IPF = 0x4, 148 EXCP_TICK = 0x5, 149 EXCP_ALIGN = 0x6, 150 EXCP_ILLEGAL = 0x7, 151 EXCP_INT = 0x8, 152 EXCP_DTLBMISS = 0x9, 153 EXCP_ITLBMISS = 0xa, 154 EXCP_RANGE = 0xb, 155 EXCP_SYSCALL = 0xc, 156 EXCP_FPE = 0xd, 157 EXCP_TRAP = 0xe, 158 EXCP_NR, 159 }; 160 161 /* Supervisor register */ 162 enum { 163 SR_SM = (1 << 0), 164 SR_TEE = (1 << 1), 165 SR_IEE = (1 << 2), 166 SR_DCE = (1 << 3), 167 SR_ICE = (1 << 4), 168 SR_DME = (1 << 5), 169 SR_IME = (1 << 6), 170 SR_LEE = (1 << 7), 171 SR_CE = (1 << 8), 172 SR_F = (1 << 9), 173 SR_CY = (1 << 10), 174 SR_OV = (1 << 11), 175 SR_OVE = (1 << 12), 176 SR_DSX = (1 << 13), 177 SR_EPH = (1 << 14), 178 SR_FO = (1 << 15), 179 SR_SUMRA = (1 << 16), 180 SR_SCE = (1 << 17), 181 }; 182 183 /* Tick Timer Mode Register */ 184 enum { 185 TTMR_TP = (0xfffffff), 186 TTMR_IP = (1 << 28), 187 TTMR_IE = (1 << 29), 188 TTMR_M = (3 << 30), 189 }; 190 191 /* Timer Mode */ 192 enum { 193 TIMER_NONE = (0 << 30), 194 TIMER_INTR = (1 << 30), 195 TIMER_SHOT = (2 << 30), 196 TIMER_CONT = (3 << 30), 197 }; 198 199 /* TLB size */ 200 enum { 201 TLB_SIZE = 128, 202 TLB_MASK = TLB_SIZE - 1, 203 }; 204 205 /* TLB prot */ 206 enum { 207 URE = (1 << 6), 208 UWE = (1 << 7), 209 SRE = (1 << 8), 210 SWE = (1 << 9), 211 212 SXE = (1 << 6), 213 UXE = (1 << 7), 214 }; 215 216 typedef struct OpenRISCTLBEntry { 217 uint32_t mr; 218 uint32_t tr; 219 } OpenRISCTLBEntry; 220 221 #ifndef CONFIG_USER_ONLY 222 typedef struct CPUOpenRISCTLBContext { 223 OpenRISCTLBEntry itlb[TLB_SIZE]; 224 OpenRISCTLBEntry dtlb[TLB_SIZE]; 225 226 int (*cpu_openrisc_map_address_code)(OpenRISCCPU *cpu, 227 hwaddr *physical, 228 int *prot, 229 target_ulong address, int rw); 230 int (*cpu_openrisc_map_address_data)(OpenRISCCPU *cpu, 231 hwaddr *physical, 232 int *prot, 233 target_ulong address, int rw); 234 } CPUOpenRISCTLBContext; 235 #endif 236 237 typedef struct CPUArchState { 238 target_ulong shadow_gpr[16][32]; /* Shadow registers */ 239 240 target_ulong pc; /* Program counter */ 241 target_ulong ppc; /* Prev PC */ 242 target_ulong jmp_pc; /* Jump PC */ 243 244 uint64_t mac; /* Multiply registers MACHI:MACLO */ 245 246 target_ulong epcr; /* Exception PC register */ 247 target_ulong eear; /* Exception EA register */ 248 249 target_ulong sr_f; /* the SR_F bit, values 0, 1. */ 250 target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */ 251 target_long sr_ov; /* the SR_OV bit (in the sign bit only) */ 252 uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */ 253 uint32_t esr; /* Exception supervisor register */ 254 uint32_t evbar; /* Exception vector base address register */ 255 uint32_t pmr; /* Power Management Register */ 256 uint32_t fpcsr; /* Float register */ 257 float_status fp_status; 258 259 target_ulong lock_addr; 260 target_ulong lock_value; 261 262 uint32_t dflag; /* In delay slot (boolean) */ 263 264 #ifndef CONFIG_USER_ONLY 265 CPUOpenRISCTLBContext tlb; 266 #endif 267 268 /* Fields up to this point are cleared by a CPU reset */ 269 struct {} end_reset_fields; 270 271 /* Fields from here on are preserved across CPU reset. */ 272 uint32_t vr; /* Version register */ 273 uint32_t vr2; /* Version register 2 */ 274 uint32_t avr; /* Architecture version register */ 275 uint32_t upr; /* Unit presence register */ 276 uint32_t cpucfgr; /* CPU configure register */ 277 uint32_t dmmucfgr; /* DMMU configure register */ 278 uint32_t immucfgr; /* IMMU configure register */ 279 280 #ifndef CONFIG_USER_ONLY 281 QEMUTimer *timer; 282 uint32_t ttmr; /* Timer tick mode register */ 283 int is_counting; 284 285 uint32_t picmr; /* Interrupt mask register */ 286 uint32_t picsr; /* Interrupt control register */ 287 #endif 288 } CPUOpenRISCState; 289 290 /** 291 * OpenRISCCPU: 292 * @env: #CPUOpenRISCState 293 * 294 * A OpenRISC CPU. 295 */ 296 struct ArchCPU { 297 CPUState parent_obj; 298 299 CPUOpenRISCState env; 300 }; 301 302 void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 303 int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 304 int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 305 void openrisc_translate_init(void); 306 int print_insn_or1k(bfd_vma addr, disassemble_info *info); 307 308 #ifndef CONFIG_USER_ONLY 309 hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 310 311 bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 312 MMUAccessType access_type, int mmu_idx, 313 bool probe, uintptr_t retaddr); 314 315 extern const VMStateDescription vmstate_openrisc_cpu; 316 317 void openrisc_cpu_do_interrupt(CPUState *cpu); 318 bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); 319 320 /* hw/openrisc_pic.c */ 321 void cpu_openrisc_pic_init(OpenRISCCPU *cpu); 322 323 /* hw/openrisc_timer.c */ 324 void cpu_openrisc_clock_init(OpenRISCCPU *cpu); 325 uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu); 326 void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val); 327 void cpu_openrisc_count_update(OpenRISCCPU *cpu); 328 void cpu_openrisc_timer_update(OpenRISCCPU *cpu); 329 void cpu_openrisc_count_start(OpenRISCCPU *cpu); 330 void cpu_openrisc_count_stop(OpenRISCCPU *cpu); 331 #endif 332 333 #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU 334 335 #include "exec/cpu-all.h" 336 337 #define TB_FLAGS_SM SR_SM 338 #define TB_FLAGS_DME SR_DME 339 #define TB_FLAGS_IME SR_IME 340 #define TB_FLAGS_OVE SR_OVE 341 #define TB_FLAGS_DFLAG 2 /* reuse SR_TEE */ 342 #define TB_FLAGS_R0_0 4 /* reuse SR_IEE */ 343 344 static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i) 345 { 346 return env->shadow_gpr[0][i]; 347 } 348 349 static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val) 350 { 351 env->shadow_gpr[0][i] = val; 352 } 353 354 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, 355 uint64_t *cs_base, uint32_t *flags) 356 { 357 *pc = env->pc; 358 *cs_base = 0; 359 *flags = (env->dflag ? TB_FLAGS_DFLAG : 0) 360 | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) 361 | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); 362 } 363 364 static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) 365 { 366 return (env->sr 367 + env->sr_f * SR_F 368 + env->sr_cy * SR_CY 369 + (env->sr_ov < 0) * SR_OV); 370 } 371 372 static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val) 373 { 374 env->sr_f = (val & SR_F) != 0; 375 env->sr_cy = (val & SR_CY) != 0; 376 env->sr_ov = (val & SR_OV ? -1 : 0); 377 env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO; 378 } 379 380 void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val); 381 382 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 383 384 #endif /* OPENRISC_CPU_H */ 385