1 /* 2 * OpenRISC virtual CPU header. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef OPENRISC_CPU_H 21 #define OPENRISC_CPU_H 22 23 #define TARGET_LONG_BITS 32 24 25 #define CPUArchState struct CPUOpenRISCState 26 27 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */ 28 struct OpenRISCCPU; 29 30 #include "qemu-common.h" 31 #include "exec/cpu-defs.h" 32 #include "qom/cpu.h" 33 34 #define TYPE_OPENRISC_CPU "or1k-cpu" 35 36 #define OPENRISC_CPU_CLASS(klass) \ 37 OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU) 38 #define OPENRISC_CPU(obj) \ 39 OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU) 40 #define OPENRISC_CPU_GET_CLASS(obj) \ 41 OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU) 42 43 /** 44 * OpenRISCCPUClass: 45 * @parent_realize: The parent class' realize handler. 46 * @parent_reset: The parent class' reset handler. 47 * 48 * A OpenRISC CPU model. 49 */ 50 typedef struct OpenRISCCPUClass { 51 /*< private >*/ 52 CPUClass parent_class; 53 /*< public >*/ 54 55 DeviceRealize parent_realize; 56 void (*parent_reset)(CPUState *cpu); 57 } OpenRISCCPUClass; 58 59 #define NB_MMU_MODES 3 60 #define TARGET_INSN_START_EXTRA_WORDS 1 61 62 enum { 63 MMU_NOMMU_IDX = 0, 64 MMU_SUPERVISOR_IDX = 1, 65 MMU_USER_IDX = 2, 66 }; 67 68 #define TARGET_PAGE_BITS 13 69 70 #define TARGET_PHYS_ADDR_SPACE_BITS 32 71 #define TARGET_VIRT_ADDR_SPACE_BITS 32 72 73 #define SET_FP_CAUSE(reg, v) do {\ 74 (reg) = ((reg) & ~(0x3f << 12)) | \ 75 ((v & 0x3f) << 12);\ 76 } while (0) 77 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 78 #define UPDATE_FP_FLAGS(reg, v) do {\ 79 (reg) |= ((v & 0x1f) << 2);\ 80 } while (0) 81 82 /* Version Register */ 83 #define SPR_VR 0xFFFF003F 84 85 /* Interrupt */ 86 #define NR_IRQS 32 87 88 /* Unit presece register */ 89 enum { 90 UPR_UP = (1 << 0), 91 UPR_DCP = (1 << 1), 92 UPR_ICP = (1 << 2), 93 UPR_DMP = (1 << 3), 94 UPR_IMP = (1 << 4), 95 UPR_MP = (1 << 5), 96 UPR_DUP = (1 << 6), 97 UPR_PCUR = (1 << 7), 98 UPR_PMP = (1 << 8), 99 UPR_PICP = (1 << 9), 100 UPR_TTP = (1 << 10), 101 UPR_CUP = (255 << 24), 102 }; 103 104 /* CPU configure register */ 105 enum { 106 CPUCFGR_NSGF = (15 << 0), 107 CPUCFGR_CGF = (1 << 4), 108 CPUCFGR_OB32S = (1 << 5), 109 CPUCFGR_OB64S = (1 << 6), 110 CPUCFGR_OF32S = (1 << 7), 111 CPUCFGR_OF64S = (1 << 8), 112 CPUCFGR_OV64S = (1 << 9), 113 /* CPUCFGR_ND = (1 << 10), */ 114 /* CPUCFGR_AVRP = (1 << 11), */ 115 CPUCFGR_EVBARP = (1 << 12), 116 /* CPUCFGR_ISRP = (1 << 13), */ 117 /* CPUCFGR_AECSRP = (1 << 14), */ 118 }; 119 120 /* DMMU configure register */ 121 enum { 122 DMMUCFGR_NTW = (3 << 0), 123 DMMUCFGR_NTS = (7 << 2), 124 DMMUCFGR_NAE = (7 << 5), 125 DMMUCFGR_CRI = (1 << 8), 126 DMMUCFGR_PRI = (1 << 9), 127 DMMUCFGR_TEIRI = (1 << 10), 128 DMMUCFGR_HTR = (1 << 11), 129 }; 130 131 /* IMMU configure register */ 132 enum { 133 IMMUCFGR_NTW = (3 << 0), 134 IMMUCFGR_NTS = (7 << 2), 135 IMMUCFGR_NAE = (7 << 5), 136 IMMUCFGR_CRI = (1 << 8), 137 IMMUCFGR_PRI = (1 << 9), 138 IMMUCFGR_TEIRI = (1 << 10), 139 IMMUCFGR_HTR = (1 << 11), 140 }; 141 142 /* Power management register */ 143 enum { 144 PMR_SDF = (15 << 0), 145 PMR_DME = (1 << 4), 146 PMR_SME = (1 << 5), 147 PMR_DCGE = (1 << 6), 148 PMR_SUME = (1 << 7), 149 }; 150 151 /* Float point control status register */ 152 enum { 153 FPCSR_FPEE = 1, 154 FPCSR_RM = (3 << 1), 155 FPCSR_OVF = (1 << 3), 156 FPCSR_UNF = (1 << 4), 157 FPCSR_SNF = (1 << 5), 158 FPCSR_QNF = (1 << 6), 159 FPCSR_ZF = (1 << 7), 160 FPCSR_IXF = (1 << 8), 161 FPCSR_IVF = (1 << 9), 162 FPCSR_INF = (1 << 10), 163 FPCSR_DZF = (1 << 11), 164 }; 165 166 /* Exceptions indices */ 167 enum { 168 EXCP_RESET = 0x1, 169 EXCP_BUSERR = 0x2, 170 EXCP_DPF = 0x3, 171 EXCP_IPF = 0x4, 172 EXCP_TICK = 0x5, 173 EXCP_ALIGN = 0x6, 174 EXCP_ILLEGAL = 0x7, 175 EXCP_INT = 0x8, 176 EXCP_DTLBMISS = 0x9, 177 EXCP_ITLBMISS = 0xa, 178 EXCP_RANGE = 0xb, 179 EXCP_SYSCALL = 0xc, 180 EXCP_FPE = 0xd, 181 EXCP_TRAP = 0xe, 182 EXCP_NR, 183 }; 184 185 /* Supervisor register */ 186 enum { 187 SR_SM = (1 << 0), 188 SR_TEE = (1 << 1), 189 SR_IEE = (1 << 2), 190 SR_DCE = (1 << 3), 191 SR_ICE = (1 << 4), 192 SR_DME = (1 << 5), 193 SR_IME = (1 << 6), 194 SR_LEE = (1 << 7), 195 SR_CE = (1 << 8), 196 SR_F = (1 << 9), 197 SR_CY = (1 << 10), 198 SR_OV = (1 << 11), 199 SR_OVE = (1 << 12), 200 SR_DSX = (1 << 13), 201 SR_EPH = (1 << 14), 202 SR_FO = (1 << 15), 203 SR_SUMRA = (1 << 16), 204 SR_SCE = (1 << 17), 205 }; 206 207 /* Tick Timer Mode Register */ 208 enum { 209 TTMR_TP = (0xfffffff), 210 TTMR_IP = (1 << 28), 211 TTMR_IE = (1 << 29), 212 TTMR_M = (3 << 30), 213 }; 214 215 /* Timer Mode */ 216 enum { 217 TIMER_NONE = (0 << 30), 218 TIMER_INTR = (1 << 30), 219 TIMER_SHOT = (2 << 30), 220 TIMER_CONT = (3 << 30), 221 }; 222 223 /* TLB size */ 224 enum { 225 TLB_SIZE = 128, 226 TLB_MASK = TLB_SIZE - 1, 227 }; 228 229 /* TLB prot */ 230 enum { 231 URE = (1 << 6), 232 UWE = (1 << 7), 233 SRE = (1 << 8), 234 SWE = (1 << 9), 235 236 SXE = (1 << 6), 237 UXE = (1 << 7), 238 }; 239 240 typedef struct OpenRISCTLBEntry { 241 uint32_t mr; 242 uint32_t tr; 243 } OpenRISCTLBEntry; 244 245 #ifndef CONFIG_USER_ONLY 246 typedef struct CPUOpenRISCTLBContext { 247 OpenRISCTLBEntry itlb[TLB_SIZE]; 248 OpenRISCTLBEntry dtlb[TLB_SIZE]; 249 250 int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, 251 hwaddr *physical, 252 int *prot, 253 target_ulong address, int rw); 254 int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu, 255 hwaddr *physical, 256 int *prot, 257 target_ulong address, int rw); 258 } CPUOpenRISCTLBContext; 259 #endif 260 261 typedef struct CPUOpenRISCState { 262 target_ulong shadow_gpr[16][32]; /* Shadow registers */ 263 264 target_ulong pc; /* Program counter */ 265 target_ulong ppc; /* Prev PC */ 266 target_ulong jmp_pc; /* Jump PC */ 267 268 uint64_t mac; /* Multiply registers MACHI:MACLO */ 269 270 target_ulong epcr; /* Exception PC register */ 271 target_ulong eear; /* Exception EA register */ 272 273 target_ulong sr_f; /* the SR_F bit, values 0, 1. */ 274 target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */ 275 target_long sr_ov; /* the SR_OV bit (in the sign bit only) */ 276 uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */ 277 uint32_t vr; /* Version register */ 278 uint32_t upr; /* Unit presence register */ 279 uint32_t dmmucfgr; /* DMMU configure register */ 280 uint32_t immucfgr; /* IMMU configure register */ 281 uint32_t esr; /* Exception supervisor register */ 282 uint32_t evbar; /* Exception vector base address register */ 283 uint32_t pmr; /* Power Management Register */ 284 uint32_t fpcsr; /* Float register */ 285 float_status fp_status; 286 287 target_ulong lock_addr; 288 target_ulong lock_value; 289 290 uint32_t dflag; /* In delay slot (boolean) */ 291 292 #ifndef CONFIG_USER_ONLY 293 CPUOpenRISCTLBContext tlb; 294 #endif 295 296 /* Fields up to this point are cleared by a CPU reset */ 297 struct {} end_reset_fields; 298 299 CPU_COMMON 300 301 /* Fields from here on are preserved across CPU reset. */ 302 uint32_t cpucfgr; /* CPU configure register */ 303 304 #ifndef CONFIG_USER_ONLY 305 QEMUTimer *timer; 306 uint32_t ttmr; /* Timer tick mode register */ 307 int is_counting; 308 309 uint32_t picmr; /* Interrupt mask register */ 310 uint32_t picsr; /* Interrupt contrl register*/ 311 #endif 312 void *irq[32]; /* Interrupt irq input */ 313 } CPUOpenRISCState; 314 315 /** 316 * OpenRISCCPU: 317 * @env: #CPUOpenRISCState 318 * 319 * A OpenRISC CPU. 320 */ 321 typedef struct OpenRISCCPU { 322 /*< private >*/ 323 CPUState parent_obj; 324 /*< public >*/ 325 326 CPUOpenRISCState env; 327 328 } OpenRISCCPU; 329 330 static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env) 331 { 332 return container_of(env, OpenRISCCPU, env); 333 } 334 335 #define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e)) 336 337 #define ENV_OFFSET offsetof(OpenRISCCPU, env) 338 339 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf); 340 void openrisc_cpu_do_interrupt(CPUState *cpu); 341 bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); 342 void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, 343 fprintf_function cpu_fprintf, int flags); 344 hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 345 int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 346 int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 347 void openrisc_translate_init(void); 348 int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, 349 int rw, int mmu_idx); 350 int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); 351 int print_insn_or1k(bfd_vma addr, disassemble_info *info); 352 353 #define cpu_list cpu_openrisc_list 354 #define cpu_signal_handler cpu_openrisc_signal_handler 355 356 #ifndef CONFIG_USER_ONLY 357 extern const struct VMStateDescription vmstate_openrisc_cpu; 358 359 /* hw/openrisc_pic.c */ 360 void cpu_openrisc_pic_init(OpenRISCCPU *cpu); 361 362 /* hw/openrisc_timer.c */ 363 void cpu_openrisc_clock_init(OpenRISCCPU *cpu); 364 uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu); 365 void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val); 366 void cpu_openrisc_count_update(OpenRISCCPU *cpu); 367 void cpu_openrisc_timer_update(OpenRISCCPU *cpu); 368 void cpu_openrisc_count_start(OpenRISCCPU *cpu); 369 void cpu_openrisc_count_stop(OpenRISCCPU *cpu); 370 #endif 371 372 #define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU 373 #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX 374 #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU 375 376 #include "exec/cpu-all.h" 377 378 #define TB_FLAGS_SM SR_SM 379 #define TB_FLAGS_DME SR_DME 380 #define TB_FLAGS_IME SR_IME 381 #define TB_FLAGS_OVE SR_OVE 382 #define TB_FLAGS_DFLAG 2 /* reuse SR_TEE */ 383 #define TB_FLAGS_R0_0 4 /* reuse SR_IEE */ 384 385 static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i) 386 { 387 return env->shadow_gpr[0][i]; 388 } 389 390 static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val) 391 { 392 env->shadow_gpr[0][i] = val; 393 } 394 395 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, 396 target_ulong *pc, 397 target_ulong *cs_base, uint32_t *flags) 398 { 399 *pc = env->pc; 400 *cs_base = 0; 401 *flags = (env->dflag ? TB_FLAGS_DFLAG : 0) 402 | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) 403 | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); 404 } 405 406 static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) 407 { 408 int ret = MMU_NOMMU_IDX; /* mmu is disabled */ 409 410 if (env->sr & (ifetch ? SR_IME : SR_DME)) { 411 /* The mmu is enabled; test supervisor state. */ 412 ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; 413 } 414 415 return ret; 416 } 417 418 static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) 419 { 420 return (env->sr 421 + env->sr_f * SR_F 422 + env->sr_cy * SR_CY 423 + (env->sr_ov < 0) * SR_OV); 424 } 425 426 static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val) 427 { 428 env->sr_f = (val & SR_F) != 0; 429 env->sr_cy = (val & SR_CY) != 0; 430 env->sr_ov = (val & SR_OV ? -1 : 0); 431 env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO; 432 } 433 434 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 435 436 #endif /* OPENRISC_CPU_H */ 437