1 /* 2 * QEMU OpenRISC CPU 3 * 4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "cpu.h" 23 #include "qemu-common.h" 24 #include "exec/exec-all.h" 25 26 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) 27 { 28 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 29 30 cpu->env.pc = value; 31 } 32 33 static bool openrisc_cpu_has_work(CPUState *cs) 34 { 35 return cs->interrupt_request & (CPU_INTERRUPT_HARD | 36 CPU_INTERRUPT_TIMER); 37 } 38 39 /* CPUClass::reset() */ 40 static void openrisc_cpu_reset(CPUState *s) 41 { 42 OpenRISCCPU *cpu = OPENRISC_CPU(s); 43 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); 44 45 occ->parent_reset(s); 46 47 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); 48 49 cpu->env.pc = 0x100; 50 cpu->env.sr = SR_FO | SR_SM; 51 cpu->env.lock_addr = -1; 52 s->exception_index = -1; 53 54 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | 55 UPR_PMP; 56 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2)); 57 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2)); 58 59 #ifndef CONFIG_USER_ONLY 60 cpu->env.picmr = 0x00000000; 61 cpu->env.picsr = 0x00000000; 62 63 cpu->env.ttmr = 0x00000000; 64 #endif 65 } 66 67 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) 68 { 69 CPUState *cs = CPU(dev); 70 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); 71 Error *local_err = NULL; 72 73 cpu_exec_realizefn(cs, &local_err); 74 if (local_err != NULL) { 75 error_propagate(errp, local_err); 76 return; 77 } 78 79 qemu_init_vcpu(cs); 80 cpu_reset(cs); 81 82 occ->parent_realize(dev, errp); 83 } 84 85 static void openrisc_cpu_initfn(Object *obj) 86 { 87 CPUState *cs = CPU(obj); 88 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 89 static int inited; 90 91 cs->env_ptr = &cpu->env; 92 93 #ifndef CONFIG_USER_ONLY 94 cpu_openrisc_mmu_init(cpu); 95 #endif 96 97 if (tcg_enabled() && !inited) { 98 inited = 1; 99 openrisc_translate_init(); 100 } 101 } 102 103 /* CPU models */ 104 105 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) 106 { 107 ObjectClass *oc; 108 char *typename; 109 110 typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model); 111 oc = object_class_by_name(typename); 112 g_free(typename); 113 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) || 114 object_class_is_abstract(oc))) { 115 return NULL; 116 } 117 return oc; 118 } 119 120 static void or1200_initfn(Object *obj) 121 { 122 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 123 124 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 125 CPUCFGR_EVBARP; 126 } 127 128 static void openrisc_any_initfn(Object *obj) 129 { 130 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 131 132 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP; 133 } 134 135 typedef struct OpenRISCCPUInfo { 136 const char *name; 137 void (*initfn)(Object *obj); 138 } OpenRISCCPUInfo; 139 140 static const OpenRISCCPUInfo openrisc_cpus[] = { 141 { .name = "or1200", .initfn = or1200_initfn }, 142 { .name = "any", .initfn = openrisc_any_initfn }, 143 }; 144 145 static void openrisc_cpu_class_init(ObjectClass *oc, void *data) 146 { 147 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); 148 CPUClass *cc = CPU_CLASS(occ); 149 DeviceClass *dc = DEVICE_CLASS(oc); 150 151 occ->parent_realize = dc->realize; 152 dc->realize = openrisc_cpu_realizefn; 153 154 occ->parent_reset = cc->reset; 155 cc->reset = openrisc_cpu_reset; 156 157 cc->class_by_name = openrisc_cpu_class_by_name; 158 cc->has_work = openrisc_cpu_has_work; 159 cc->do_interrupt = openrisc_cpu_do_interrupt; 160 cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt; 161 cc->dump_state = openrisc_cpu_dump_state; 162 cc->set_pc = openrisc_cpu_set_pc; 163 cc->gdb_read_register = openrisc_cpu_gdb_read_register; 164 cc->gdb_write_register = openrisc_cpu_gdb_write_register; 165 #ifdef CONFIG_USER_ONLY 166 cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault; 167 #else 168 cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; 169 dc->vmsd = &vmstate_openrisc_cpu; 170 #endif 171 cc->gdb_num_core_regs = 32 + 3; 172 } 173 174 static void cpu_register(const OpenRISCCPUInfo *info) 175 { 176 TypeInfo type_info = { 177 .parent = TYPE_OPENRISC_CPU, 178 .instance_size = sizeof(OpenRISCCPU), 179 .instance_init = info->initfn, 180 .class_size = sizeof(OpenRISCCPUClass), 181 }; 182 183 type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name); 184 type_register(&type_info); 185 g_free((void *)type_info.name); 186 } 187 188 static const TypeInfo openrisc_cpu_type_info = { 189 .name = TYPE_OPENRISC_CPU, 190 .parent = TYPE_CPU, 191 .instance_size = sizeof(OpenRISCCPU), 192 .instance_init = openrisc_cpu_initfn, 193 .abstract = true, 194 .class_size = sizeof(OpenRISCCPUClass), 195 .class_init = openrisc_cpu_class_init, 196 }; 197 198 static void openrisc_cpu_register_types(void) 199 { 200 int i; 201 202 type_register_static(&openrisc_cpu_type_info); 203 for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) { 204 cpu_register(&openrisc_cpus[i]); 205 } 206 } 207 208 /* Sort alphabetically by type name, except for "any". */ 209 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b) 210 { 211 ObjectClass *class_a = (ObjectClass *)a; 212 ObjectClass *class_b = (ObjectClass *)b; 213 const char *name_a, *name_b; 214 215 name_a = object_class_get_name(class_a); 216 name_b = object_class_get_name(class_b); 217 if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) { 218 return 1; 219 } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) { 220 return -1; 221 } else { 222 return strcmp(name_a, name_b); 223 } 224 } 225 226 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data) 227 { 228 ObjectClass *oc = data; 229 CPUListState *s = user_data; 230 const char *typename; 231 char *name; 232 233 typename = object_class_get_name(oc); 234 name = g_strndup(typename, 235 strlen(typename) - strlen("-" TYPE_OPENRISC_CPU)); 236 (*s->cpu_fprintf)(s->file, " %s\n", 237 name); 238 g_free(name); 239 } 240 241 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf) 242 { 243 CPUListState s = { 244 .file = f, 245 .cpu_fprintf = cpu_fprintf, 246 }; 247 GSList *list; 248 249 list = object_class_get_list(TYPE_OPENRISC_CPU, false); 250 list = g_slist_sort(list, openrisc_cpu_list_compare); 251 (*cpu_fprintf)(f, "Available CPUs:\n"); 252 g_slist_foreach(list, openrisc_cpu_list_entry, &s); 253 g_slist_free(list); 254 } 255 256 type_init(openrisc_cpu_register_types) 257