1 /* 2 * QEMU OpenRISC CPU 3 * 4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu/qemu-print.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "tcg/tcg.h" 26 27 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) 28 { 29 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 30 31 cpu->env.pc = value; 32 cpu->env.dflag = 0; 33 } 34 35 static vaddr openrisc_cpu_get_pc(CPUState *cs) 36 { 37 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 38 39 return cpu->env.pc; 40 } 41 42 static void openrisc_cpu_synchronize_from_tb(CPUState *cs, 43 const TranslationBlock *tb) 44 { 45 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 46 47 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 48 cpu->env.pc = tb->pc; 49 } 50 51 static void openrisc_restore_state_to_opc(CPUState *cs, 52 const TranslationBlock *tb, 53 const uint64_t *data) 54 { 55 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 56 57 cpu->env.pc = data[0]; 58 cpu->env.dflag = data[1] & 1; 59 if (data[1] & 2) { 60 cpu->env.ppc = cpu->env.pc - 4; 61 } 62 } 63 64 static bool openrisc_cpu_has_work(CPUState *cs) 65 { 66 return cs->interrupt_request & (CPU_INTERRUPT_HARD | 67 CPU_INTERRUPT_TIMER); 68 } 69 70 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) 71 { 72 info->print_insn = print_insn_or1k; 73 } 74 75 static void openrisc_cpu_reset_hold(Object *obj) 76 { 77 CPUState *s = CPU(obj); 78 OpenRISCCPU *cpu = OPENRISC_CPU(s); 79 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); 80 81 if (occ->parent_phases.hold) { 82 occ->parent_phases.hold(obj); 83 } 84 85 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); 86 87 cpu->env.pc = 0x100; 88 cpu->env.sr = SR_FO | SR_SM; 89 cpu->env.lock_addr = -1; 90 s->exception_index = -1; 91 cpu_set_fpcsr(&cpu->env, 0); 92 93 #ifndef CONFIG_USER_ONLY 94 cpu->env.picmr = 0x00000000; 95 cpu->env.picsr = 0x00000000; 96 97 cpu->env.ttmr = 0x00000000; 98 #endif 99 } 100 101 #ifndef CONFIG_USER_ONLY 102 static void openrisc_cpu_set_irq(void *opaque, int irq, int level) 103 { 104 OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; 105 CPUState *cs = CPU(cpu); 106 uint32_t irq_bit; 107 108 if (irq > 31 || irq < 0) { 109 return; 110 } 111 112 irq_bit = 1U << irq; 113 114 if (level) { 115 cpu->env.picsr |= irq_bit; 116 } else { 117 cpu->env.picsr &= ~irq_bit; 118 } 119 120 if (cpu->env.picsr & cpu->env.picmr) { 121 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 122 } else { 123 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 124 } 125 } 126 #endif 127 128 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) 129 { 130 CPUState *cs = CPU(dev); 131 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); 132 Error *local_err = NULL; 133 134 cpu_exec_realizefn(cs, &local_err); 135 if (local_err != NULL) { 136 error_propagate(errp, local_err); 137 return; 138 } 139 140 qemu_init_vcpu(cs); 141 cpu_reset(cs); 142 143 occ->parent_realize(dev, errp); 144 } 145 146 static void openrisc_cpu_initfn(Object *obj) 147 { 148 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 149 150 cpu_set_cpustate_pointers(cpu); 151 152 #ifndef CONFIG_USER_ONLY 153 qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_IRQS); 154 #endif 155 } 156 157 /* CPU models */ 158 159 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) 160 { 161 ObjectClass *oc; 162 char *typename; 163 164 typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model); 165 oc = object_class_by_name(typename); 166 g_free(typename); 167 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) || 168 object_class_is_abstract(oc))) { 169 return NULL; 170 } 171 return oc; 172 } 173 174 static void or1200_initfn(Object *obj) 175 { 176 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 177 178 cpu->env.vr = 0x13000008; 179 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 180 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 181 CPUCFGR_EVBARP; 182 183 /* 1Way, TLB_SIZE entries. */ 184 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 185 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 186 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 187 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 188 } 189 190 static void openrisc_any_initfn(Object *obj) 191 { 192 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 193 194 cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */ 195 cpu->env.vr2 = 0; /* No version specific id */ 196 cpu->env.avr = 0x01030000; /* Architecture v1.3 */ 197 198 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 199 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 200 CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S; 201 202 /* 1Way, TLB_SIZE entries. */ 203 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 204 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 205 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 206 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 207 } 208 209 #ifndef CONFIG_USER_ONLY 210 #include "hw/core/sysemu-cpu-ops.h" 211 212 static const struct SysemuCPUOps openrisc_sysemu_ops = { 213 .get_phys_page_debug = openrisc_cpu_get_phys_page_debug, 214 }; 215 #endif 216 217 #include "hw/core/tcg-cpu-ops.h" 218 219 static const struct TCGCPUOps openrisc_tcg_ops = { 220 .initialize = openrisc_translate_init, 221 .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, 222 .restore_state_to_opc = openrisc_restore_state_to_opc, 223 224 #ifndef CONFIG_USER_ONLY 225 .tlb_fill = openrisc_cpu_tlb_fill, 226 .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, 227 .do_interrupt = openrisc_cpu_do_interrupt, 228 #endif /* !CONFIG_USER_ONLY */ 229 }; 230 231 static void openrisc_cpu_class_init(ObjectClass *oc, void *data) 232 { 233 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); 234 CPUClass *cc = CPU_CLASS(occ); 235 DeviceClass *dc = DEVICE_CLASS(oc); 236 ResettableClass *rc = RESETTABLE_CLASS(oc); 237 238 device_class_set_parent_realize(dc, openrisc_cpu_realizefn, 239 &occ->parent_realize); 240 resettable_class_set_parent_phases(rc, NULL, openrisc_cpu_reset_hold, NULL, 241 &occ->parent_phases); 242 243 cc->class_by_name = openrisc_cpu_class_by_name; 244 cc->has_work = openrisc_cpu_has_work; 245 cc->dump_state = openrisc_cpu_dump_state; 246 cc->set_pc = openrisc_cpu_set_pc; 247 cc->get_pc = openrisc_cpu_get_pc; 248 cc->gdb_read_register = openrisc_cpu_gdb_read_register; 249 cc->gdb_write_register = openrisc_cpu_gdb_write_register; 250 #ifndef CONFIG_USER_ONLY 251 dc->vmsd = &vmstate_openrisc_cpu; 252 cc->sysemu_ops = &openrisc_sysemu_ops; 253 #endif 254 cc->gdb_num_core_regs = 32 + 3; 255 cc->disas_set_info = openrisc_disas_set_info; 256 cc->tcg_ops = &openrisc_tcg_ops; 257 } 258 259 /* Sort alphabetically by type name, except for "any". */ 260 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b) 261 { 262 ObjectClass *class_a = (ObjectClass *)a; 263 ObjectClass *class_b = (ObjectClass *)b; 264 const char *name_a, *name_b; 265 266 name_a = object_class_get_name(class_a); 267 name_b = object_class_get_name(class_b); 268 if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) { 269 return 1; 270 } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) { 271 return -1; 272 } else { 273 return strcmp(name_a, name_b); 274 } 275 } 276 277 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data) 278 { 279 ObjectClass *oc = data; 280 const char *typename; 281 char *name; 282 283 typename = object_class_get_name(oc); 284 name = g_strndup(typename, 285 strlen(typename) - strlen("-" TYPE_OPENRISC_CPU)); 286 qemu_printf(" %s\n", name); 287 g_free(name); 288 } 289 290 void cpu_openrisc_list(void) 291 { 292 GSList *list; 293 294 list = object_class_get_list(TYPE_OPENRISC_CPU, false); 295 list = g_slist_sort(list, openrisc_cpu_list_compare); 296 qemu_printf("Available CPUs:\n"); 297 g_slist_foreach(list, openrisc_cpu_list_entry, NULL); 298 g_slist_free(list); 299 } 300 301 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \ 302 { \ 303 .parent = TYPE_OPENRISC_CPU, \ 304 .instance_init = initfn, \ 305 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \ 306 } 307 308 static const TypeInfo openrisc_cpus_type_infos[] = { 309 { /* base class should be registered first */ 310 .name = TYPE_OPENRISC_CPU, 311 .parent = TYPE_CPU, 312 .instance_size = sizeof(OpenRISCCPU), 313 .instance_init = openrisc_cpu_initfn, 314 .abstract = true, 315 .class_size = sizeof(OpenRISCCPUClass), 316 .class_init = openrisc_cpu_class_init, 317 }, 318 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn), 319 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn), 320 }; 321 322 DEFINE_TYPES(openrisc_cpus_type_infos) 323