xref: /openbmc/qemu/target/openrisc/cpu.c (revision ab938ae4)
1 /*
2  * QEMU OpenRISC CPU
3  *
4  * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "cpu.h"
23 #include "qemu-common.h"
24 #include "exec/exec-all.h"
25 
26 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
27 {
28     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
29 
30     cpu->env.pc = value;
31 }
32 
33 static bool openrisc_cpu_has_work(CPUState *cs)
34 {
35     return cs->interrupt_request & (CPU_INTERRUPT_HARD |
36                                     CPU_INTERRUPT_TIMER);
37 }
38 
39 /* CPUClass::reset() */
40 static void openrisc_cpu_reset(CPUState *s)
41 {
42     OpenRISCCPU *cpu = OPENRISC_CPU(s);
43     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
44 
45     occ->parent_reset(s);
46 
47     memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
48 
49     cpu->env.pc = 0x100;
50     cpu->env.sr = SR_FO | SR_SM;
51     cpu->env.lock_addr = -1;
52     s->exception_index = -1;
53 
54     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP |
55                    UPR_PMP;
56     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
57     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
58 
59 #ifndef CONFIG_USER_ONLY
60     cpu->env.picmr = 0x00000000;
61     cpu->env.picsr = 0x00000000;
62 
63     cpu->env.ttmr = 0x00000000;
64     cpu->env.ttcr = 0x00000000;
65 #endif
66 }
67 
68 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
69 {
70     CPUState *cs = CPU(dev);
71     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
72     Error *local_err = NULL;
73 
74     cpu_exec_realizefn(cs, &local_err);
75     if (local_err != NULL) {
76         error_propagate(errp, local_err);
77         return;
78     }
79 
80     qemu_init_vcpu(cs);
81     cpu_reset(cs);
82 
83     occ->parent_realize(dev, errp);
84 }
85 
86 static void openrisc_cpu_initfn(Object *obj)
87 {
88     CPUState *cs = CPU(obj);
89     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
90     static int inited;
91 
92     cs->env_ptr = &cpu->env;
93 
94 #ifndef CONFIG_USER_ONLY
95     cpu_openrisc_mmu_init(cpu);
96 #endif
97 
98     if (tcg_enabled() && !inited) {
99         inited = 1;
100         openrisc_translate_init();
101     }
102 }
103 
104 /* CPU models */
105 
106 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
107 {
108     ObjectClass *oc;
109     char *typename;
110 
111     if (cpu_model == NULL) {
112         return NULL;
113     }
114 
115     typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model);
116     oc = object_class_by_name(typename);
117     g_free(typename);
118     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
119                        object_class_is_abstract(oc))) {
120         return NULL;
121     }
122     return oc;
123 }
124 
125 static void or1200_initfn(Object *obj)
126 {
127     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
128 
129     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
130                        CPUCFGR_EVBARP;
131 }
132 
133 static void openrisc_any_initfn(Object *obj)
134 {
135     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
136 
137     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP;
138 }
139 
140 typedef struct OpenRISCCPUInfo {
141     const char *name;
142     void (*initfn)(Object *obj);
143 } OpenRISCCPUInfo;
144 
145 static const OpenRISCCPUInfo openrisc_cpus[] = {
146     { .name = "or1200",      .initfn = or1200_initfn },
147     { .name = "any",         .initfn = openrisc_any_initfn },
148 };
149 
150 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
151 {
152     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
153     CPUClass *cc = CPU_CLASS(occ);
154     DeviceClass *dc = DEVICE_CLASS(oc);
155 
156     occ->parent_realize = dc->realize;
157     dc->realize = openrisc_cpu_realizefn;
158 
159     occ->parent_reset = cc->reset;
160     cc->reset = openrisc_cpu_reset;
161 
162     cc->class_by_name = openrisc_cpu_class_by_name;
163     cc->has_work = openrisc_cpu_has_work;
164     cc->do_interrupt = openrisc_cpu_do_interrupt;
165     cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
166     cc->dump_state = openrisc_cpu_dump_state;
167     cc->set_pc = openrisc_cpu_set_pc;
168     cc->gdb_read_register = openrisc_cpu_gdb_read_register;
169     cc->gdb_write_register = openrisc_cpu_gdb_write_register;
170 #ifdef CONFIG_USER_ONLY
171     cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault;
172 #else
173     cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
174     dc->vmsd = &vmstate_openrisc_cpu;
175 #endif
176     cc->gdb_num_core_regs = 32 + 3;
177 }
178 
179 static void cpu_register(const OpenRISCCPUInfo *info)
180 {
181     TypeInfo type_info = {
182         .parent = TYPE_OPENRISC_CPU,
183         .instance_size = sizeof(OpenRISCCPU),
184         .instance_init = info->initfn,
185         .class_size = sizeof(OpenRISCCPUClass),
186     };
187 
188     type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
189     type_register(&type_info);
190     g_free((void *)type_info.name);
191 }
192 
193 static const TypeInfo openrisc_cpu_type_info = {
194     .name = TYPE_OPENRISC_CPU,
195     .parent = TYPE_CPU,
196     .instance_size = sizeof(OpenRISCCPU),
197     .instance_init = openrisc_cpu_initfn,
198     .abstract = true,
199     .class_size = sizeof(OpenRISCCPUClass),
200     .class_init = openrisc_cpu_class_init,
201 };
202 
203 static void openrisc_cpu_register_types(void)
204 {
205     int i;
206 
207     type_register_static(&openrisc_cpu_type_info);
208     for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) {
209         cpu_register(&openrisc_cpus[i]);
210     }
211 }
212 
213 /* Sort alphabetically by type name, except for "any". */
214 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
215 {
216     ObjectClass *class_a = (ObjectClass *)a;
217     ObjectClass *class_b = (ObjectClass *)b;
218     const char *name_a, *name_b;
219 
220     name_a = object_class_get_name(class_a);
221     name_b = object_class_get_name(class_b);
222     if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
223         return 1;
224     } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
225         return -1;
226     } else {
227         return strcmp(name_a, name_b);
228     }
229 }
230 
231 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
232 {
233     ObjectClass *oc = data;
234     CPUListState *s = user_data;
235     const char *typename;
236     char *name;
237 
238     typename = object_class_get_name(oc);
239     name = g_strndup(typename,
240                      strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
241     (*s->cpu_fprintf)(s->file, "  %s\n",
242                       name);
243     g_free(name);
244 }
245 
246 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
247 {
248     CPUListState s = {
249         .file = f,
250         .cpu_fprintf = cpu_fprintf,
251     };
252     GSList *list;
253 
254     list = object_class_get_list(TYPE_OPENRISC_CPU, false);
255     list = g_slist_sort(list, openrisc_cpu_list_compare);
256     (*cpu_fprintf)(f, "Available CPUs:\n");
257     g_slist_foreach(list, openrisc_cpu_list_entry, &s);
258     g_slist_free(list);
259 }
260 
261 type_init(openrisc_cpu_register_types)
262