1 /* 2 * QEMU OpenRISC CPU 3 * 4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu/qemu-print.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 26 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) 27 { 28 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 29 30 cpu->env.pc = value; 31 cpu->env.dflag = 0; 32 } 33 34 static void openrisc_cpu_synchronize_from_tb(CPUState *cs, 35 const TranslationBlock *tb) 36 { 37 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 38 39 cpu->env.pc = tb->pc; 40 } 41 42 43 static bool openrisc_cpu_has_work(CPUState *cs) 44 { 45 return cs->interrupt_request & (CPU_INTERRUPT_HARD | 46 CPU_INTERRUPT_TIMER); 47 } 48 49 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) 50 { 51 info->print_insn = print_insn_or1k; 52 } 53 54 static void openrisc_cpu_reset(DeviceState *dev) 55 { 56 CPUState *s = CPU(dev); 57 OpenRISCCPU *cpu = OPENRISC_CPU(s); 58 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); 59 60 occ->parent_reset(dev); 61 62 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); 63 64 cpu->env.pc = 0x100; 65 cpu->env.sr = SR_FO | SR_SM; 66 cpu->env.lock_addr = -1; 67 s->exception_index = -1; 68 cpu_set_fpcsr(&cpu->env, 0); 69 70 #ifndef CONFIG_USER_ONLY 71 cpu->env.picmr = 0x00000000; 72 cpu->env.picsr = 0x00000000; 73 74 cpu->env.ttmr = 0x00000000; 75 #endif 76 } 77 78 #ifndef CONFIG_USER_ONLY 79 static void openrisc_cpu_set_irq(void *opaque, int irq, int level) 80 { 81 OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; 82 CPUState *cs = CPU(cpu); 83 uint32_t irq_bit; 84 85 if (irq > 31 || irq < 0) { 86 return; 87 } 88 89 irq_bit = 1U << irq; 90 91 if (level) { 92 cpu->env.picsr |= irq_bit; 93 } else { 94 cpu->env.picsr &= ~irq_bit; 95 } 96 97 if (cpu->env.picsr & cpu->env.picmr) { 98 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 99 } else { 100 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 101 cpu->env.picsr = 0; 102 } 103 } 104 #endif 105 106 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) 107 { 108 CPUState *cs = CPU(dev); 109 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); 110 Error *local_err = NULL; 111 112 cpu_exec_realizefn(cs, &local_err); 113 if (local_err != NULL) { 114 error_propagate(errp, local_err); 115 return; 116 } 117 118 qemu_init_vcpu(cs); 119 cpu_reset(cs); 120 121 occ->parent_realize(dev, errp); 122 } 123 124 static void openrisc_cpu_initfn(Object *obj) 125 { 126 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 127 128 cpu_set_cpustate_pointers(cpu); 129 130 #ifndef CONFIG_USER_ONLY 131 qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_IRQS); 132 #endif 133 } 134 135 /* CPU models */ 136 137 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) 138 { 139 ObjectClass *oc; 140 char *typename; 141 142 typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model); 143 oc = object_class_by_name(typename); 144 g_free(typename); 145 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) || 146 object_class_is_abstract(oc))) { 147 return NULL; 148 } 149 return oc; 150 } 151 152 static void or1200_initfn(Object *obj) 153 { 154 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 155 156 cpu->env.vr = 0x13000008; 157 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 158 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 159 CPUCFGR_EVBARP; 160 161 /* 1Way, TLB_SIZE entries. */ 162 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 163 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 164 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 165 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 166 } 167 168 static void openrisc_any_initfn(Object *obj) 169 { 170 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 171 172 cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */ 173 cpu->env.vr2 = 0; /* No version specific id */ 174 cpu->env.avr = 0x01030000; /* Architecture v1.3 */ 175 176 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 177 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 178 CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S; 179 180 /* 1Way, TLB_SIZE entries. */ 181 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 182 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 183 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 184 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 185 } 186 187 #ifndef CONFIG_USER_ONLY 188 #include "hw/core/sysemu-cpu-ops.h" 189 190 static const struct SysemuCPUOps openrisc_sysemu_ops = { 191 .get_phys_page_debug = openrisc_cpu_get_phys_page_debug, 192 }; 193 #endif 194 195 #include "hw/core/tcg-cpu-ops.h" 196 197 static const struct TCGCPUOps openrisc_tcg_ops = { 198 .initialize = openrisc_translate_init, 199 .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, 200 201 #ifndef CONFIG_USER_ONLY 202 .tlb_fill = openrisc_cpu_tlb_fill, 203 .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, 204 .do_interrupt = openrisc_cpu_do_interrupt, 205 #endif /* !CONFIG_USER_ONLY */ 206 }; 207 208 static void openrisc_cpu_class_init(ObjectClass *oc, void *data) 209 { 210 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); 211 CPUClass *cc = CPU_CLASS(occ); 212 DeviceClass *dc = DEVICE_CLASS(oc); 213 214 device_class_set_parent_realize(dc, openrisc_cpu_realizefn, 215 &occ->parent_realize); 216 device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset); 217 218 cc->class_by_name = openrisc_cpu_class_by_name; 219 cc->has_work = openrisc_cpu_has_work; 220 cc->dump_state = openrisc_cpu_dump_state; 221 cc->set_pc = openrisc_cpu_set_pc; 222 cc->gdb_read_register = openrisc_cpu_gdb_read_register; 223 cc->gdb_write_register = openrisc_cpu_gdb_write_register; 224 #ifndef CONFIG_USER_ONLY 225 dc->vmsd = &vmstate_openrisc_cpu; 226 cc->sysemu_ops = &openrisc_sysemu_ops; 227 #endif 228 cc->gdb_num_core_regs = 32 + 3; 229 cc->disas_set_info = openrisc_disas_set_info; 230 cc->tcg_ops = &openrisc_tcg_ops; 231 } 232 233 /* Sort alphabetically by type name, except for "any". */ 234 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b) 235 { 236 ObjectClass *class_a = (ObjectClass *)a; 237 ObjectClass *class_b = (ObjectClass *)b; 238 const char *name_a, *name_b; 239 240 name_a = object_class_get_name(class_a); 241 name_b = object_class_get_name(class_b); 242 if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) { 243 return 1; 244 } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) { 245 return -1; 246 } else { 247 return strcmp(name_a, name_b); 248 } 249 } 250 251 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data) 252 { 253 ObjectClass *oc = data; 254 const char *typename; 255 char *name; 256 257 typename = object_class_get_name(oc); 258 name = g_strndup(typename, 259 strlen(typename) - strlen("-" TYPE_OPENRISC_CPU)); 260 qemu_printf(" %s\n", name); 261 g_free(name); 262 } 263 264 void cpu_openrisc_list(void) 265 { 266 GSList *list; 267 268 list = object_class_get_list(TYPE_OPENRISC_CPU, false); 269 list = g_slist_sort(list, openrisc_cpu_list_compare); 270 qemu_printf("Available CPUs:\n"); 271 g_slist_foreach(list, openrisc_cpu_list_entry, NULL); 272 g_slist_free(list); 273 } 274 275 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \ 276 { \ 277 .parent = TYPE_OPENRISC_CPU, \ 278 .instance_init = initfn, \ 279 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \ 280 } 281 282 static const TypeInfo openrisc_cpus_type_infos[] = { 283 { /* base class should be registered first */ 284 .name = TYPE_OPENRISC_CPU, 285 .parent = TYPE_CPU, 286 .instance_size = sizeof(OpenRISCCPU), 287 .instance_init = openrisc_cpu_initfn, 288 .abstract = true, 289 .class_size = sizeof(OpenRISCCPUClass), 290 .class_init = openrisc_cpu_class_init, 291 }, 292 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn), 293 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn), 294 }; 295 296 DEFINE_TYPES(openrisc_cpus_type_infos) 297