1 /* 2 * QEMU OpenRISC CPU 3 * 4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu/qemu-print.h" 23 #include "cpu.h" 24 #include "exec/translation-block.h" 25 #include "fpu/softfloat-helpers.h" 26 #include "tcg/tcg.h" 27 28 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) 29 { 30 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 31 32 cpu->env.pc = value; 33 cpu->env.dflag = 0; 34 } 35 36 static vaddr openrisc_cpu_get_pc(CPUState *cs) 37 { 38 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 39 40 return cpu->env.pc; 41 } 42 43 static void openrisc_cpu_synchronize_from_tb(CPUState *cs, 44 const TranslationBlock *tb) 45 { 46 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 47 48 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 49 cpu->env.pc = tb->pc; 50 } 51 52 static void openrisc_restore_state_to_opc(CPUState *cs, 53 const TranslationBlock *tb, 54 const uint64_t *data) 55 { 56 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 57 58 cpu->env.pc = data[0]; 59 cpu->env.dflag = data[1] & 1; 60 if (data[1] & 2) { 61 cpu->env.ppc = cpu->env.pc - 4; 62 } 63 } 64 65 #ifndef CONFIG_USER_ONLY 66 static bool openrisc_cpu_has_work(CPUState *cs) 67 { 68 return cs->interrupt_request & (CPU_INTERRUPT_HARD | 69 CPU_INTERRUPT_TIMER); 70 } 71 #endif /* !CONFIG_USER_ONLY */ 72 73 static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) 74 { 75 CPUOpenRISCState *env = cpu_env(cs); 76 77 if (env->sr & (ifetch ? SR_IME : SR_DME)) { 78 /* The mmu is enabled; test supervisor state. */ 79 return env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; 80 } 81 82 return MMU_NOMMU_IDX; /* mmu is disabled */ 83 } 84 85 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) 86 { 87 info->endian = BFD_ENDIAN_BIG; 88 info->print_insn = print_insn_or1k; 89 } 90 91 static void openrisc_cpu_reset_hold(Object *obj, ResetType type) 92 { 93 CPUState *cs = CPU(obj); 94 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 95 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(obj); 96 97 if (occ->parent_phases.hold) { 98 occ->parent_phases.hold(obj, type); 99 } 100 101 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); 102 103 cpu->env.pc = 0x100; 104 cpu->env.sr = SR_FO | SR_SM; 105 cpu->env.lock_addr = -1; 106 cs->exception_index = -1; 107 cpu_set_fpcsr(&cpu->env, 0); 108 109 set_float_detect_tininess(float_tininess_before_rounding, 110 &cpu->env.fp_status); 111 /* 112 * TODO: this is probably not the correct NaN propagation rule for 113 * this architecture. 114 */ 115 set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); 116 117 /* Default NaN: sign bit clear, frac msb set */ 118 set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status); 119 120 #ifndef CONFIG_USER_ONLY 121 cpu->env.picmr = 0x00000000; 122 cpu->env.picsr = 0x00000000; 123 124 cpu->env.ttmr = 0x00000000; 125 #endif 126 } 127 128 #ifndef CONFIG_USER_ONLY 129 static void openrisc_cpu_set_irq(void *opaque, int irq, int level) 130 { 131 OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; 132 CPUState *cs = CPU(cpu); 133 uint32_t irq_bit; 134 135 if (irq > 31 || irq < 0) { 136 return; 137 } 138 139 irq_bit = 1U << irq; 140 141 if (level) { 142 cpu->env.picsr |= irq_bit; 143 } else { 144 cpu->env.picsr &= ~irq_bit; 145 } 146 147 if (cpu->env.picsr & cpu->env.picmr) { 148 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 149 } else { 150 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 151 } 152 } 153 #endif 154 155 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) 156 { 157 CPUState *cs = CPU(dev); 158 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); 159 Error *local_err = NULL; 160 161 cpu_exec_realizefn(cs, &local_err); 162 if (local_err != NULL) { 163 error_propagate(errp, local_err); 164 return; 165 } 166 167 qemu_init_vcpu(cs); 168 cpu_reset(cs); 169 170 #ifndef CONFIG_USER_ONLY 171 cpu_openrisc_clock_init(OPENRISC_CPU(dev)); 172 #endif 173 174 occ->parent_realize(dev, errp); 175 } 176 177 static void openrisc_cpu_initfn(Object *obj) 178 { 179 #ifndef CONFIG_USER_ONLY 180 qdev_init_gpio_in_named(DEVICE(obj), openrisc_cpu_set_irq, "IRQ", NR_IRQS); 181 #endif 182 } 183 184 /* CPU models */ 185 186 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) 187 { 188 ObjectClass *oc; 189 char *typename; 190 191 typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model); 192 oc = object_class_by_name(typename); 193 g_free(typename); 194 195 return oc; 196 } 197 198 static void or1200_initfn(Object *obj) 199 { 200 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 201 202 cpu->env.vr = 0x13000008; 203 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 204 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 205 CPUCFGR_EVBARP; 206 207 /* 1Way, TLB_SIZE entries. */ 208 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 209 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 210 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 211 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 212 } 213 214 static void openrisc_any_initfn(Object *obj) 215 { 216 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 217 218 cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */ 219 cpu->env.vr2 = 0; /* No version specific id */ 220 cpu->env.avr = 0x01030000; /* Architecture v1.3 */ 221 222 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 223 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 224 CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S; 225 226 /* 1Way, TLB_SIZE entries. */ 227 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 228 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 229 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 230 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 231 } 232 233 #ifndef CONFIG_USER_ONLY 234 #include "hw/core/sysemu-cpu-ops.h" 235 236 static const struct SysemuCPUOps openrisc_sysemu_ops = { 237 .has_work = openrisc_cpu_has_work, 238 .get_phys_page_debug = openrisc_cpu_get_phys_page_debug, 239 }; 240 #endif 241 242 #include "accel/tcg/cpu-ops.h" 243 244 static const TCGCPUOps openrisc_tcg_ops = { 245 .guest_default_memory_order = 0, 246 .mttcg_supported = true, 247 248 .initialize = openrisc_translate_init, 249 .translate_code = openrisc_translate_code, 250 .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, 251 .restore_state_to_opc = openrisc_restore_state_to_opc, 252 .mmu_index = openrisc_cpu_mmu_index, 253 254 #ifndef CONFIG_USER_ONLY 255 .tlb_fill = openrisc_cpu_tlb_fill, 256 .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, 257 .cpu_exec_halt = openrisc_cpu_has_work, 258 .do_interrupt = openrisc_cpu_do_interrupt, 259 #endif /* !CONFIG_USER_ONLY */ 260 }; 261 262 static void openrisc_cpu_class_init(ObjectClass *oc, const void *data) 263 { 264 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); 265 CPUClass *cc = CPU_CLASS(occ); 266 DeviceClass *dc = DEVICE_CLASS(oc); 267 ResettableClass *rc = RESETTABLE_CLASS(oc); 268 269 device_class_set_parent_realize(dc, openrisc_cpu_realizefn, 270 &occ->parent_realize); 271 resettable_class_set_parent_phases(rc, NULL, openrisc_cpu_reset_hold, NULL, 272 &occ->parent_phases); 273 274 cc->class_by_name = openrisc_cpu_class_by_name; 275 cc->dump_state = openrisc_cpu_dump_state; 276 cc->set_pc = openrisc_cpu_set_pc; 277 cc->get_pc = openrisc_cpu_get_pc; 278 cc->gdb_read_register = openrisc_cpu_gdb_read_register; 279 cc->gdb_write_register = openrisc_cpu_gdb_write_register; 280 #ifndef CONFIG_USER_ONLY 281 dc->vmsd = &vmstate_openrisc_cpu; 282 cc->sysemu_ops = &openrisc_sysemu_ops; 283 #endif 284 cc->gdb_num_core_regs = 32 + 3; 285 cc->disas_set_info = openrisc_disas_set_info; 286 cc->tcg_ops = &openrisc_tcg_ops; 287 } 288 289 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \ 290 { \ 291 .parent = TYPE_OPENRISC_CPU, \ 292 .instance_init = initfn, \ 293 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \ 294 } 295 296 static const TypeInfo openrisc_cpus_type_infos[] = { 297 { /* base class should be registered first */ 298 .name = TYPE_OPENRISC_CPU, 299 .parent = TYPE_CPU, 300 .instance_size = sizeof(OpenRISCCPU), 301 .instance_align = __alignof(OpenRISCCPU), 302 .instance_init = openrisc_cpu_initfn, 303 .abstract = true, 304 .class_size = sizeof(OpenRISCCPUClass), 305 .class_init = openrisc_cpu_class_init, 306 }, 307 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn), 308 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn), 309 }; 310 311 DEFINE_TYPES(openrisc_cpus_type_infos) 312