1 /* 2 * QEMU OpenRISC CPU 3 * 4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "cpu.h" 23 #include "qemu-common.h" 24 25 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) 26 { 27 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 28 29 cpu->env.pc = value; 30 cpu->env.dflag = 0; 31 } 32 33 static bool openrisc_cpu_has_work(CPUState *cs) 34 { 35 return cs->interrupt_request & (CPU_INTERRUPT_HARD | 36 CPU_INTERRUPT_TIMER); 37 } 38 39 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) 40 { 41 info->print_insn = print_insn_or1k; 42 } 43 44 /* CPUClass::reset() */ 45 static void openrisc_cpu_reset(CPUState *s) 46 { 47 OpenRISCCPU *cpu = OPENRISC_CPU(s); 48 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); 49 50 occ->parent_reset(s); 51 52 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); 53 54 cpu->env.pc = 0x100; 55 cpu->env.sr = SR_FO | SR_SM; 56 cpu->env.lock_addr = -1; 57 s->exception_index = -1; 58 59 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | 60 UPR_PMP; 61 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 62 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 63 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 64 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 65 66 #ifndef CONFIG_USER_ONLY 67 cpu->env.picmr = 0x00000000; 68 cpu->env.picsr = 0x00000000; 69 70 cpu->env.ttmr = 0x00000000; 71 #endif 72 } 73 74 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) 75 { 76 CPUState *cs = CPU(dev); 77 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); 78 Error *local_err = NULL; 79 80 cpu_exec_realizefn(cs, &local_err); 81 if (local_err != NULL) { 82 error_propagate(errp, local_err); 83 return; 84 } 85 86 qemu_init_vcpu(cs); 87 cpu_reset(cs); 88 89 occ->parent_realize(dev, errp); 90 } 91 92 static void openrisc_cpu_initfn(Object *obj) 93 { 94 CPUState *cs = CPU(obj); 95 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 96 97 cs->env_ptr = &cpu->env; 98 } 99 100 /* CPU models */ 101 102 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) 103 { 104 ObjectClass *oc; 105 char *typename; 106 107 typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model); 108 oc = object_class_by_name(typename); 109 g_free(typename); 110 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) || 111 object_class_is_abstract(oc))) { 112 return NULL; 113 } 114 return oc; 115 } 116 117 static void or1200_initfn(Object *obj) 118 { 119 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 120 121 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 122 CPUCFGR_EVBARP; 123 } 124 125 static void openrisc_any_initfn(Object *obj) 126 { 127 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 128 129 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP; 130 } 131 132 static void openrisc_cpu_class_init(ObjectClass *oc, void *data) 133 { 134 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); 135 CPUClass *cc = CPU_CLASS(occ); 136 DeviceClass *dc = DEVICE_CLASS(oc); 137 138 device_class_set_parent_realize(dc, openrisc_cpu_realizefn, 139 &occ->parent_realize); 140 occ->parent_reset = cc->reset; 141 cc->reset = openrisc_cpu_reset; 142 143 cc->class_by_name = openrisc_cpu_class_by_name; 144 cc->has_work = openrisc_cpu_has_work; 145 cc->do_interrupt = openrisc_cpu_do_interrupt; 146 cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt; 147 cc->dump_state = openrisc_cpu_dump_state; 148 cc->set_pc = openrisc_cpu_set_pc; 149 cc->gdb_read_register = openrisc_cpu_gdb_read_register; 150 cc->gdb_write_register = openrisc_cpu_gdb_write_register; 151 #ifdef CONFIG_USER_ONLY 152 cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault; 153 #else 154 cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; 155 dc->vmsd = &vmstate_openrisc_cpu; 156 #endif 157 cc->gdb_num_core_regs = 32 + 3; 158 cc->tcg_initialize = openrisc_translate_init; 159 cc->disas_set_info = openrisc_disas_set_info; 160 } 161 162 /* Sort alphabetically by type name, except for "any". */ 163 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b) 164 { 165 ObjectClass *class_a = (ObjectClass *)a; 166 ObjectClass *class_b = (ObjectClass *)b; 167 const char *name_a, *name_b; 168 169 name_a = object_class_get_name(class_a); 170 name_b = object_class_get_name(class_b); 171 if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) { 172 return 1; 173 } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) { 174 return -1; 175 } else { 176 return strcmp(name_a, name_b); 177 } 178 } 179 180 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data) 181 { 182 ObjectClass *oc = data; 183 CPUListState *s = user_data; 184 const char *typename; 185 char *name; 186 187 typename = object_class_get_name(oc); 188 name = g_strndup(typename, 189 strlen(typename) - strlen("-" TYPE_OPENRISC_CPU)); 190 (*s->cpu_fprintf)(s->file, " %s\n", 191 name); 192 g_free(name); 193 } 194 195 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf) 196 { 197 CPUListState s = { 198 .file = f, 199 .cpu_fprintf = cpu_fprintf, 200 }; 201 GSList *list; 202 203 list = object_class_get_list(TYPE_OPENRISC_CPU, false); 204 list = g_slist_sort(list, openrisc_cpu_list_compare); 205 (*cpu_fprintf)(f, "Available CPUs:\n"); 206 g_slist_foreach(list, openrisc_cpu_list_entry, &s); 207 g_slist_free(list); 208 } 209 210 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \ 211 { \ 212 .parent = TYPE_OPENRISC_CPU, \ 213 .instance_init = initfn, \ 214 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \ 215 } 216 217 static const TypeInfo openrisc_cpus_type_infos[] = { 218 { /* base class should be registered first */ 219 .name = TYPE_OPENRISC_CPU, 220 .parent = TYPE_CPU, 221 .instance_size = sizeof(OpenRISCCPU), 222 .instance_init = openrisc_cpu_initfn, 223 .abstract = true, 224 .class_size = sizeof(OpenRISCCPUClass), 225 .class_init = openrisc_cpu_class_init, 226 }, 227 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn), 228 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn), 229 }; 230 231 DEFINE_TYPES(openrisc_cpus_type_infos) 232