1 /* 2 * QEMU OpenRISC CPU 3 * 4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu/qemu-print.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 26 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) 27 { 28 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 29 30 cpu->env.pc = value; 31 cpu->env.dflag = 0; 32 } 33 34 static vaddr openrisc_cpu_get_pc(CPUState *cs) 35 { 36 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 37 38 return cpu->env.pc; 39 } 40 41 static void openrisc_cpu_synchronize_from_tb(CPUState *cs, 42 const TranslationBlock *tb) 43 { 44 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 45 46 cpu->env.pc = tb_pc(tb); 47 } 48 49 static void openrisc_restore_state_to_opc(CPUState *cs, 50 const TranslationBlock *tb, 51 const uint64_t *data) 52 { 53 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 54 55 cpu->env.pc = data[0]; 56 cpu->env.dflag = data[1] & 1; 57 if (data[1] & 2) { 58 cpu->env.ppc = cpu->env.pc - 4; 59 } 60 } 61 62 static bool openrisc_cpu_has_work(CPUState *cs) 63 { 64 return cs->interrupt_request & (CPU_INTERRUPT_HARD | 65 CPU_INTERRUPT_TIMER); 66 } 67 68 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) 69 { 70 info->print_insn = print_insn_or1k; 71 } 72 73 static void openrisc_cpu_reset_hold(Object *obj) 74 { 75 CPUState *s = CPU(obj); 76 OpenRISCCPU *cpu = OPENRISC_CPU(s); 77 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); 78 79 if (occ->parent_phases.hold) { 80 occ->parent_phases.hold(obj); 81 } 82 83 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); 84 85 cpu->env.pc = 0x100; 86 cpu->env.sr = SR_FO | SR_SM; 87 cpu->env.lock_addr = -1; 88 s->exception_index = -1; 89 cpu_set_fpcsr(&cpu->env, 0); 90 91 #ifndef CONFIG_USER_ONLY 92 cpu->env.picmr = 0x00000000; 93 cpu->env.picsr = 0x00000000; 94 95 cpu->env.ttmr = 0x00000000; 96 #endif 97 } 98 99 #ifndef CONFIG_USER_ONLY 100 static void openrisc_cpu_set_irq(void *opaque, int irq, int level) 101 { 102 OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; 103 CPUState *cs = CPU(cpu); 104 uint32_t irq_bit; 105 106 if (irq > 31 || irq < 0) { 107 return; 108 } 109 110 irq_bit = 1U << irq; 111 112 if (level) { 113 cpu->env.picsr |= irq_bit; 114 } else { 115 cpu->env.picsr &= ~irq_bit; 116 } 117 118 if (cpu->env.picsr & cpu->env.picmr) { 119 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 120 } else { 121 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 122 } 123 } 124 #endif 125 126 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) 127 { 128 CPUState *cs = CPU(dev); 129 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); 130 Error *local_err = NULL; 131 132 cpu_exec_realizefn(cs, &local_err); 133 if (local_err != NULL) { 134 error_propagate(errp, local_err); 135 return; 136 } 137 138 qemu_init_vcpu(cs); 139 cpu_reset(cs); 140 141 occ->parent_realize(dev, errp); 142 } 143 144 static void openrisc_cpu_initfn(Object *obj) 145 { 146 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 147 148 cpu_set_cpustate_pointers(cpu); 149 150 #ifndef CONFIG_USER_ONLY 151 qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_IRQS); 152 #endif 153 } 154 155 /* CPU models */ 156 157 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) 158 { 159 ObjectClass *oc; 160 char *typename; 161 162 typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model); 163 oc = object_class_by_name(typename); 164 g_free(typename); 165 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) || 166 object_class_is_abstract(oc))) { 167 return NULL; 168 } 169 return oc; 170 } 171 172 static void or1200_initfn(Object *obj) 173 { 174 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 175 176 cpu->env.vr = 0x13000008; 177 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 178 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 179 CPUCFGR_EVBARP; 180 181 /* 1Way, TLB_SIZE entries. */ 182 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 183 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 184 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 185 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 186 } 187 188 static void openrisc_any_initfn(Object *obj) 189 { 190 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 191 192 cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */ 193 cpu->env.vr2 = 0; /* No version specific id */ 194 cpu->env.avr = 0x01030000; /* Architecture v1.3 */ 195 196 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 197 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 198 CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S; 199 200 /* 1Way, TLB_SIZE entries. */ 201 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 202 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 203 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 204 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 205 } 206 207 #ifndef CONFIG_USER_ONLY 208 #include "hw/core/sysemu-cpu-ops.h" 209 210 static const struct SysemuCPUOps openrisc_sysemu_ops = { 211 .get_phys_page_debug = openrisc_cpu_get_phys_page_debug, 212 }; 213 #endif 214 215 #include "hw/core/tcg-cpu-ops.h" 216 217 static const struct TCGCPUOps openrisc_tcg_ops = { 218 .initialize = openrisc_translate_init, 219 .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, 220 .restore_state_to_opc = openrisc_restore_state_to_opc, 221 222 #ifndef CONFIG_USER_ONLY 223 .tlb_fill = openrisc_cpu_tlb_fill, 224 .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, 225 .do_interrupt = openrisc_cpu_do_interrupt, 226 #endif /* !CONFIG_USER_ONLY */ 227 }; 228 229 static void openrisc_cpu_class_init(ObjectClass *oc, void *data) 230 { 231 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); 232 CPUClass *cc = CPU_CLASS(occ); 233 DeviceClass *dc = DEVICE_CLASS(oc); 234 ResettableClass *rc = RESETTABLE_CLASS(oc); 235 236 device_class_set_parent_realize(dc, openrisc_cpu_realizefn, 237 &occ->parent_realize); 238 resettable_class_set_parent_phases(rc, NULL, openrisc_cpu_reset_hold, NULL, 239 &occ->parent_phases); 240 241 cc->class_by_name = openrisc_cpu_class_by_name; 242 cc->has_work = openrisc_cpu_has_work; 243 cc->dump_state = openrisc_cpu_dump_state; 244 cc->set_pc = openrisc_cpu_set_pc; 245 cc->get_pc = openrisc_cpu_get_pc; 246 cc->gdb_read_register = openrisc_cpu_gdb_read_register; 247 cc->gdb_write_register = openrisc_cpu_gdb_write_register; 248 #ifndef CONFIG_USER_ONLY 249 dc->vmsd = &vmstate_openrisc_cpu; 250 cc->sysemu_ops = &openrisc_sysemu_ops; 251 #endif 252 cc->gdb_num_core_regs = 32 + 3; 253 cc->disas_set_info = openrisc_disas_set_info; 254 cc->tcg_ops = &openrisc_tcg_ops; 255 } 256 257 /* Sort alphabetically by type name, except for "any". */ 258 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b) 259 { 260 ObjectClass *class_a = (ObjectClass *)a; 261 ObjectClass *class_b = (ObjectClass *)b; 262 const char *name_a, *name_b; 263 264 name_a = object_class_get_name(class_a); 265 name_b = object_class_get_name(class_b); 266 if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) { 267 return 1; 268 } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) { 269 return -1; 270 } else { 271 return strcmp(name_a, name_b); 272 } 273 } 274 275 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data) 276 { 277 ObjectClass *oc = data; 278 const char *typename; 279 char *name; 280 281 typename = object_class_get_name(oc); 282 name = g_strndup(typename, 283 strlen(typename) - strlen("-" TYPE_OPENRISC_CPU)); 284 qemu_printf(" %s\n", name); 285 g_free(name); 286 } 287 288 void cpu_openrisc_list(void) 289 { 290 GSList *list; 291 292 list = object_class_get_list(TYPE_OPENRISC_CPU, false); 293 list = g_slist_sort(list, openrisc_cpu_list_compare); 294 qemu_printf("Available CPUs:\n"); 295 g_slist_foreach(list, openrisc_cpu_list_entry, NULL); 296 g_slist_free(list); 297 } 298 299 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \ 300 { \ 301 .parent = TYPE_OPENRISC_CPU, \ 302 .instance_init = initfn, \ 303 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \ 304 } 305 306 static const TypeInfo openrisc_cpus_type_infos[] = { 307 { /* base class should be registered first */ 308 .name = TYPE_OPENRISC_CPU, 309 .parent = TYPE_CPU, 310 .instance_size = sizeof(OpenRISCCPU), 311 .instance_init = openrisc_cpu_initfn, 312 .abstract = true, 313 .class_size = sizeof(OpenRISCCPUClass), 314 .class_init = openrisc_cpu_class_init, 315 }, 316 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn), 317 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn), 318 }; 319 320 DEFINE_TYPES(openrisc_cpus_type_infos) 321