1 /*
2  * Address Computation and Large Constant Instructions
3  *
4  *  Copyright (c) 2004-2005 Jocelyn Mayer
5  *  Copyright (c) 2006 Marius Groeger (FPU operations)
6  *  Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7  *  Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
8  *  Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
9  *  Copyright (c) 2020 Philippe Mathieu-Daudé
10  *
11  * SPDX-License-Identifier: LGPL-2.1-or-later
12  */
13 #include "qemu/osdep.h"
14 #include "tcg/tcg-op.h"
15 #include "translate.h"
16 
17 bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
18 {
19     TCGv t0;
20     TCGv t1;
21 
22     if (rd == 0) {
23         /* Treat as NOP. */
24         return true;
25     }
26     t0 = tcg_temp_new();
27     t1 = tcg_temp_new();
28     gen_load_gpr(t0, rs);
29     gen_load_gpr(t1, rt);
30     tcg_gen_shli_tl(t0, t0, sa + 1);
31     tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
32     tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
33     return true;
34 }
35 
36 bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
37 {
38     TCGv t0;
39     TCGv t1;
40 
41     check_mips_64(ctx);
42 
43     if (rd == 0) {
44         /* Treat as NOP. */
45         return true;
46     }
47     t0 = tcg_temp_new();
48     t1 = tcg_temp_new();
49     gen_load_gpr(t0, rs);
50     gen_load_gpr(t1, rt);
51     tcg_gen_shli_tl(t0, t0, sa + 1);
52     tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
53     return true;
54 }
55