xref: /openbmc/qemu/target/mips/tcg/tcg-internal.h (revision 2f44bea9)
1 /*
2  * MIPS internal definitions and helpers (TCG accelerator)
3  *
4  * SPDX-License-Identifier: GPL-2.0-or-later
5  *
6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
7  * See the COPYING file in the top-level directory.
8  */
9 
10 #ifndef MIPS_TCG_INTERNAL_H
11 #define MIPS_TCG_INTERNAL_H
12 
13 #include "tcg/tcg.h"
14 #include "exec/memattrs.h"
15 #include "hw/core/cpu.h"
16 #include "cpu.h"
17 
18 void mips_tcg_init(void);
19 
20 void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
21 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
22                        MMUAccessType access_type, int mmu_idx,
23                        bool probe, uintptr_t retaddr);
24 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
25                                   MMUAccessType access_type, int mmu_idx,
26                                   uintptr_t retaddr) QEMU_NORETURN;
27 
28 const char *mips_exception_name(int32_t exception);
29 
30 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
31                                           int error_code, uintptr_t pc);
32 
33 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
34                                                     uint32_t exception,
35                                                     uintptr_t pc)
36 {
37     do_raise_exception_err(env, exception, 0, pc);
38 }
39 
40 #if !defined(CONFIG_USER_ONLY)
41 
42 void mips_cpu_do_interrupt(CPUState *cpu);
43 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
44 
45 void mmu_init(CPUMIPSState *env, const mips_def_t *def);
46 
47 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
48 
49 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
50 uint32_t cpu_mips_get_random(CPUMIPSState *env);
51 
52 bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb);
53 
54 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
55                                   MMUAccessType access_type, uintptr_t retaddr);
56 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
57                                     vaddr addr, unsigned size,
58                                     MMUAccessType access_type,
59                                     int mmu_idx, MemTxAttrs attrs,
60                                     MemTxResult response, uintptr_t retaddr);
61 void cpu_mips_tlb_flush(CPUMIPSState *env);
62 
63 #endif /* !CONFIG_USER_ONLY */
64 
65 #endif
66