1 /* 2 * MIPS TLB (Translation lookaside buffer) helpers. 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 21 #include "cpu.h" 22 #include "internal.h" 23 #include "exec/exec-all.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/log.h" 26 #include "hw/mips/cpudevs.h" 27 #include "exec/helper-proto.h" 28 29 /* TLB management */ 30 static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) 31 { 32 /* Discard entries from env->tlb[first] onwards. */ 33 while (env->tlb->tlb_in_use > first) { 34 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); 35 } 36 } 37 38 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo) 39 { 40 #if defined(TARGET_MIPS64) 41 return extract64(entrylo, 6, 54); 42 #else 43 return extract64(entrylo, 6, 24) | /* PFN */ 44 (extract64(entrylo, 32, 32) << 24); /* PFNX */ 45 #endif 46 } 47 48 static void r4k_fill_tlb(CPUMIPSState *env, int idx) 49 { 50 r4k_tlb_t *tlb; 51 uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1); 52 53 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ 54 tlb = &env->tlb->mmu.r4k.tlb[idx]; 55 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) { 56 tlb->EHINV = 1; 57 return; 58 } 59 tlb->EHINV = 0; 60 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); 61 #if defined(TARGET_MIPS64) 62 tlb->VPN &= env->SEGMask; 63 #endif 64 tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; 65 tlb->MMID = env->CP0_MemoryMapID; 66 tlb->PageMask = env->CP0_PageMask; 67 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; 68 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; 69 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; 70 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; 71 tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1; 72 tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1; 73 tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12; 74 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; 75 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; 76 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; 77 tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1; 78 tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1; 79 tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12; 80 } 81 82 static void r4k_helper_tlbinv(CPUMIPSState *env) 83 { 84 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); 85 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; 86 uint32_t MMID = env->CP0_MemoryMapID; 87 uint32_t tlb_mmid; 88 r4k_tlb_t *tlb; 89 int idx; 90 91 MMID = mi ? MMID : (uint32_t) ASID; 92 for (idx = 0; idx < env->tlb->nb_tlb; idx++) { 93 tlb = &env->tlb->mmu.r4k.tlb[idx]; 94 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; 95 if (!tlb->G && tlb_mmid == MMID) { 96 tlb->EHINV = 1; 97 } 98 } 99 cpu_mips_tlb_flush(env); 100 } 101 102 static void r4k_helper_tlbinvf(CPUMIPSState *env) 103 { 104 int idx; 105 106 for (idx = 0; idx < env->tlb->nb_tlb; idx++) { 107 env->tlb->mmu.r4k.tlb[idx].EHINV = 1; 108 } 109 cpu_mips_tlb_flush(env); 110 } 111 112 static void r4k_helper_tlbwi(CPUMIPSState *env) 113 { 114 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); 115 target_ulong VPN; 116 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; 117 uint32_t MMID = env->CP0_MemoryMapID; 118 uint32_t tlb_mmid; 119 bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1; 120 r4k_tlb_t *tlb; 121 int idx; 122 123 MMID = mi ? MMID : (uint32_t) ASID; 124 125 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; 126 tlb = &env->tlb->mmu.r4k.tlb[idx]; 127 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); 128 #if defined(TARGET_MIPS64) 129 VPN &= env->SEGMask; 130 #endif 131 EHINV = (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) != 0; 132 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; 133 V0 = (env->CP0_EntryLo0 & 2) != 0; 134 D0 = (env->CP0_EntryLo0 & 4) != 0; 135 XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) &1; 136 RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) &1; 137 V1 = (env->CP0_EntryLo1 & 2) != 0; 138 D1 = (env->CP0_EntryLo1 & 4) != 0; 139 XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1; 140 RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1; 141 142 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; 143 /* 144 * Discard cached TLB entries, unless tlbwi is just upgrading access 145 * permissions on the current entry. 146 */ 147 if (tlb->VPN != VPN || tlb_mmid != MMID || tlb->G != G || 148 (!tlb->EHINV && EHINV) || 149 (tlb->V0 && !V0) || (tlb->D0 && !D0) || 150 (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) || 151 (tlb->V1 && !V1) || (tlb->D1 && !D1) || 152 (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) { 153 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); 154 } 155 156 r4k_invalidate_tlb(env, idx, 0); 157 r4k_fill_tlb(env, idx); 158 } 159 160 static void r4k_helper_tlbwr(CPUMIPSState *env) 161 { 162 int r = cpu_mips_get_random(env); 163 164 r4k_invalidate_tlb(env, r, 1); 165 r4k_fill_tlb(env, r); 166 } 167 168 static void r4k_helper_tlbp(CPUMIPSState *env) 169 { 170 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); 171 r4k_tlb_t *tlb; 172 target_ulong mask; 173 target_ulong tag; 174 target_ulong VPN; 175 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; 176 uint32_t MMID = env->CP0_MemoryMapID; 177 uint32_t tlb_mmid; 178 int i; 179 180 MMID = mi ? MMID : (uint32_t) ASID; 181 for (i = 0; i < env->tlb->nb_tlb; i++) { 182 tlb = &env->tlb->mmu.r4k.tlb[i]; 183 /* 1k pages are not supported. */ 184 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); 185 tag = env->CP0_EntryHi & ~mask; 186 VPN = tlb->VPN & ~mask; 187 #if defined(TARGET_MIPS64) 188 tag &= env->SEGMask; 189 #endif 190 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; 191 /* Check ASID/MMID, virtual page number & size */ 192 if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag && !tlb->EHINV) { 193 /* TLB match */ 194 env->CP0_Index = i; 195 break; 196 } 197 } 198 if (i == env->tlb->nb_tlb) { 199 /* No match. Discard any shadow entries, if any of them match. */ 200 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { 201 tlb = &env->tlb->mmu.r4k.tlb[i]; 202 /* 1k pages are not supported. */ 203 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); 204 tag = env->CP0_EntryHi & ~mask; 205 VPN = tlb->VPN & ~mask; 206 #if defined(TARGET_MIPS64) 207 tag &= env->SEGMask; 208 #endif 209 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; 210 /* Check ASID/MMID, virtual page number & size */ 211 if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag) { 212 r4k_mips_tlb_flush_extra(env, i); 213 break; 214 } 215 } 216 217 env->CP0_Index |= 0x80000000; 218 } 219 } 220 221 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) 222 { 223 #if defined(TARGET_MIPS64) 224 return tlb_pfn << 6; 225 #else 226 return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */ 227 (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */ 228 #endif 229 } 230 231 static void r4k_helper_tlbr(CPUMIPSState *env) 232 { 233 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); 234 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; 235 uint32_t MMID = env->CP0_MemoryMapID; 236 uint32_t tlb_mmid; 237 r4k_tlb_t *tlb; 238 int idx; 239 240 MMID = mi ? MMID : (uint32_t) ASID; 241 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; 242 tlb = &env->tlb->mmu.r4k.tlb[idx]; 243 244 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; 245 /* If this will change the current ASID/MMID, flush qemu's TLB. */ 246 if (MMID != tlb_mmid) { 247 cpu_mips_tlb_flush(env); 248 } 249 250 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); 251 252 if (tlb->EHINV) { 253 env->CP0_EntryHi = 1 << CP0EnHi_EHINV; 254 env->CP0_PageMask = 0; 255 env->CP0_EntryLo0 = 0; 256 env->CP0_EntryLo1 = 0; 257 } else { 258 env->CP0_EntryHi = mi ? tlb->VPN : tlb->VPN | tlb->ASID; 259 env->CP0_MemoryMapID = tlb->MMID; 260 env->CP0_PageMask = tlb->PageMask; 261 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | 262 ((uint64_t)tlb->RI0 << CP0EnLo_RI) | 263 ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) | 264 get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12); 265 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | 266 ((uint64_t)tlb->RI1 << CP0EnLo_RI) | 267 ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) | 268 get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12); 269 } 270 } 271 272 void helper_tlbwi(CPUMIPSState *env) 273 { 274 env->tlb->helper_tlbwi(env); 275 } 276 277 void helper_tlbwr(CPUMIPSState *env) 278 { 279 env->tlb->helper_tlbwr(env); 280 } 281 282 void helper_tlbp(CPUMIPSState *env) 283 { 284 env->tlb->helper_tlbp(env); 285 } 286 287 void helper_tlbr(CPUMIPSState *env) 288 { 289 env->tlb->helper_tlbr(env); 290 } 291 292 void helper_tlbinv(CPUMIPSState *env) 293 { 294 env->tlb->helper_tlbinv(env); 295 } 296 297 void helper_tlbinvf(CPUMIPSState *env) 298 { 299 env->tlb->helper_tlbinvf(env); 300 } 301 302 static void global_invalidate_tlb(CPUMIPSState *env, 303 uint32_t invMsgVPN2, 304 uint8_t invMsgR, 305 uint32_t invMsgMMid, 306 bool invAll, 307 bool invVAMMid, 308 bool invMMid, 309 bool invVA) 310 { 311 312 int idx; 313 r4k_tlb_t *tlb; 314 bool VAMatch; 315 bool MMidMatch; 316 317 for (idx = 0; idx < env->tlb->nb_tlb; idx++) { 318 tlb = &env->tlb->mmu.r4k.tlb[idx]; 319 VAMatch = 320 (((tlb->VPN & ~tlb->PageMask) == (invMsgVPN2 & ~tlb->PageMask)) 321 #ifdef TARGET_MIPS64 322 && 323 (extract64(env->CP0_EntryHi, 62, 2) == invMsgR) 324 #endif 325 ); 326 MMidMatch = tlb->MMID == invMsgMMid; 327 if ((invAll && (idx > env->CP0_Wired)) || 328 (VAMatch && invVAMMid && (tlb->G || MMidMatch)) || 329 (VAMatch && invVA) || 330 (MMidMatch && !(tlb->G) && invMMid)) { 331 tlb->EHINV = 1; 332 } 333 } 334 cpu_mips_tlb_flush(env); 335 } 336 337 void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type) 338 { 339 bool invAll = type == 0; 340 bool invVA = type == 1; 341 bool invMMid = type == 2; 342 bool invVAMMid = type == 3; 343 uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1); 344 uint8_t invMsgR = 0; 345 uint32_t invMsgMMid = env->CP0_MemoryMapID; 346 CPUState *other_cs = first_cpu; 347 348 #ifdef TARGET_MIPS64 349 invMsgR = extract64(arg, 62, 2); 350 #endif 351 352 CPU_FOREACH(other_cs) { 353 MIPSCPU *other_cpu = MIPS_CPU(other_cs); 354 global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsgMMid, 355 invAll, invVAMMid, invMMid, invVA); 356 } 357 } 358 359 /* no MMU emulation */ 360 static int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, 361 target_ulong address, MMUAccessType access_type) 362 { 363 *physical = address; 364 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 365 return TLBRET_MATCH; 366 } 367 368 /* fixed mapping MMU emulation */ 369 static int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, 370 int *prot, target_ulong address, 371 MMUAccessType access_type) 372 { 373 if (address <= (int32_t)0x7FFFFFFFUL) { 374 if (!(env->CP0_Status & (1 << CP0St_ERL))) { 375 *physical = address + 0x40000000UL; 376 } else { 377 *physical = address; 378 } 379 } else if (address <= (int32_t)0xBFFFFFFFUL) { 380 *physical = address & 0x1FFFFFFF; 381 } else { 382 *physical = address; 383 } 384 385 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 386 return TLBRET_MATCH; 387 } 388 389 /* MIPS32/MIPS64 R4000-style MMU emulation */ 390 static int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, 391 target_ulong address, MMUAccessType access_type) 392 { 393 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; 394 uint32_t MMID = env->CP0_MemoryMapID; 395 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); 396 uint32_t tlb_mmid; 397 int i; 398 399 MMID = mi ? MMID : (uint32_t) ASID; 400 401 for (i = 0; i < env->tlb->tlb_in_use; i++) { 402 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; 403 /* 1k pages are not supported. */ 404 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); 405 target_ulong tag = address & ~mask; 406 target_ulong VPN = tlb->VPN & ~mask; 407 #if defined(TARGET_MIPS64) 408 tag &= env->SEGMask; 409 #endif 410 411 /* Check ASID/MMID, virtual page number & size */ 412 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; 413 if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag && !tlb->EHINV) { 414 /* TLB match */ 415 int n = !!(address & mask & ~(mask >> 1)); 416 /* Check access rights */ 417 if (!(n ? tlb->V1 : tlb->V0)) { 418 return TLBRET_INVALID; 419 } 420 if (access_type == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) { 421 return TLBRET_XI; 422 } 423 if (access_type == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) { 424 return TLBRET_RI; 425 } 426 if (access_type != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) { 427 *physical = tlb->PFN[n] | (address & (mask >> 1)); 428 *prot = PAGE_READ; 429 if (n ? tlb->D1 : tlb->D0) { 430 *prot |= PAGE_WRITE; 431 } 432 if (!(n ? tlb->XI1 : tlb->XI0)) { 433 *prot |= PAGE_EXEC; 434 } 435 return TLBRET_MATCH; 436 } 437 return TLBRET_DIRTY; 438 } 439 } 440 return TLBRET_NOMATCH; 441 } 442 443 static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def) 444 { 445 env->tlb->nb_tlb = 1; 446 env->tlb->map_address = &no_mmu_map_address; 447 } 448 449 static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def) 450 { 451 env->tlb->nb_tlb = 1; 452 env->tlb->map_address = &fixed_mmu_map_address; 453 } 454 455 static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) 456 { 457 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); 458 env->tlb->map_address = &r4k_map_address; 459 env->tlb->helper_tlbwi = r4k_helper_tlbwi; 460 env->tlb->helper_tlbwr = r4k_helper_tlbwr; 461 env->tlb->helper_tlbp = r4k_helper_tlbp; 462 env->tlb->helper_tlbr = r4k_helper_tlbr; 463 env->tlb->helper_tlbinv = r4k_helper_tlbinv; 464 env->tlb->helper_tlbinvf = r4k_helper_tlbinvf; 465 } 466 467 void mmu_init(CPUMIPSState *env, const mips_def_t *def) 468 { 469 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); 470 471 switch (def->mmu_type) { 472 case MMU_TYPE_NONE: 473 no_mmu_init(env, def); 474 break; 475 case MMU_TYPE_R4000: 476 r4k_mmu_init(env, def); 477 break; 478 case MMU_TYPE_FMT: 479 fixed_mmu_init(env, def); 480 break; 481 case MMU_TYPE_R3000: 482 case MMU_TYPE_R6000: 483 case MMU_TYPE_R8000: 484 default: 485 cpu_abort(env_cpu(env), "MMU type not supported\n"); 486 } 487 } 488 489 void cpu_mips_tlb_flush(CPUMIPSState *env) 490 { 491 /* Flush qemu's TLB and discard all shadowed entries. */ 492 tlb_flush(env_cpu(env)); 493 env->tlb->tlb_in_use = env->tlb->nb_tlb; 494 } 495 496 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, 497 MMUAccessType access_type, int tlb_error) 498 { 499 CPUState *cs = env_cpu(env); 500 int exception = 0, error_code = 0; 501 502 if (access_type == MMU_INST_FETCH) { 503 error_code |= EXCP_INST_NOTAVAIL; 504 } 505 506 switch (tlb_error) { 507 default: 508 case TLBRET_BADADDR: 509 /* Reference to kernel address from user mode or supervisor mode */ 510 /* Reference to supervisor address from user mode */ 511 if (access_type == MMU_DATA_STORE) { 512 exception = EXCP_AdES; 513 } else { 514 exception = EXCP_AdEL; 515 } 516 break; 517 case TLBRET_NOMATCH: 518 /* No TLB match for a mapped address */ 519 if (access_type == MMU_DATA_STORE) { 520 exception = EXCP_TLBS; 521 } else { 522 exception = EXCP_TLBL; 523 } 524 error_code |= EXCP_TLB_NOMATCH; 525 break; 526 case TLBRET_INVALID: 527 /* TLB match with no valid bit */ 528 if (access_type == MMU_DATA_STORE) { 529 exception = EXCP_TLBS; 530 } else { 531 exception = EXCP_TLBL; 532 } 533 break; 534 case TLBRET_DIRTY: 535 /* TLB match but 'D' bit is cleared */ 536 exception = EXCP_LTLBL; 537 break; 538 case TLBRET_XI: 539 /* Execute-Inhibit Exception */ 540 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) { 541 exception = EXCP_TLBXI; 542 } else { 543 exception = EXCP_TLBL; 544 } 545 break; 546 case TLBRET_RI: 547 /* Read-Inhibit Exception */ 548 if (env->CP0_PageGrain & (1 << CP0PG_IEC)) { 549 exception = EXCP_TLBRI; 550 } else { 551 exception = EXCP_TLBL; 552 } 553 break; 554 } 555 /* Raise exception */ 556 if (!(env->hflags & MIPS_HFLAG_DM)) { 557 env->CP0_BadVAddr = address; 558 } 559 env->CP0_Context = (env->CP0_Context & ~0x007fffff) | 560 ((address >> 9) & 0x007ffff0); 561 env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) | 562 (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) | 563 (address & (TARGET_PAGE_MASK << 1)); 564 #if defined(TARGET_MIPS64) 565 env->CP0_EntryHi &= env->SEGMask; 566 env->CP0_XContext = 567 (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | /* PTEBase */ 568 (extract64(address, 62, 2) << (env->SEGBITS - 9)) | /* R */ 569 (extract64(address, 13, env->SEGBITS - 13) << 4); /* BadVPN2 */ 570 #endif 571 cs->exception_index = exception; 572 env->error_code = error_code; 573 } 574 575 #if !defined(TARGET_MIPS64) 576 577 /* 578 * Perform hardware page table walk 579 * 580 * Memory accesses are performed using the KERNEL privilege level. 581 * Synchronous exceptions detected on memory accesses cause a silent exit 582 * from page table walking, resulting in a TLB or XTLB Refill exception. 583 * 584 * Implementations are not required to support page table walk memory 585 * accesses from mapped memory regions. When an unsupported access is 586 * attempted, a silent exit is taken, resulting in a TLB or XTLB Refill 587 * exception. 588 * 589 * Note that if an exception is caused by AddressTranslation or LoadMemory 590 * functions, the exception is not taken, a silent exit is taken, 591 * resulting in a TLB or XTLB Refill exception. 592 */ 593 594 static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size, 595 uint64_t *pte) 596 { 597 if ((vaddr & ((entry_size >> 3) - 1)) != 0) { 598 return false; 599 } 600 if (entry_size == 64) { 601 *pte = cpu_ldq_code(env, vaddr); 602 } else { 603 *pte = cpu_ldl_code(env, vaddr); 604 } 605 return true; 606 } 607 608 static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry, 609 int entry_size, int ptei) 610 { 611 uint64_t result = entry; 612 uint64_t rixi; 613 if (ptei > entry_size) { 614 ptei -= 32; 615 } 616 result >>= (ptei - 2); 617 rixi = result & 3; 618 result >>= 2; 619 result |= rixi << CP0EnLo_XI; 620 return result; 621 } 622 623 static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, 624 int directory_index, bool *huge_page, bool *hgpg_directory_hit, 625 uint64_t *pw_entrylo0, uint64_t *pw_entrylo1) 626 { 627 int dph = (env->CP0_PWCtl >> CP0PC_DPH) & 0x1; 628 int psn = (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F; 629 int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1; 630 int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; 631 int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F; 632 int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3; 633 int directory_shift = (ptew > 1) ? -1 : 634 (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift; 635 int leaf_shift = (ptew > 1) ? -1 : 636 (ptew == 1) ? native_shift + 1 : native_shift; 637 uint32_t direntry_size = 1 << (directory_shift + 3); 638 uint32_t leafentry_size = 1 << (leaf_shift + 3); 639 uint64_t entry; 640 uint64_t paddr; 641 int prot; 642 uint64_t lsb = 0; 643 uint64_t w = 0; 644 645 if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD, 646 cpu_mmu_index(env, false)) != 647 TLBRET_MATCH) { 648 /* wrong base address */ 649 return 0; 650 } 651 if (!get_pte(env, *vaddr, direntry_size, &entry)) { 652 return 0; 653 } 654 655 if ((entry & (1 << psn)) && hugepg) { 656 *huge_page = true; 657 *hgpg_directory_hit = true; 658 entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew); 659 w = directory_index - 1; 660 if (directory_index & 0x1) { 661 /* Generate adjacent page from same PTE for odd TLB page */ 662 lsb = (1 << w) >> 6; 663 *pw_entrylo0 = entry & ~lsb; /* even page */ 664 *pw_entrylo1 = entry | lsb; /* odd page */ 665 } else if (dph) { 666 int oddpagebit = 1 << leaf_shift; 667 uint64_t vaddr2 = *vaddr ^ oddpagebit; 668 if (*vaddr & oddpagebit) { 669 *pw_entrylo1 = entry; 670 } else { 671 *pw_entrylo0 = entry; 672 } 673 if (get_physical_address(env, &paddr, &prot, vaddr2, MMU_DATA_LOAD, 674 cpu_mmu_index(env, false)) != 675 TLBRET_MATCH) { 676 return 0; 677 } 678 if (!get_pte(env, vaddr2, leafentry_size, &entry)) { 679 return 0; 680 } 681 entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew); 682 if (*vaddr & oddpagebit) { 683 *pw_entrylo0 = entry; 684 } else { 685 *pw_entrylo1 = entry; 686 } 687 } else { 688 return 0; 689 } 690 return 1; 691 } else { 692 *vaddr = entry; 693 return 2; 694 } 695 } 696 697 static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, 698 int mmu_idx) 699 { 700 int gdw = (env->CP0_PWSize >> CP0PS_GDW) & 0x3F; 701 int udw = (env->CP0_PWSize >> CP0PS_UDW) & 0x3F; 702 int mdw = (env->CP0_PWSize >> CP0PS_MDW) & 0x3F; 703 int ptw = (env->CP0_PWSize >> CP0PS_PTW) & 0x3F; 704 int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F; 705 706 /* Initial values */ 707 bool huge_page = false; 708 bool hgpg_bdhit = false; 709 bool hgpg_gdhit = false; 710 bool hgpg_udhit = false; 711 bool hgpg_mdhit = false; 712 713 int32_t pw_pagemask = 0; 714 target_ulong pw_entryhi = 0; 715 uint64_t pw_entrylo0 = 0; 716 uint64_t pw_entrylo1 = 0; 717 718 /* Native pointer size */ 719 /*For the 32-bit architectures, this bit is fixed to 0.*/ 720 int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3; 721 722 /* Indices from PWField */ 723 int pf_gdw = (env->CP0_PWField >> CP0PF_GDW) & 0x3F; 724 int pf_udw = (env->CP0_PWField >> CP0PF_UDW) & 0x3F; 725 int pf_mdw = (env->CP0_PWField >> CP0PF_MDW) & 0x3F; 726 int pf_ptw = (env->CP0_PWField >> CP0PF_PTW) & 0x3F; 727 int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; 728 729 /* Indices computed from faulting address */ 730 int gindex = (address >> pf_gdw) & ((1 << gdw) - 1); 731 int uindex = (address >> pf_udw) & ((1 << udw) - 1); 732 int mindex = (address >> pf_mdw) & ((1 << mdw) - 1); 733 int ptindex = (address >> pf_ptw) & ((1 << ptw) - 1); 734 735 /* Other HTW configs */ 736 int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1; 737 738 /* HTW Shift values (depend on entry size) */ 739 int directory_shift = (ptew > 1) ? -1 : 740 (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift; 741 int leaf_shift = (ptew > 1) ? -1 : 742 (ptew == 1) ? native_shift + 1 : native_shift; 743 744 /* Offsets into tables */ 745 int goffset = gindex << directory_shift; 746 int uoffset = uindex << directory_shift; 747 int moffset = mindex << directory_shift; 748 int ptoffset0 = (ptindex >> 1) << (leaf_shift + 1); 749 int ptoffset1 = ptoffset0 | (1 << (leaf_shift)); 750 751 uint32_t leafentry_size = 1 << (leaf_shift + 3); 752 753 /* Starting address - Page Table Base */ 754 uint64_t vaddr = env->CP0_PWBase; 755 756 uint64_t dir_entry; 757 uint64_t paddr; 758 int prot; 759 int m; 760 761 if (!(env->CP0_Config3 & (1 << CP0C3_PW))) { 762 /* walker is unimplemented */ 763 return false; 764 } 765 if (!(env->CP0_PWCtl & (1 << CP0PC_PWEN))) { 766 /* walker is disabled */ 767 return false; 768 } 769 if (!(gdw > 0 || udw > 0 || mdw > 0)) { 770 /* no structure to walk */ 771 return false; 772 } 773 if ((directory_shift == -1) || (leaf_shift == -1)) { 774 return false; 775 } 776 777 /* Global Directory */ 778 if (gdw > 0) { 779 vaddr |= goffset; 780 switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhit, 781 &pw_entrylo0, &pw_entrylo1)) 782 { 783 case 0: 784 return false; 785 case 1: 786 goto refill; 787 case 2: 788 default: 789 break; 790 } 791 } 792 793 /* Upper directory */ 794 if (udw > 0) { 795 vaddr |= uoffset; 796 switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhit, 797 &pw_entrylo0, &pw_entrylo1)) 798 { 799 case 0: 800 return false; 801 case 1: 802 goto refill; 803 case 2: 804 default: 805 break; 806 } 807 } 808 809 /* Middle directory */ 810 if (mdw > 0) { 811 vaddr |= moffset; 812 switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhit, 813 &pw_entrylo0, &pw_entrylo1)) 814 { 815 case 0: 816 return false; 817 case 1: 818 goto refill; 819 case 2: 820 default: 821 break; 822 } 823 } 824 825 /* Leaf Level Page Table - First half of PTE pair */ 826 vaddr |= ptoffset0; 827 if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD, 828 cpu_mmu_index(env, false)) != 829 TLBRET_MATCH) { 830 return false; 831 } 832 if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { 833 return false; 834 } 835 dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew); 836 pw_entrylo0 = dir_entry; 837 838 /* Leaf Level Page Table - Second half of PTE pair */ 839 vaddr |= ptoffset1; 840 if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD, 841 cpu_mmu_index(env, false)) != 842 TLBRET_MATCH) { 843 return false; 844 } 845 if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { 846 return false; 847 } 848 dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew); 849 pw_entrylo1 = dir_entry; 850 851 refill: 852 853 m = (1 << pf_ptw) - 1; 854 855 if (huge_page) { 856 switch (hgpg_bdhit << 3 | hgpg_gdhit << 2 | hgpg_udhit << 1 | 857 hgpg_mdhit) 858 { 859 case 4: 860 m = (1 << pf_gdw) - 1; 861 if (pf_gdw & 1) { 862 m >>= 1; 863 } 864 break; 865 case 2: 866 m = (1 << pf_udw) - 1; 867 if (pf_udw & 1) { 868 m >>= 1; 869 } 870 break; 871 case 1: 872 m = (1 << pf_mdw) - 1; 873 if (pf_mdw & 1) { 874 m >>= 1; 875 } 876 break; 877 } 878 } 879 pw_pagemask = m >> TARGET_PAGE_BITS_MIN; 880 update_pagemask(env, pw_pagemask << CP0PM_MASK, &pw_pagemask); 881 pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF); 882 { 883 target_ulong tmp_entryhi = env->CP0_EntryHi; 884 int32_t tmp_pagemask = env->CP0_PageMask; 885 uint64_t tmp_entrylo0 = env->CP0_EntryLo0; 886 uint64_t tmp_entrylo1 = env->CP0_EntryLo1; 887 888 env->CP0_EntryHi = pw_entryhi; 889 env->CP0_PageMask = pw_pagemask; 890 env->CP0_EntryLo0 = pw_entrylo0; 891 env->CP0_EntryLo1 = pw_entrylo1; 892 893 /* 894 * The hardware page walker inserts a page into the TLB in a manner 895 * identical to a TLBWR instruction as executed by the software refill 896 * handler. 897 */ 898 r4k_helper_tlbwr(env); 899 900 env->CP0_EntryHi = tmp_entryhi; 901 env->CP0_PageMask = tmp_pagemask; 902 env->CP0_EntryLo0 = tmp_entrylo0; 903 env->CP0_EntryLo1 = tmp_entrylo1; 904 } 905 return true; 906 } 907 #endif 908 909 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 910 MMUAccessType access_type, int mmu_idx, 911 bool probe, uintptr_t retaddr) 912 { 913 MIPSCPU *cpu = MIPS_CPU(cs); 914 CPUMIPSState *env = &cpu->env; 915 hwaddr physical; 916 int prot; 917 int ret = TLBRET_BADADDR; 918 919 /* data access */ 920 /* XXX: put correct access by using cpu_restore_state() correctly */ 921 ret = get_physical_address(env, &physical, &prot, address, 922 access_type, mmu_idx); 923 switch (ret) { 924 case TLBRET_MATCH: 925 qemu_log_mask(CPU_LOG_MMU, 926 "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx 927 " prot %d\n", __func__, address, physical, prot); 928 break; 929 default: 930 qemu_log_mask(CPU_LOG_MMU, 931 "%s address=%" VADDR_PRIx " ret %d\n", __func__, address, 932 ret); 933 break; 934 } 935 if (ret == TLBRET_MATCH) { 936 tlb_set_page(cs, address & TARGET_PAGE_MASK, 937 physical & TARGET_PAGE_MASK, prot, 938 mmu_idx, TARGET_PAGE_SIZE); 939 return true; 940 } 941 #if !defined(TARGET_MIPS64) 942 if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) { 943 /* 944 * Memory reads during hardware page table walking are performed 945 * as if they were kernel-mode load instructions. 946 */ 947 int mode = (env->hflags & MIPS_HFLAG_KSU); 948 bool ret_walker; 949 env->hflags &= ~MIPS_HFLAG_KSU; 950 ret_walker = page_table_walk_refill(env, address, mmu_idx); 951 env->hflags |= mode; 952 if (ret_walker) { 953 ret = get_physical_address(env, &physical, &prot, address, 954 access_type, mmu_idx); 955 if (ret == TLBRET_MATCH) { 956 tlb_set_page(cs, address & TARGET_PAGE_MASK, 957 physical & TARGET_PAGE_MASK, prot, 958 mmu_idx, TARGET_PAGE_SIZE); 959 return true; 960 } 961 } 962 } 963 #endif 964 if (probe) { 965 return false; 966 } 967 968 raise_mmu_exception(env, address, access_type, ret); 969 do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); 970 } 971 972 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, 973 MMUAccessType access_type, uintptr_t retaddr) 974 { 975 hwaddr physical; 976 int prot; 977 int ret = 0; 978 CPUState *cs = env_cpu(env); 979 980 /* data access */ 981 ret = get_physical_address(env, &physical, &prot, address, access_type, 982 cpu_mmu_index(env, false)); 983 if (ret == TLBRET_MATCH) { 984 return physical; 985 } 986 987 raise_mmu_exception(env, address, access_type, ret); 988 cpu_loop_exit_restore(cs, retaddr); 989 } 990 991 static void set_hflags_for_handler(CPUMIPSState *env) 992 { 993 /* Exception handlers are entered in 32-bit mode. */ 994 env->hflags &= ~(MIPS_HFLAG_M16); 995 /* ...except that microMIPS lets you choose. */ 996 if (env->insn_flags & ASE_MICROMIPS) { 997 env->hflags |= (!!(env->CP0_Config3 & 998 (1 << CP0C3_ISA_ON_EXC)) 999 << MIPS_HFLAG_M16_SHIFT); 1000 } 1001 } 1002 1003 static inline void set_badinstr_registers(CPUMIPSState *env) 1004 { 1005 if (env->insn_flags & ISA_NANOMIPS32) { 1006 if (env->CP0_Config3 & (1 << CP0C3_BI)) { 1007 uint32_t instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16; 1008 if ((instr & 0x10000000) == 0) { 1009 instr |= cpu_lduw_code(env, env->active_tc.PC + 2); 1010 } 1011 env->CP0_BadInstr = instr; 1012 1013 if ((instr & 0xFC000000) == 0x60000000) { 1014 instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16; 1015 env->CP0_BadInstrX = instr; 1016 } 1017 } 1018 return; 1019 } 1020 1021 if (env->hflags & MIPS_HFLAG_M16) { 1022 /* TODO: add BadInstr support for microMIPS */ 1023 return; 1024 } 1025 if (env->CP0_Config3 & (1 << CP0C3_BI)) { 1026 env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC); 1027 } 1028 if ((env->CP0_Config3 & (1 << CP0C3_BP)) && 1029 (env->hflags & MIPS_HFLAG_BMASK)) { 1030 env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4); 1031 } 1032 } 1033 1034 void mips_cpu_do_interrupt(CPUState *cs) 1035 { 1036 MIPSCPU *cpu = MIPS_CPU(cs); 1037 CPUMIPSState *env = &cpu->env; 1038 bool update_badinstr = 0; 1039 target_ulong offset; 1040 int cause = -1; 1041 1042 if (qemu_loglevel_mask(CPU_LOG_INT) 1043 && cs->exception_index != EXCP_EXT_INTERRUPT) { 1044 qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx 1045 " %s exception\n", 1046 __func__, env->active_tc.PC, env->CP0_EPC, 1047 mips_exception_name(cs->exception_index)); 1048 } 1049 if (cs->exception_index == EXCP_EXT_INTERRUPT && 1050 (env->hflags & MIPS_HFLAG_DM)) { 1051 cs->exception_index = EXCP_DINT; 1052 } 1053 offset = 0x180; 1054 switch (cs->exception_index) { 1055 case EXCP_DSS: 1056 env->CP0_Debug |= 1 << CP0DB_DSS; 1057 /* 1058 * Debug single step cannot be raised inside a delay slot and 1059 * resume will always occur on the next instruction 1060 * (but we assume the pc has always been updated during 1061 * code translation). 1062 */ 1063 env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16); 1064 goto enter_debug_mode; 1065 case EXCP_DINT: 1066 env->CP0_Debug |= 1 << CP0DB_DINT; 1067 goto set_DEPC; 1068 case EXCP_DIB: 1069 env->CP0_Debug |= 1 << CP0DB_DIB; 1070 goto set_DEPC; 1071 case EXCP_DBp: 1072 env->CP0_Debug |= 1 << CP0DB_DBp; 1073 /* Setup DExcCode - SDBBP instruction */ 1074 env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 1075 (9 << CP0DB_DEC); 1076 goto set_DEPC; 1077 case EXCP_DDBS: 1078 env->CP0_Debug |= 1 << CP0DB_DDBS; 1079 goto set_DEPC; 1080 case EXCP_DDBL: 1081 env->CP0_Debug |= 1 << CP0DB_DDBL; 1082 set_DEPC: 1083 env->CP0_DEPC = exception_resume_pc(env); 1084 env->hflags &= ~MIPS_HFLAG_BMASK; 1085 enter_debug_mode: 1086 if (env->insn_flags & ISA_MIPS3) { 1087 env->hflags |= MIPS_HFLAG_64; 1088 if (!(env->insn_flags & ISA_MIPS_R6) || 1089 env->CP0_Status & (1 << CP0St_KX)) { 1090 env->hflags &= ~MIPS_HFLAG_AWRAP; 1091 } 1092 } 1093 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0; 1094 env->hflags &= ~(MIPS_HFLAG_KSU); 1095 /* EJTAG probe trap enable is not implemented... */ 1096 if (!(env->CP0_Status & (1 << CP0St_EXL))) { 1097 env->CP0_Cause &= ~(1U << CP0Ca_BD); 1098 } 1099 env->active_tc.PC = env->exception_base + 0x480; 1100 set_hflags_for_handler(env); 1101 break; 1102 case EXCP_RESET: 1103 cpu_reset(CPU(cpu)); 1104 break; 1105 case EXCP_SRESET: 1106 env->CP0_Status |= (1 << CP0St_SR); 1107 memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo)); 1108 goto set_error_EPC; 1109 case EXCP_NMI: 1110 env->CP0_Status |= (1 << CP0St_NMI); 1111 set_error_EPC: 1112 env->CP0_ErrorEPC = exception_resume_pc(env); 1113 env->hflags &= ~MIPS_HFLAG_BMASK; 1114 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); 1115 if (env->insn_flags & ISA_MIPS3) { 1116 env->hflags |= MIPS_HFLAG_64; 1117 if (!(env->insn_flags & ISA_MIPS_R6) || 1118 env->CP0_Status & (1 << CP0St_KX)) { 1119 env->hflags &= ~MIPS_HFLAG_AWRAP; 1120 } 1121 } 1122 env->hflags |= MIPS_HFLAG_CP0; 1123 env->hflags &= ~(MIPS_HFLAG_KSU); 1124 if (!(env->CP0_Status & (1 << CP0St_EXL))) { 1125 env->CP0_Cause &= ~(1U << CP0Ca_BD); 1126 } 1127 env->active_tc.PC = env->exception_base; 1128 set_hflags_for_handler(env); 1129 break; 1130 case EXCP_EXT_INTERRUPT: 1131 cause = 0; 1132 if (env->CP0_Cause & (1 << CP0Ca_IV)) { 1133 uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f; 1134 1135 if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) { 1136 offset = 0x200; 1137 } else { 1138 uint32_t vector = 0; 1139 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP; 1140 1141 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { 1142 /* 1143 * For VEIC mode, the external interrupt controller feeds 1144 * the vector through the CP0Cause IP lines. 1145 */ 1146 vector = pending; 1147 } else { 1148 /* 1149 * Vectored Interrupts 1150 * Mask with Status.IM7-IM0 to get enabled interrupts. 1151 */ 1152 pending &= (env->CP0_Status >> CP0St_IM) & 0xff; 1153 /* Find the highest-priority interrupt. */ 1154 while (pending >>= 1) { 1155 vector++; 1156 } 1157 } 1158 offset = 0x200 + (vector * (spacing << 5)); 1159 } 1160 } 1161 goto set_EPC; 1162 case EXCP_LTLBL: 1163 cause = 1; 1164 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); 1165 goto set_EPC; 1166 case EXCP_TLBL: 1167 cause = 2; 1168 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); 1169 if ((env->error_code & EXCP_TLB_NOMATCH) && 1170 !(env->CP0_Status & (1 << CP0St_EXL))) { 1171 #if defined(TARGET_MIPS64) 1172 int R = env->CP0_BadVAddr >> 62; 1173 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; 1174 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; 1175 1176 if ((R != 0 || UX) && (R != 3 || KX) && 1177 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) { 1178 offset = 0x080; 1179 } else { 1180 #endif 1181 offset = 0x000; 1182 #if defined(TARGET_MIPS64) 1183 } 1184 #endif 1185 } 1186 goto set_EPC; 1187 case EXCP_TLBS: 1188 cause = 3; 1189 update_badinstr = 1; 1190 if ((env->error_code & EXCP_TLB_NOMATCH) && 1191 !(env->CP0_Status & (1 << CP0St_EXL))) { 1192 #if defined(TARGET_MIPS64) 1193 int R = env->CP0_BadVAddr >> 62; 1194 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; 1195 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; 1196 1197 if ((R != 0 || UX) && (R != 3 || KX) && 1198 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) { 1199 offset = 0x080; 1200 } else { 1201 #endif 1202 offset = 0x000; 1203 #if defined(TARGET_MIPS64) 1204 } 1205 #endif 1206 } 1207 goto set_EPC; 1208 case EXCP_AdEL: 1209 cause = 4; 1210 update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); 1211 goto set_EPC; 1212 case EXCP_AdES: 1213 cause = 5; 1214 update_badinstr = 1; 1215 goto set_EPC; 1216 case EXCP_IBE: 1217 cause = 6; 1218 goto set_EPC; 1219 case EXCP_DBE: 1220 cause = 7; 1221 goto set_EPC; 1222 case EXCP_SYSCALL: 1223 cause = 8; 1224 update_badinstr = 1; 1225 goto set_EPC; 1226 case EXCP_BREAK: 1227 cause = 9; 1228 update_badinstr = 1; 1229 goto set_EPC; 1230 case EXCP_RI: 1231 cause = 10; 1232 update_badinstr = 1; 1233 goto set_EPC; 1234 case EXCP_CpU: 1235 cause = 11; 1236 update_badinstr = 1; 1237 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | 1238 (env->error_code << CP0Ca_CE); 1239 goto set_EPC; 1240 case EXCP_OVERFLOW: 1241 cause = 12; 1242 update_badinstr = 1; 1243 goto set_EPC; 1244 case EXCP_TRAP: 1245 cause = 13; 1246 update_badinstr = 1; 1247 goto set_EPC; 1248 case EXCP_MSAFPE: 1249 cause = 14; 1250 update_badinstr = 1; 1251 goto set_EPC; 1252 case EXCP_FPE: 1253 cause = 15; 1254 update_badinstr = 1; 1255 goto set_EPC; 1256 case EXCP_C2E: 1257 cause = 18; 1258 goto set_EPC; 1259 case EXCP_TLBRI: 1260 cause = 19; 1261 update_badinstr = 1; 1262 goto set_EPC; 1263 case EXCP_TLBXI: 1264 cause = 20; 1265 goto set_EPC; 1266 case EXCP_MSADIS: 1267 cause = 21; 1268 update_badinstr = 1; 1269 goto set_EPC; 1270 case EXCP_MDMX: 1271 cause = 22; 1272 goto set_EPC; 1273 case EXCP_DWATCH: 1274 cause = 23; 1275 /* XXX: TODO: manage deferred watch exceptions */ 1276 goto set_EPC; 1277 case EXCP_MCHECK: 1278 cause = 24; 1279 goto set_EPC; 1280 case EXCP_THREAD: 1281 cause = 25; 1282 goto set_EPC; 1283 case EXCP_DSPDIS: 1284 cause = 26; 1285 goto set_EPC; 1286 case EXCP_CACHE: 1287 cause = 30; 1288 offset = 0x100; 1289 set_EPC: 1290 if (!(env->CP0_Status & (1 << CP0St_EXL))) { 1291 env->CP0_EPC = exception_resume_pc(env); 1292 if (update_badinstr) { 1293 set_badinstr_registers(env); 1294 } 1295 if (env->hflags & MIPS_HFLAG_BMASK) { 1296 env->CP0_Cause |= (1U << CP0Ca_BD); 1297 } else { 1298 env->CP0_Cause &= ~(1U << CP0Ca_BD); 1299 } 1300 env->CP0_Status |= (1 << CP0St_EXL); 1301 if (env->insn_flags & ISA_MIPS3) { 1302 env->hflags |= MIPS_HFLAG_64; 1303 if (!(env->insn_flags & ISA_MIPS_R6) || 1304 env->CP0_Status & (1 << CP0St_KX)) { 1305 env->hflags &= ~MIPS_HFLAG_AWRAP; 1306 } 1307 } 1308 env->hflags |= MIPS_HFLAG_CP0; 1309 env->hflags &= ~(MIPS_HFLAG_KSU); 1310 } 1311 env->hflags &= ~MIPS_HFLAG_BMASK; 1312 if (env->CP0_Status & (1 << CP0St_BEV)) { 1313 env->active_tc.PC = env->exception_base + 0x200; 1314 } else if (cause == 30 && !(env->CP0_Config3 & (1 << CP0C3_SC) && 1315 env->CP0_Config5 & (1 << CP0C5_CV))) { 1316 /* Force KSeg1 for cache errors */ 1317 env->active_tc.PC = KSEG1_BASE | (env->CP0_EBase & 0x1FFFF000); 1318 } else { 1319 env->active_tc.PC = env->CP0_EBase & ~0xfff; 1320 } 1321 1322 env->active_tc.PC += offset; 1323 set_hflags_for_handler(env); 1324 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | 1325 (cause << CP0Ca_EC); 1326 break; 1327 default: 1328 abort(); 1329 } 1330 if (qemu_loglevel_mask(CPU_LOG_INT) 1331 && cs->exception_index != EXCP_EXT_INTERRUPT) { 1332 qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" 1333 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", 1334 __func__, env->active_tc.PC, env->CP0_EPC, cause, 1335 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, 1336 env->CP0_DEPC); 1337 } 1338 cs->exception_index = EXCP_NONE; 1339 } 1340 1341 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) 1342 { 1343 CPUState *cs = env_cpu(env); 1344 r4k_tlb_t *tlb; 1345 target_ulong addr; 1346 target_ulong end; 1347 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; 1348 uint32_t MMID = env->CP0_MemoryMapID; 1349 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); 1350 uint32_t tlb_mmid; 1351 target_ulong mask; 1352 1353 MMID = mi ? MMID : (uint32_t) ASID; 1354 1355 tlb = &env->tlb->mmu.r4k.tlb[idx]; 1356 /* 1357 * The qemu TLB is flushed when the ASID/MMID changes, so no need to 1358 * flush these entries again. 1359 */ 1360 tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; 1361 if (tlb->G == 0 && tlb_mmid != MMID) { 1362 return; 1363 } 1364 1365 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { 1366 /* 1367 * For tlbwr, we can shadow the discarded entry into 1368 * a new (fake) TLB entry, as long as the guest can not 1369 * tell that it's there. 1370 */ 1371 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb; 1372 env->tlb->tlb_in_use++; 1373 return; 1374 } 1375 1376 /* 1k pages are not supported. */ 1377 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); 1378 if (tlb->V0) { 1379 addr = tlb->VPN & ~mask; 1380 #if defined(TARGET_MIPS64) 1381 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { 1382 addr |= 0x3FFFFF0000000000ULL; 1383 } 1384 #endif 1385 end = addr | (mask >> 1); 1386 while (addr < end) { 1387 tlb_flush_page(cs, addr); 1388 addr += TARGET_PAGE_SIZE; 1389 } 1390 } 1391 if (tlb->V1) { 1392 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); 1393 #if defined(TARGET_MIPS64) 1394 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { 1395 addr |= 0x3FFFFF0000000000ULL; 1396 } 1397 #endif 1398 end = addr | mask; 1399 while (addr - 1 < end) { 1400 tlb_flush_page(cs, addr); 1401 addr += TARGET_PAGE_SIZE; 1402 } 1403 } 1404 } 1405