1/* 2 * microMIPS translation routines 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * Copyright (c) 2006 Marius Groeger (FPU operations) 6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) 7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) 8 * 9 * SPDX-License-Identifier: LGPL-2.1-or-later 10 */ 11 12/* 13 * microMIPS32/microMIPS64 major opcodes 14 * 15 * 1. MIPS Architecture for Programmers Volume II-B: 16 * The microMIPS32 Instruction Set (Revision 3.05) 17 * 18 * Table 6.2 microMIPS32 Encoding of Major Opcode Field 19 * 20 * 2. MIPS Architecture For Programmers Volume II-A: 21 * The MIPS64 Instruction Set (Revision 3.51) 22 */ 23 24enum { 25 POOL32A = 0x00, 26 POOL16A = 0x01, 27 LBU16 = 0x02, 28 MOVE16 = 0x03, 29 ADDI32 = 0x04, 30 R6_LUI = 0x04, 31 AUI = 0x04, 32 LBU32 = 0x05, 33 SB32 = 0x06, 34 LB32 = 0x07, 35 36 POOL32B = 0x08, 37 POOL16B = 0x09, 38 LHU16 = 0x0a, 39 ANDI16 = 0x0b, 40 ADDIU32 = 0x0c, 41 LHU32 = 0x0d, 42 SH32 = 0x0e, 43 LH32 = 0x0f, 44 45 POOL32I = 0x10, 46 POOL16C = 0x11, 47 LWSP16 = 0x12, 48 POOL16D = 0x13, 49 ORI32 = 0x14, 50 POOL32F = 0x15, 51 POOL32S = 0x16, /* MIPS64 */ 52 DADDIU32 = 0x17, /* MIPS64 */ 53 54 POOL32C = 0x18, 55 LWGP16 = 0x19, 56 LW16 = 0x1a, 57 POOL16E = 0x1b, 58 XORI32 = 0x1c, 59 JALS32 = 0x1d, 60 BOVC = 0x1d, 61 BEQC = 0x1d, 62 BEQZALC = 0x1d, 63 ADDIUPC = 0x1e, 64 PCREL = 0x1e, 65 BNVC = 0x1f, 66 BNEC = 0x1f, 67 BNEZALC = 0x1f, 68 69 R6_BEQZC = 0x20, 70 JIC = 0x20, 71 POOL16F = 0x21, 72 SB16 = 0x22, 73 BEQZ16 = 0x23, 74 BEQZC16 = 0x23, 75 SLTI32 = 0x24, 76 BEQ32 = 0x25, 77 BC = 0x25, 78 SWC132 = 0x26, 79 LWC132 = 0x27, 80 81 /* 0x29 is reserved */ 82 RES_29 = 0x29, 83 R6_BNEZC = 0x28, 84 JIALC = 0x28, 85 SH16 = 0x2a, 86 BNEZ16 = 0x2b, 87 BNEZC16 = 0x2b, 88 SLTIU32 = 0x2c, 89 BNE32 = 0x2d, 90 BALC = 0x2d, 91 SDC132 = 0x2e, 92 LDC132 = 0x2f, 93 94 /* 0x31 is reserved */ 95 RES_31 = 0x31, 96 BLEZALC = 0x30, 97 BGEZALC = 0x30, 98 BGEUC = 0x30, 99 SWSP16 = 0x32, 100 B16 = 0x33, 101 BC16 = 0x33, 102 ANDI32 = 0x34, 103 J32 = 0x35, 104 BGTZC = 0x35, 105 BLTZC = 0x35, 106 BLTC = 0x35, 107 SD32 = 0x36, /* MIPS64 */ 108 LD32 = 0x37, /* MIPS64 */ 109 110 /* 0x39 is reserved */ 111 RES_39 = 0x39, 112 BGTZALC = 0x38, 113 BLTZALC = 0x38, 114 BLTUC = 0x38, 115 SW16 = 0x3a, 116 LI16 = 0x3b, 117 JALX32 = 0x3c, 118 JAL32 = 0x3d, 119 BLEZC = 0x3d, 120 BGEZC = 0x3d, 121 BGEC = 0x3d, 122 SW32 = 0x3e, 123 LW32 = 0x3f 124}; 125 126/* PCREL Instructions perform PC-Relative address calculation. bits 20..16 */ 127enum { 128 ADDIUPC_00 = 0x00, 129 ADDIUPC_01 = 0x01, 130 ADDIUPC_02 = 0x02, 131 ADDIUPC_03 = 0x03, 132 ADDIUPC_04 = 0x04, 133 ADDIUPC_05 = 0x05, 134 ADDIUPC_06 = 0x06, 135 ADDIUPC_07 = 0x07, 136 AUIPC = 0x1e, 137 ALUIPC = 0x1f, 138 LWPC_08 = 0x08, 139 LWPC_09 = 0x09, 140 LWPC_0A = 0x0A, 141 LWPC_0B = 0x0B, 142 LWPC_0C = 0x0C, 143 LWPC_0D = 0x0D, 144 LWPC_0E = 0x0E, 145 LWPC_0F = 0x0F, 146}; 147 148/* POOL32A encoding of minor opcode field */ 149 150enum { 151 /* 152 * These opcodes are distinguished only by bits 9..6; those bits are 153 * what are recorded below. 154 */ 155 SLL32 = 0x0, 156 SRL32 = 0x1, 157 SRA = 0x2, 158 ROTR = 0x3, 159 SELEQZ = 0x5, 160 SELNEZ = 0x6, 161 R6_RDHWR = 0x7, 162 163 SLLV = 0x0, 164 SRLV = 0x1, 165 SRAV = 0x2, 166 ROTRV = 0x3, 167 ADD = 0x4, 168 ADDU32 = 0x5, 169 SUB = 0x6, 170 SUBU32 = 0x7, 171 MUL = 0x8, 172 AND = 0x9, 173 OR32 = 0xa, 174 NOR = 0xb, 175 XOR32 = 0xc, 176 SLT = 0xd, 177 SLTU = 0xe, 178 179 MOVN = 0x0, 180 R6_MUL = 0x0, 181 MOVZ = 0x1, 182 MUH = 0x1, 183 MULU = 0x2, 184 MUHU = 0x3, 185 LWXS = 0x4, 186 R6_DIV = 0x4, 187 MOD = 0x5, 188 R6_DIVU = 0x6, 189 MODU = 0x7, 190 191 /* The following can be distinguished by their lower 6 bits. */ 192 BREAK32 = 0x07, 193 INS = 0x0c, 194 LSA = 0x0f, 195 ALIGN = 0x1f, 196 EXT = 0x2c, 197 POOL32AXF = 0x3c, 198 SIGRIE = 0x3f 199}; 200 201/* POOL32AXF encoding of minor opcode field extension */ 202 203/* 204 * 1. MIPS Architecture for Programmers Volume II-B: 205 * The microMIPS32 Instruction Set (Revision 3.05) 206 * 207 * Table 6.5 POOL32Axf Encoding of Minor Opcode Extension Field 208 * 209 * 2. MIPS Architecture for Programmers VolumeIV-e: 210 * The MIPS DSP Application-Specific Extension 211 * to the microMIPS32 Architecture (Revision 2.34) 212 * 213 * Table 5.5 POOL32Axf Encoding of Minor Opcode Extension Field 214 */ 215 216enum { 217 /* bits 11..6 */ 218 TEQ = 0x00, 219 TGE = 0x08, 220 TGEU = 0x10, 221 TLT = 0x20, 222 TLTU = 0x28, 223 TNE = 0x30, 224 225 MFC0 = 0x03, 226 MTC0 = 0x0b, 227 228 /* begin of microMIPS32 DSP */ 229 230 /* bits 13..12 for 0x01 */ 231 MFHI_ACC = 0x0, 232 MFLO_ACC = 0x1, 233 MTHI_ACC = 0x2, 234 MTLO_ACC = 0x3, 235 236 /* bits 13..12 for 0x2a */ 237 MADD_ACC = 0x0, 238 MADDU_ACC = 0x1, 239 MSUB_ACC = 0x2, 240 MSUBU_ACC = 0x3, 241 242 /* bits 13..12 for 0x32 */ 243 MULT_ACC = 0x0, 244 MULTU_ACC = 0x1, 245 246 /* end of microMIPS32 DSP */ 247 248 /* bits 15..12 for 0x2c */ 249 BITSWAP = 0x0, 250 SEB = 0x2, 251 SEH = 0x3, 252 CLO = 0x4, 253 CLZ = 0x5, 254 RDHWR = 0x6, 255 WSBH = 0x7, 256 MULT = 0x8, 257 MULTU = 0x9, 258 DIV = 0xa, 259 DIVU = 0xb, 260 MADD = 0xc, 261 MADDU = 0xd, 262 MSUB = 0xe, 263 MSUBU = 0xf, 264 265 /* bits 15..12 for 0x34 */ 266 MFC2 = 0x4, 267 MTC2 = 0x5, 268 MFHC2 = 0x8, 269 MTHC2 = 0x9, 270 CFC2 = 0xc, 271 CTC2 = 0xd, 272 273 /* bits 15..12 for 0x3c */ 274 JALR = 0x0, 275 JR = 0x0, /* alias */ 276 JALRC = 0x0, 277 JRC = 0x0, 278 JALR_HB = 0x1, 279 JALRC_HB = 0x1, 280 JALRS = 0x4, 281 JALRS_HB = 0x5, 282 283 /* bits 15..12 for 0x05 */ 284 RDPGPR = 0xe, 285 WRPGPR = 0xf, 286 287 /* bits 15..12 for 0x0d */ 288 TLBP = 0x0, 289 TLBR = 0x1, 290 TLBWI = 0x2, 291 TLBWR = 0x3, 292 TLBINV = 0x4, 293 TLBINVF = 0x5, 294 WAIT = 0x9, 295 IRET = 0xd, 296 DERET = 0xe, 297 ERET = 0xf, 298 299 /* bits 15..12 for 0x15 */ 300 DMT = 0x0, 301 DVPE = 0x1, 302 EMT = 0x2, 303 EVPE = 0x3, 304 305 /* bits 15..12 for 0x1d */ 306 DI = 0x4, 307 EI = 0x5, 308 309 /* bits 15..12 for 0x2d */ 310 SYNC = 0x6, 311 SYSCALL = 0x8, 312 SDBBP = 0xd, 313 314 /* bits 15..12 for 0x35 */ 315 MFHI32 = 0x0, 316 MFLO32 = 0x1, 317 MTHI32 = 0x2, 318 MTLO32 = 0x3, 319}; 320 321/* POOL32B encoding of minor opcode field (bits 15..12) */ 322 323enum { 324 LWC2 = 0x0, 325 LWP = 0x1, 326 LDP = 0x4, 327 LWM32 = 0x5, 328 CACHE = 0x6, 329 LDM = 0x7, 330 SWC2 = 0x8, 331 SWP = 0x9, 332 SDP = 0xc, 333 SWM32 = 0xd, 334 SDM = 0xf 335}; 336 337/* POOL32C encoding of minor opcode field (bits 15..12) */ 338 339enum { 340 LWL = 0x0, 341 SWL = 0x8, 342 LWR = 0x1, 343 SWR = 0x9, 344 PREF = 0x2, 345 ST_EVA = 0xa, 346 LL = 0x3, 347 SC = 0xb, 348 LDL = 0x4, 349 SDL = 0xc, 350 LDR = 0x5, 351 SDR = 0xd, 352 LD_EVA = 0x6, 353 LWU = 0xe, 354 LLD = 0x7, 355 SCD = 0xf 356}; 357 358/* POOL32C LD-EVA encoding of minor opcode field (bits 11..9) */ 359 360enum { 361 LBUE = 0x0, 362 LHUE = 0x1, 363 LWLE = 0x2, 364 LWRE = 0x3, 365 LBE = 0x4, 366 LHE = 0x5, 367 LLE = 0x6, 368 LWE = 0x7, 369}; 370 371/* POOL32C ST-EVA encoding of minor opcode field (bits 11..9) */ 372 373enum { 374 SWLE = 0x0, 375 SWRE = 0x1, 376 PREFE = 0x2, 377 CACHEE = 0x3, 378 SBE = 0x4, 379 SHE = 0x5, 380 SCE = 0x6, 381 SWE = 0x7, 382}; 383 384/* POOL32F encoding of minor opcode field (bits 5..0) */ 385 386enum { 387 /* These are the bit 7..6 values */ 388 ADD_FMT = 0x0, 389 390 SUB_FMT = 0x1, 391 392 MUL_FMT = 0x2, 393 394 DIV_FMT = 0x3, 395 396 /* These are the bit 8..6 values */ 397 MOVN_FMT = 0x0, 398 RSQRT2_FMT = 0x0, 399 MOVF_FMT = 0x0, 400 RINT_FMT = 0x0, 401 SELNEZ_FMT = 0x0, 402 403 MOVZ_FMT = 0x1, 404 LWXC1 = 0x1, 405 MOVT_FMT = 0x1, 406 CLASS_FMT = 0x1, 407 SELEQZ_FMT = 0x1, 408 409 PLL_PS = 0x2, 410 SWXC1 = 0x2, 411 SEL_FMT = 0x2, 412 413 PLU_PS = 0x3, 414 LDXC1 = 0x3, 415 416 MOVN_FMT_04 = 0x4, 417 PUL_PS = 0x4, 418 SDXC1 = 0x4, 419 RECIP2_FMT = 0x4, 420 421 MOVZ_FMT_05 = 0x05, 422 PUU_PS = 0x5, 423 LUXC1 = 0x5, 424 425 CVT_PS_S = 0x6, 426 SUXC1 = 0x6, 427 ADDR_PS = 0x6, 428 PREFX = 0x6, 429 MADDF_FMT = 0x6, 430 431 MULR_PS = 0x7, 432 MSUBF_FMT = 0x7, 433 434 MADD_S = 0x01, 435 MADD_D = 0x09, 436 MADD_PS = 0x11, 437 ALNV_PS = 0x19, 438 MSUB_S = 0x21, 439 MSUB_D = 0x29, 440 MSUB_PS = 0x31, 441 442 NMADD_S = 0x02, 443 NMADD_D = 0x0a, 444 NMADD_PS = 0x12, 445 NMSUB_S = 0x22, 446 NMSUB_D = 0x2a, 447 NMSUB_PS = 0x32, 448 449 MIN_FMT = 0x3, 450 MAX_FMT = 0xb, 451 MINA_FMT = 0x23, 452 MAXA_FMT = 0x2b, 453 POOL32FXF = 0x3b, 454 455 CABS_COND_FMT = 0x1c, /* MIPS3D */ 456 C_COND_FMT = 0x3c, 457 458 CMP_CONDN_S = 0x5, 459 CMP_CONDN_D = 0x15 460}; 461 462/* POOL32Fxf encoding of minor opcode extension field */ 463 464enum { 465 CVT_L = 0x04, 466 RSQRT_FMT = 0x08, 467 FLOOR_L = 0x0c, 468 CVT_PW_PS = 0x1c, 469 CVT_W = 0x24, 470 SQRT_FMT = 0x28, 471 FLOOR_W = 0x2c, 472 CVT_PS_PW = 0x3c, 473 CFC1 = 0x40, 474 RECIP_FMT = 0x48, 475 CEIL_L = 0x4c, 476 CTC1 = 0x60, 477 CEIL_W = 0x6c, 478 MFC1 = 0x80, 479 CVT_S_PL = 0x84, 480 TRUNC_L = 0x8c, 481 MTC1 = 0xa0, 482 CVT_S_PU = 0xa4, 483 TRUNC_W = 0xac, 484 MFHC1 = 0xc0, 485 ROUND_L = 0xcc, 486 MTHC1 = 0xe0, 487 ROUND_W = 0xec, 488 489 MOV_FMT = 0x01, 490 MOVF = 0x05, 491 ABS_FMT = 0x0d, 492 RSQRT1_FMT = 0x1d, 493 MOVT = 0x25, 494 NEG_FMT = 0x2d, 495 CVT_D = 0x4d, 496 RECIP1_FMT = 0x5d, 497 CVT_S = 0x6d 498}; 499 500/* POOL32I encoding of minor opcode field (bits 25..21) */ 501 502enum { 503 BLTZ = 0x00, 504 BLTZAL = 0x01, 505 BGEZ = 0x02, 506 BGEZAL = 0x03, 507 BLEZ = 0x04, 508 BNEZC = 0x05, 509 BGTZ = 0x06, 510 BEQZC = 0x07, 511 TLTI = 0x08, 512 BC1EQZC = 0x08, 513 TGEI = 0x09, 514 BC1NEZC = 0x09, 515 TLTIU = 0x0a, 516 BC2EQZC = 0x0a, 517 TGEIU = 0x0b, 518 BC2NEZC = 0x0a, 519 TNEI = 0x0c, 520 R6_SYNCI = 0x0c, 521 LUI = 0x0d, 522 TEQI = 0x0e, 523 SYNCI = 0x10, 524 BLTZALS = 0x11, 525 BGEZALS = 0x13, 526 BC2F = 0x14, 527 BC2T = 0x15, 528 /* These overlap and are distinguished by bit16 of the instruction */ 529 BC1F = 0x1c, 530 BC1T = 0x1d, 531 BC1ANY2F = 0x1c, 532 BC1ANY2T = 0x1d, 533 BC1ANY4F = 0x1e, 534 BC1ANY4T = 0x1f 535}; 536 537/* POOL16A encoding of minor opcode field */ 538 539enum { 540 ADDU16 = 0x0, 541 SUBU16 = 0x1 542}; 543 544/* POOL16B encoding of minor opcode field */ 545 546enum { 547 SLL16 = 0x0, 548 SRL16 = 0x1 549}; 550 551/* POOL16C encoding of minor opcode field */ 552 553enum { 554 NOT16 = 0x00, 555 XOR16 = 0x04, 556 AND16 = 0x08, 557 OR16 = 0x0c, 558 LWM16 = 0x10, 559 SWM16 = 0x14, 560 JR16 = 0x18, 561 JRC16 = 0x1a, 562 JALR16 = 0x1c, 563 JALR16S = 0x1e, 564 MFHI16 = 0x20, 565 MFLO16 = 0x24, 566 BREAK16 = 0x28, 567 SDBBP16 = 0x2c, 568 JRADDIUSP = 0x30 569}; 570 571/* R6 POOL16C encoding of minor opcode field (bits 0..5) */ 572 573enum { 574 R6_NOT16 = 0x00, 575 R6_AND16 = 0x01, 576 R6_LWM16 = 0x02, 577 R6_JRC16 = 0x03, 578 MOVEP = 0x04, 579 MOVEP_05 = 0x05, 580 MOVEP_06 = 0x06, 581 MOVEP_07 = 0x07, 582 R6_XOR16 = 0x08, 583 R6_OR16 = 0x09, 584 R6_SWM16 = 0x0a, 585 JALRC16 = 0x0b, 586 MOVEP_0C = 0x0c, 587 MOVEP_0D = 0x0d, 588 MOVEP_0E = 0x0e, 589 MOVEP_0F = 0x0f, 590 JRCADDIUSP = 0x13, 591 R6_BREAK16 = 0x1b, 592 R6_SDBBP16 = 0x3b 593}; 594 595/* POOL16D encoding of minor opcode field */ 596 597enum { 598 ADDIUS5 = 0x0, 599 ADDIUSP = 0x1 600}; 601 602/* POOL16E encoding of minor opcode field */ 603 604enum { 605 ADDIUR2 = 0x0, 606 ADDIUR1SP = 0x1 607}; 608 609static int mmreg(int r) 610{ 611 static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; 612 613 return map[r]; 614} 615 616/* Used for 16-bit store instructions. */ 617static int mmreg2(int r) 618{ 619 static const int map[] = { 0, 17, 2, 3, 4, 5, 6, 7 }; 620 621 return map[r]; 622} 623 624#define uMIPS_RD(op) ((op >> 7) & 0x7) 625#define uMIPS_RS(op) ((op >> 4) & 0x7) 626#define uMIPS_RS2(op) uMIPS_RS(op) 627#define uMIPS_RS1(op) ((op >> 1) & 0x7) 628#define uMIPS_RD5(op) ((op >> 5) & 0x1f) 629#define uMIPS_RS5(op) (op & 0x1f) 630 631/* Signed immediate */ 632#define SIMM(op, start, width) \ 633 ((int32_t)(((op >> start) & ((~0U) >> (32 - width))) \ 634 << (32 - width)) \ 635 >> (32 - width)) 636/* Zero-extended immediate */ 637#define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32 - width))) 638 639static void gen_addiur1sp(DisasContext *ctx) 640{ 641 int rd = mmreg(uMIPS_RD(ctx->opcode)); 642 643 gen_arith_imm(ctx, OPC_ADDIU, rd, 29, ((ctx->opcode >> 1) & 0x3f) << 2); 644} 645 646static void gen_addiur2(DisasContext *ctx) 647{ 648 static const int decoded_imm[] = { 1, 4, 8, 12, 16, 20, 24, -1 }; 649 int rd = mmreg(uMIPS_RD(ctx->opcode)); 650 int rs = mmreg(uMIPS_RS(ctx->opcode)); 651 652 gen_arith_imm(ctx, OPC_ADDIU, rd, rs, decoded_imm[ZIMM(ctx->opcode, 1, 3)]); 653} 654 655static void gen_addiusp(DisasContext *ctx) 656{ 657 int encoded = ZIMM(ctx->opcode, 1, 9); 658 int decoded; 659 660 if (encoded <= 1) { 661 decoded = 256 + encoded; 662 } else if (encoded <= 255) { 663 decoded = encoded; 664 } else if (encoded <= 509) { 665 decoded = encoded - 512; 666 } else { 667 decoded = encoded - 768; 668 } 669 670 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, decoded << 2); 671} 672 673static void gen_addius5(DisasContext *ctx) 674{ 675 int imm = SIMM(ctx->opcode, 1, 4); 676 int rd = (ctx->opcode >> 5) & 0x1f; 677 678 gen_arith_imm(ctx, OPC_ADDIU, rd, rd, imm); 679} 680 681static void gen_andi16(DisasContext *ctx) 682{ 683 static const int decoded_imm[] = { 128, 1, 2, 3, 4, 7, 8, 15, 16, 684 31, 32, 63, 64, 255, 32768, 65535 }; 685 int rd = mmreg(uMIPS_RD(ctx->opcode)); 686 int rs = mmreg(uMIPS_RS(ctx->opcode)); 687 int encoded = ZIMM(ctx->opcode, 0, 4); 688 689 gen_logic_imm(ctx, OPC_ANDI, rd, rs, decoded_imm[encoded]); 690} 691 692static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist, 693 int base, int16_t offset) 694{ 695 TCGv t0, t1; 696 TCGv_i32 t2; 697 698 if (ctx->hflags & MIPS_HFLAG_BMASK) { 699 gen_reserved_instruction(ctx); 700 return; 701 } 702 703 t0 = tcg_temp_new(); 704 705 gen_base_offset_addr(ctx, t0, base, offset); 706 707 t1 = tcg_constant_tl(reglist); 708 t2 = tcg_constant_i32(ctx->mem_idx); 709 710 save_cpu_state(ctx, 1); 711 switch (opc) { 712 case LWM32: 713 gen_helper_lwm(cpu_env, t0, t1, t2); 714 break; 715 case SWM32: 716 gen_helper_swm(cpu_env, t0, t1, t2); 717 break; 718#ifdef TARGET_MIPS64 719 case LDM: 720 gen_helper_ldm(cpu_env, t0, t1, t2); 721 break; 722 case SDM: 723 gen_helper_sdm(cpu_env, t0, t1, t2); 724 break; 725#endif 726 } 727} 728 729 730static void gen_pool16c_insn(DisasContext *ctx) 731{ 732 int rd = mmreg((ctx->opcode >> 3) & 0x7); 733 int rs = mmreg(ctx->opcode & 0x7); 734 735 switch (((ctx->opcode) >> 4) & 0x3f) { 736 case NOT16 + 0: 737 case NOT16 + 1: 738 case NOT16 + 2: 739 case NOT16 + 3: 740 gen_logic(ctx, OPC_NOR, rd, rs, 0); 741 break; 742 case XOR16 + 0: 743 case XOR16 + 1: 744 case XOR16 + 2: 745 case XOR16 + 3: 746 gen_logic(ctx, OPC_XOR, rd, rd, rs); 747 break; 748 case AND16 + 0: 749 case AND16 + 1: 750 case AND16 + 2: 751 case AND16 + 3: 752 gen_logic(ctx, OPC_AND, rd, rd, rs); 753 break; 754 case OR16 + 0: 755 case OR16 + 1: 756 case OR16 + 2: 757 case OR16 + 3: 758 gen_logic(ctx, OPC_OR, rd, rd, rs); 759 break; 760 case LWM16 + 0: 761 case LWM16 + 1: 762 case LWM16 + 2: 763 case LWM16 + 3: 764 { 765 static const int lwm_convert[] = { 0x11, 0x12, 0x13, 0x14 }; 766 int offset = ZIMM(ctx->opcode, 0, 4); 767 768 gen_ldst_multiple(ctx, LWM32, lwm_convert[(ctx->opcode >> 4) & 0x3], 769 29, offset << 2); 770 } 771 break; 772 case SWM16 + 0: 773 case SWM16 + 1: 774 case SWM16 + 2: 775 case SWM16 + 3: 776 { 777 static const int swm_convert[] = { 0x11, 0x12, 0x13, 0x14 }; 778 int offset = ZIMM(ctx->opcode, 0, 4); 779 780 gen_ldst_multiple(ctx, SWM32, swm_convert[(ctx->opcode >> 4) & 0x3], 781 29, offset << 2); 782 } 783 break; 784 case JR16 + 0: 785 case JR16 + 1: 786 { 787 int reg = ctx->opcode & 0x1f; 788 789 gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0, 4); 790 } 791 break; 792 case JRC16 + 0: 793 case JRC16 + 1: 794 { 795 int reg = ctx->opcode & 0x1f; 796 gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0, 0); 797 /* 798 * Let normal delay slot handling in our caller take us 799 * to the branch target. 800 */ 801 } 802 break; 803 case JALR16 + 0: 804 case JALR16 + 1: 805 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 4); 806 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 807 break; 808 case JALR16S + 0: 809 case JALR16S + 1: 810 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 2); 811 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 812 break; 813 case MFHI16 + 0: 814 case MFHI16 + 1: 815 gen_HILO(ctx, OPC_MFHI, 0, uMIPS_RS5(ctx->opcode)); 816 break; 817 case MFLO16 + 0: 818 case MFLO16 + 1: 819 gen_HILO(ctx, OPC_MFLO, 0, uMIPS_RS5(ctx->opcode)); 820 break; 821 case BREAK16: 822 generate_exception_break(ctx, extract32(ctx->opcode, 0, 4)); 823 break; 824 case SDBBP16: 825 if (is_uhi(ctx, extract32(ctx->opcode, 0, 4))) { 826 ctx->base.is_jmp = DISAS_SEMIHOST; 827 } else { 828 /* 829 * XXX: not clear which exception should be raised 830 * when in debug mode... 831 */ 832 check_insn(ctx, ISA_MIPS_R1); 833 generate_exception_end(ctx, EXCP_DBp); 834 } 835 break; 836 case JRADDIUSP + 0: 837 case JRADDIUSP + 1: 838 { 839 int imm = ZIMM(ctx->opcode, 0, 5); 840 gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0); 841 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2); 842 /* 843 * Let normal delay slot handling in our caller take us 844 * to the branch target. 845 */ 846 } 847 break; 848 default: 849 gen_reserved_instruction(ctx); 850 break; 851 } 852} 853 854static inline void gen_movep(DisasContext *ctx, int enc_dest, int enc_rt, 855 int enc_rs) 856{ 857 int rd, re; 858 static const int rd_enc[] = { 5, 5, 6, 4, 4, 4, 4, 4 }; 859 static const int re_enc[] = { 6, 7, 7, 21, 22, 5, 6, 7 }; 860 static const int rs_rt_enc[] = { 0, 17, 2, 3, 16, 18, 19, 20 }; 861 862 rd = rd_enc[enc_dest]; 863 re = re_enc[enc_dest]; 864 gen_load_gpr(cpu_gpr[rd], rs_rt_enc[enc_rs]); 865 gen_load_gpr(cpu_gpr[re], rs_rt_enc[enc_rt]); 866} 867 868static void gen_pool16c_r6_insn(DisasContext *ctx) 869{ 870 int rt = mmreg((ctx->opcode >> 7) & 0x7); 871 int rs = mmreg((ctx->opcode >> 4) & 0x7); 872 873 switch (ctx->opcode & 0xf) { 874 case R6_NOT16: 875 gen_logic(ctx, OPC_NOR, rt, rs, 0); 876 break; 877 case R6_AND16: 878 gen_logic(ctx, OPC_AND, rt, rt, rs); 879 break; 880 case R6_LWM16: 881 { 882 int lwm_converted = 0x11 + extract32(ctx->opcode, 8, 2); 883 int offset = extract32(ctx->opcode, 4, 4); 884 gen_ldst_multiple(ctx, LWM32, lwm_converted, 29, offset << 2); 885 } 886 break; 887 case R6_JRC16: /* JRCADDIUSP */ 888 if ((ctx->opcode >> 4) & 1) { 889 /* JRCADDIUSP */ 890 int imm = extract32(ctx->opcode, 5, 5); 891 gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0); 892 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2); 893 } else { 894 /* JRC16 */ 895 rs = extract32(ctx->opcode, 5, 5); 896 gen_compute_branch(ctx, OPC_JR, 2, rs, 0, 0, 0); 897 } 898 break; 899 case MOVEP: 900 case MOVEP_05: 901 case MOVEP_06: 902 case MOVEP_07: 903 case MOVEP_0C: 904 case MOVEP_0D: 905 case MOVEP_0E: 906 case MOVEP_0F: 907 { 908 int enc_dest = uMIPS_RD(ctx->opcode); 909 int enc_rt = uMIPS_RS2(ctx->opcode); 910 int enc_rs = (ctx->opcode & 3) | ((ctx->opcode >> 1) & 4); 911 gen_movep(ctx, enc_dest, enc_rt, enc_rs); 912 } 913 break; 914 case R6_XOR16: 915 gen_logic(ctx, OPC_XOR, rt, rt, rs); 916 break; 917 case R6_OR16: 918 gen_logic(ctx, OPC_OR, rt, rt, rs); 919 break; 920 case R6_SWM16: 921 { 922 int swm_converted = 0x11 + extract32(ctx->opcode, 8, 2); 923 int offset = extract32(ctx->opcode, 4, 4); 924 gen_ldst_multiple(ctx, SWM32, swm_converted, 29, offset << 2); 925 } 926 break; 927 case JALRC16: /* BREAK16, SDBBP16 */ 928 switch (ctx->opcode & 0x3f) { 929 case JALRC16: 930 case JALRC16 + 0x20: 931 /* JALRC16 */ 932 gen_compute_branch(ctx, OPC_JALR, 2, (ctx->opcode >> 5) & 0x1f, 933 31, 0, 0); 934 break; 935 case R6_BREAK16: 936 /* BREAK16 */ 937 generate_exception_break(ctx, extract32(ctx->opcode, 6, 4)); 938 break; 939 case R6_SDBBP16: 940 /* SDBBP16 */ 941 if (is_uhi(ctx, extract32(ctx->opcode, 6, 4))) { 942 ctx->base.is_jmp = DISAS_SEMIHOST; 943 } else { 944 if (ctx->hflags & MIPS_HFLAG_SBRI) { 945 generate_exception(ctx, EXCP_RI); 946 } else { 947 generate_exception(ctx, EXCP_DBp); 948 } 949 } 950 break; 951 } 952 break; 953 default: 954 generate_exception(ctx, EXCP_RI); 955 break; 956 } 957} 958 959static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, 960 int base, int16_t offset) 961{ 962 TCGv t0, t1; 963 964 if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31) { 965 gen_reserved_instruction(ctx); 966 return; 967 } 968 969 t0 = tcg_temp_new(); 970 t1 = tcg_temp_new(); 971 972 gen_base_offset_addr(ctx, t0, base, offset); 973 974 switch (opc) { 975 case LWP: 976 if (rd == base) { 977 gen_reserved_instruction(ctx); 978 return; 979 } 980 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); 981 gen_store_gpr(t1, rd); 982 tcg_gen_movi_tl(t1, 4); 983 gen_op_addr_add(ctx, t0, t0, t1); 984 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); 985 gen_store_gpr(t1, rd + 1); 986 break; 987 case SWP: 988 gen_load_gpr(t1, rd); 989 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); 990 tcg_gen_movi_tl(t1, 4); 991 gen_op_addr_add(ctx, t0, t0, t1); 992 gen_load_gpr(t1, rd + 1); 993 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); 994 break; 995#ifdef TARGET_MIPS64 996 case LDP: 997 if (rd == base) { 998 gen_reserved_instruction(ctx); 999 return; 1000 } 1001 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ); 1002 gen_store_gpr(t1, rd); 1003 tcg_gen_movi_tl(t1, 8); 1004 gen_op_addr_add(ctx, t0, t0, t1); 1005 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ); 1006 gen_store_gpr(t1, rd + 1); 1007 break; 1008 case SDP: 1009 gen_load_gpr(t1, rd); 1010 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ); 1011 tcg_gen_movi_tl(t1, 8); 1012 gen_op_addr_add(ctx, t0, t0, t1); 1013 gen_load_gpr(t1, rd + 1); 1014 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ); 1015 break; 1016#endif 1017 } 1018} 1019 1020static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) 1021{ 1022 int extension = (ctx->opcode >> 6) & 0x3f; 1023 int minor = (ctx->opcode >> 12) & 0xf; 1024 uint32_t mips32_op; 1025 1026 switch (extension) { 1027 case TEQ: 1028 mips32_op = OPC_TEQ; 1029 goto do_trap; 1030 case TGE: 1031 mips32_op = OPC_TGE; 1032 goto do_trap; 1033 case TGEU: 1034 mips32_op = OPC_TGEU; 1035 goto do_trap; 1036 case TLT: 1037 mips32_op = OPC_TLT; 1038 goto do_trap; 1039 case TLTU: 1040 mips32_op = OPC_TLTU; 1041 goto do_trap; 1042 case TNE: 1043 mips32_op = OPC_TNE; 1044 do_trap: 1045 gen_trap(ctx, mips32_op, rs, rt, -1, extract32(ctx->opcode, 12, 4)); 1046 break; 1047#ifndef CONFIG_USER_ONLY 1048 case MFC0: 1049 case MFC0 + 32: 1050 check_cp0_enabled(ctx); 1051 if (rt == 0) { 1052 /* Treat as NOP. */ 1053 break; 1054 } 1055 gen_mfc0(ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7); 1056 break; 1057 case MTC0: 1058 case MTC0 + 32: 1059 check_cp0_enabled(ctx); 1060 { 1061 TCGv t0 = tcg_temp_new(); 1062 1063 gen_load_gpr(t0, rt); 1064 gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7); 1065 } 1066 break; 1067#endif 1068 case 0x2a: 1069 switch (minor & 3) { 1070 case MADD_ACC: 1071 gen_muldiv(ctx, OPC_MADD, (ctx->opcode >> 14) & 3, rs, rt); 1072 break; 1073 case MADDU_ACC: 1074 gen_muldiv(ctx, OPC_MADDU, (ctx->opcode >> 14) & 3, rs, rt); 1075 break; 1076 case MSUB_ACC: 1077 gen_muldiv(ctx, OPC_MSUB, (ctx->opcode >> 14) & 3, rs, rt); 1078 break; 1079 case MSUBU_ACC: 1080 gen_muldiv(ctx, OPC_MSUBU, (ctx->opcode >> 14) & 3, rs, rt); 1081 break; 1082 default: 1083 goto pool32axf_invalid; 1084 } 1085 break; 1086 case 0x32: 1087 switch (minor & 3) { 1088 case MULT_ACC: 1089 gen_muldiv(ctx, OPC_MULT, (ctx->opcode >> 14) & 3, rs, rt); 1090 break; 1091 case MULTU_ACC: 1092 gen_muldiv(ctx, OPC_MULTU, (ctx->opcode >> 14) & 3, rs, rt); 1093 break; 1094 default: 1095 goto pool32axf_invalid; 1096 } 1097 break; 1098 case 0x2c: 1099 switch (minor) { 1100 case BITSWAP: 1101 check_insn(ctx, ISA_MIPS_R6); 1102 gen_bitswap(ctx, OPC_BITSWAP, rs, rt); 1103 break; 1104 case SEB: 1105 gen_bshfl(ctx, OPC_SEB, rs, rt); 1106 break; 1107 case SEH: 1108 gen_bshfl(ctx, OPC_SEH, rs, rt); 1109 break; 1110 case CLO: 1111 mips32_op = OPC_CLO; 1112 goto do_cl; 1113 case CLZ: 1114 mips32_op = OPC_CLZ; 1115 do_cl: 1116 check_insn(ctx, ISA_MIPS_R1); 1117 gen_cl(ctx, mips32_op, rt, rs); 1118 break; 1119 case RDHWR: 1120 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1121 gen_rdhwr(ctx, rt, rs, 0); 1122 break; 1123 case WSBH: 1124 gen_bshfl(ctx, OPC_WSBH, rs, rt); 1125 break; 1126 case MULT: 1127 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1128 mips32_op = OPC_MULT; 1129 goto do_mul; 1130 case MULTU: 1131 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1132 mips32_op = OPC_MULTU; 1133 goto do_mul; 1134 case DIV: 1135 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1136 mips32_op = OPC_DIV; 1137 goto do_div; 1138 case DIVU: 1139 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1140 mips32_op = OPC_DIVU; 1141 goto do_div; 1142 do_div: 1143 check_insn(ctx, ISA_MIPS_R1); 1144 gen_muldiv(ctx, mips32_op, 0, rs, rt); 1145 break; 1146 case MADD: 1147 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1148 mips32_op = OPC_MADD; 1149 goto do_mul; 1150 case MADDU: 1151 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1152 mips32_op = OPC_MADDU; 1153 goto do_mul; 1154 case MSUB: 1155 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1156 mips32_op = OPC_MSUB; 1157 goto do_mul; 1158 case MSUBU: 1159 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1160 mips32_op = OPC_MSUBU; 1161 do_mul: 1162 check_insn(ctx, ISA_MIPS_R1); 1163 gen_muldiv(ctx, mips32_op, 0, rs, rt); 1164 break; 1165 default: 1166 goto pool32axf_invalid; 1167 } 1168 break; 1169 case 0x34: 1170 switch (minor) { 1171 case MFC2: 1172 case MTC2: 1173 case MFHC2: 1174 case MTHC2: 1175 case CFC2: 1176 case CTC2: 1177 generate_exception_err(ctx, EXCP_CpU, 2); 1178 break; 1179 default: 1180 goto pool32axf_invalid; 1181 } 1182 break; 1183 case 0x3c: 1184 switch (minor) { 1185 case JALR: /* JALRC */ 1186 case JALR_HB: /* JALRC_HB */ 1187 if (ctx->insn_flags & ISA_MIPS_R6) { 1188 /* JALRC, JALRC_HB */ 1189 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0); 1190 } else { 1191 /* JALR, JALR_HB */ 1192 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 4); 1193 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 1194 } 1195 break; 1196 case JALRS: 1197 case JALRS_HB: 1198 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1199 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2); 1200 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 1201 break; 1202 default: 1203 goto pool32axf_invalid; 1204 } 1205 break; 1206 case 0x05: 1207 switch (minor) { 1208 case RDPGPR: 1209 check_cp0_enabled(ctx); 1210 check_insn(ctx, ISA_MIPS_R2); 1211 gen_load_srsgpr(rs, rt); 1212 break; 1213 case WRPGPR: 1214 check_cp0_enabled(ctx); 1215 check_insn(ctx, ISA_MIPS_R2); 1216 gen_store_srsgpr(rs, rt); 1217 break; 1218 default: 1219 goto pool32axf_invalid; 1220 } 1221 break; 1222#ifndef CONFIG_USER_ONLY 1223 case 0x0d: 1224 switch (minor) { 1225 case TLBP: 1226 mips32_op = OPC_TLBP; 1227 goto do_cp0; 1228 case TLBR: 1229 mips32_op = OPC_TLBR; 1230 goto do_cp0; 1231 case TLBWI: 1232 mips32_op = OPC_TLBWI; 1233 goto do_cp0; 1234 case TLBWR: 1235 mips32_op = OPC_TLBWR; 1236 goto do_cp0; 1237 case TLBINV: 1238 mips32_op = OPC_TLBINV; 1239 goto do_cp0; 1240 case TLBINVF: 1241 mips32_op = OPC_TLBINVF; 1242 goto do_cp0; 1243 case WAIT: 1244 mips32_op = OPC_WAIT; 1245 goto do_cp0; 1246 case DERET: 1247 mips32_op = OPC_DERET; 1248 goto do_cp0; 1249 case ERET: 1250 mips32_op = OPC_ERET; 1251 do_cp0: 1252 gen_cp0(env, ctx, mips32_op, rt, rs); 1253 break; 1254 default: 1255 goto pool32axf_invalid; 1256 } 1257 break; 1258 case 0x1d: 1259 switch (minor) { 1260 case DI: 1261 check_cp0_enabled(ctx); 1262 { 1263 TCGv t0 = tcg_temp_new(); 1264 1265 save_cpu_state(ctx, 1); 1266 gen_helper_di(t0, cpu_env); 1267 gen_store_gpr(t0, rs); 1268 /* 1269 * Stop translation as we may have switched the execution 1270 * mode. 1271 */ 1272 ctx->base.is_jmp = DISAS_STOP; 1273 } 1274 break; 1275 case EI: 1276 check_cp0_enabled(ctx); 1277 { 1278 TCGv t0 = tcg_temp_new(); 1279 1280 save_cpu_state(ctx, 1); 1281 gen_helper_ei(t0, cpu_env); 1282 gen_store_gpr(t0, rs); 1283 /* 1284 * DISAS_STOP isn't sufficient, we need to ensure we break out 1285 * of translated code to check for pending interrupts. 1286 */ 1287 gen_save_pc(ctx->base.pc_next + 4); 1288 ctx->base.is_jmp = DISAS_EXIT; 1289 } 1290 break; 1291 default: 1292 goto pool32axf_invalid; 1293 } 1294 break; 1295#endif 1296 case 0x2d: 1297 switch (minor) { 1298 case SYNC: 1299 gen_sync(extract32(ctx->opcode, 16, 5)); 1300 break; 1301 case SYSCALL: 1302 generate_exception_end(ctx, EXCP_SYSCALL); 1303 break; 1304 case SDBBP: 1305 if (is_uhi(ctx, extract32(ctx->opcode, 16, 10))) { 1306 ctx->base.is_jmp = DISAS_SEMIHOST; 1307 } else { 1308 check_insn(ctx, ISA_MIPS_R1); 1309 if (ctx->hflags & MIPS_HFLAG_SBRI) { 1310 gen_reserved_instruction(ctx); 1311 } else { 1312 generate_exception_end(ctx, EXCP_DBp); 1313 } 1314 } 1315 break; 1316 default: 1317 goto pool32axf_invalid; 1318 } 1319 break; 1320 case 0x01: 1321 switch (minor & 3) { 1322 case MFHI_ACC: 1323 gen_HILO(ctx, OPC_MFHI, minor >> 2, rs); 1324 break; 1325 case MFLO_ACC: 1326 gen_HILO(ctx, OPC_MFLO, minor >> 2, rs); 1327 break; 1328 case MTHI_ACC: 1329 gen_HILO(ctx, OPC_MTHI, minor >> 2, rs); 1330 break; 1331 case MTLO_ACC: 1332 gen_HILO(ctx, OPC_MTLO, minor >> 2, rs); 1333 break; 1334 default: 1335 goto pool32axf_invalid; 1336 } 1337 break; 1338 case 0x35: 1339 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1340 switch (minor) { 1341 case MFHI32: 1342 gen_HILO(ctx, OPC_MFHI, 0, rs); 1343 break; 1344 case MFLO32: 1345 gen_HILO(ctx, OPC_MFLO, 0, rs); 1346 break; 1347 case MTHI32: 1348 gen_HILO(ctx, OPC_MTHI, 0, rs); 1349 break; 1350 case MTLO32: 1351 gen_HILO(ctx, OPC_MTLO, 0, rs); 1352 break; 1353 default: 1354 goto pool32axf_invalid; 1355 } 1356 break; 1357 default: 1358 pool32axf_invalid: 1359 MIPS_INVAL("pool32axf"); 1360 gen_reserved_instruction(ctx); 1361 break; 1362 } 1363} 1364 1365static void gen_pool32fxf(DisasContext *ctx, int rt, int rs) 1366{ 1367 int extension = (ctx->opcode >> 6) & 0x3ff; 1368 uint32_t mips32_op; 1369 1370#define FLOAT_1BIT_FMT(opc, fmt) ((fmt << 8) | opc) 1371#define FLOAT_2BIT_FMT(opc, fmt) ((fmt << 7) | opc) 1372#define COND_FLOAT_MOV(opc, cond) ((cond << 7) | opc) 1373 1374 switch (extension) { 1375 case FLOAT_1BIT_FMT(CFC1, 0): 1376 mips32_op = OPC_CFC1; 1377 goto do_cp1; 1378 case FLOAT_1BIT_FMT(CTC1, 0): 1379 mips32_op = OPC_CTC1; 1380 goto do_cp1; 1381 case FLOAT_1BIT_FMT(MFC1, 0): 1382 mips32_op = OPC_MFC1; 1383 goto do_cp1; 1384 case FLOAT_1BIT_FMT(MTC1, 0): 1385 mips32_op = OPC_MTC1; 1386 goto do_cp1; 1387 case FLOAT_1BIT_FMT(MFHC1, 0): 1388 mips32_op = OPC_MFHC1; 1389 goto do_cp1; 1390 case FLOAT_1BIT_FMT(MTHC1, 0): 1391 mips32_op = OPC_MTHC1; 1392 do_cp1: 1393 gen_cp1(ctx, mips32_op, rt, rs); 1394 break; 1395 1396 /* Reciprocal square root */ 1397 case FLOAT_1BIT_FMT(RSQRT_FMT, FMT_SD_S): 1398 mips32_op = OPC_RSQRT_S; 1399 goto do_unaryfp; 1400 case FLOAT_1BIT_FMT(RSQRT_FMT, FMT_SD_D): 1401 mips32_op = OPC_RSQRT_D; 1402 goto do_unaryfp; 1403 1404 /* Square root */ 1405 case FLOAT_1BIT_FMT(SQRT_FMT, FMT_SD_S): 1406 mips32_op = OPC_SQRT_S; 1407 goto do_unaryfp; 1408 case FLOAT_1BIT_FMT(SQRT_FMT, FMT_SD_D): 1409 mips32_op = OPC_SQRT_D; 1410 goto do_unaryfp; 1411 1412 /* Reciprocal */ 1413 case FLOAT_1BIT_FMT(RECIP_FMT, FMT_SD_S): 1414 mips32_op = OPC_RECIP_S; 1415 goto do_unaryfp; 1416 case FLOAT_1BIT_FMT(RECIP_FMT, FMT_SD_D): 1417 mips32_op = OPC_RECIP_D; 1418 goto do_unaryfp; 1419 1420 /* Floor */ 1421 case FLOAT_1BIT_FMT(FLOOR_L, FMT_SD_S): 1422 mips32_op = OPC_FLOOR_L_S; 1423 goto do_unaryfp; 1424 case FLOAT_1BIT_FMT(FLOOR_L, FMT_SD_D): 1425 mips32_op = OPC_FLOOR_L_D; 1426 goto do_unaryfp; 1427 case FLOAT_1BIT_FMT(FLOOR_W, FMT_SD_S): 1428 mips32_op = OPC_FLOOR_W_S; 1429 goto do_unaryfp; 1430 case FLOAT_1BIT_FMT(FLOOR_W, FMT_SD_D): 1431 mips32_op = OPC_FLOOR_W_D; 1432 goto do_unaryfp; 1433 1434 /* Ceiling */ 1435 case FLOAT_1BIT_FMT(CEIL_L, FMT_SD_S): 1436 mips32_op = OPC_CEIL_L_S; 1437 goto do_unaryfp; 1438 case FLOAT_1BIT_FMT(CEIL_L, FMT_SD_D): 1439 mips32_op = OPC_CEIL_L_D; 1440 goto do_unaryfp; 1441 case FLOAT_1BIT_FMT(CEIL_W, FMT_SD_S): 1442 mips32_op = OPC_CEIL_W_S; 1443 goto do_unaryfp; 1444 case FLOAT_1BIT_FMT(CEIL_W, FMT_SD_D): 1445 mips32_op = OPC_CEIL_W_D; 1446 goto do_unaryfp; 1447 1448 /* Truncation */ 1449 case FLOAT_1BIT_FMT(TRUNC_L, FMT_SD_S): 1450 mips32_op = OPC_TRUNC_L_S; 1451 goto do_unaryfp; 1452 case FLOAT_1BIT_FMT(TRUNC_L, FMT_SD_D): 1453 mips32_op = OPC_TRUNC_L_D; 1454 goto do_unaryfp; 1455 case FLOAT_1BIT_FMT(TRUNC_W, FMT_SD_S): 1456 mips32_op = OPC_TRUNC_W_S; 1457 goto do_unaryfp; 1458 case FLOAT_1BIT_FMT(TRUNC_W, FMT_SD_D): 1459 mips32_op = OPC_TRUNC_W_D; 1460 goto do_unaryfp; 1461 1462 /* Round */ 1463 case FLOAT_1BIT_FMT(ROUND_L, FMT_SD_S): 1464 mips32_op = OPC_ROUND_L_S; 1465 goto do_unaryfp; 1466 case FLOAT_1BIT_FMT(ROUND_L, FMT_SD_D): 1467 mips32_op = OPC_ROUND_L_D; 1468 goto do_unaryfp; 1469 case FLOAT_1BIT_FMT(ROUND_W, FMT_SD_S): 1470 mips32_op = OPC_ROUND_W_S; 1471 goto do_unaryfp; 1472 case FLOAT_1BIT_FMT(ROUND_W, FMT_SD_D): 1473 mips32_op = OPC_ROUND_W_D; 1474 goto do_unaryfp; 1475 1476 /* Integer to floating-point conversion */ 1477 case FLOAT_1BIT_FMT(CVT_L, FMT_SD_S): 1478 mips32_op = OPC_CVT_L_S; 1479 goto do_unaryfp; 1480 case FLOAT_1BIT_FMT(CVT_L, FMT_SD_D): 1481 mips32_op = OPC_CVT_L_D; 1482 goto do_unaryfp; 1483 case FLOAT_1BIT_FMT(CVT_W, FMT_SD_S): 1484 mips32_op = OPC_CVT_W_S; 1485 goto do_unaryfp; 1486 case FLOAT_1BIT_FMT(CVT_W, FMT_SD_D): 1487 mips32_op = OPC_CVT_W_D; 1488 goto do_unaryfp; 1489 1490 /* Paired-foo conversions */ 1491 case FLOAT_1BIT_FMT(CVT_S_PL, 0): 1492 mips32_op = OPC_CVT_S_PL; 1493 goto do_unaryfp; 1494 case FLOAT_1BIT_FMT(CVT_S_PU, 0): 1495 mips32_op = OPC_CVT_S_PU; 1496 goto do_unaryfp; 1497 case FLOAT_1BIT_FMT(CVT_PW_PS, 0): 1498 mips32_op = OPC_CVT_PW_PS; 1499 goto do_unaryfp; 1500 case FLOAT_1BIT_FMT(CVT_PS_PW, 0): 1501 mips32_op = OPC_CVT_PS_PW; 1502 goto do_unaryfp; 1503 1504 /* Floating-point moves */ 1505 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_S): 1506 mips32_op = OPC_MOV_S; 1507 goto do_unaryfp; 1508 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_D): 1509 mips32_op = OPC_MOV_D; 1510 goto do_unaryfp; 1511 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_PS): 1512 mips32_op = OPC_MOV_PS; 1513 goto do_unaryfp; 1514 1515 /* Absolute value */ 1516 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_S): 1517 mips32_op = OPC_ABS_S; 1518 goto do_unaryfp; 1519 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_D): 1520 mips32_op = OPC_ABS_D; 1521 goto do_unaryfp; 1522 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_PS): 1523 mips32_op = OPC_ABS_PS; 1524 goto do_unaryfp; 1525 1526 /* Negation */ 1527 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_S): 1528 mips32_op = OPC_NEG_S; 1529 goto do_unaryfp; 1530 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_D): 1531 mips32_op = OPC_NEG_D; 1532 goto do_unaryfp; 1533 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_PS): 1534 mips32_op = OPC_NEG_PS; 1535 goto do_unaryfp; 1536 1537 /* Reciprocal square root step */ 1538 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_S): 1539 mips32_op = OPC_RSQRT1_S; 1540 goto do_unaryfp; 1541 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_D): 1542 mips32_op = OPC_RSQRT1_D; 1543 goto do_unaryfp; 1544 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_PS): 1545 mips32_op = OPC_RSQRT1_PS; 1546 goto do_unaryfp; 1547 1548 /* Reciprocal step */ 1549 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_S): 1550 mips32_op = OPC_RECIP1_S; 1551 goto do_unaryfp; 1552 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_D): 1553 mips32_op = OPC_RECIP1_S; 1554 goto do_unaryfp; 1555 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_PS): 1556 mips32_op = OPC_RECIP1_PS; 1557 goto do_unaryfp; 1558 1559 /* Conversions from double */ 1560 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_S): 1561 mips32_op = OPC_CVT_D_S; 1562 goto do_unaryfp; 1563 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_W): 1564 mips32_op = OPC_CVT_D_W; 1565 goto do_unaryfp; 1566 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_L): 1567 mips32_op = OPC_CVT_D_L; 1568 goto do_unaryfp; 1569 1570 /* Conversions from single */ 1571 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_D): 1572 mips32_op = OPC_CVT_S_D; 1573 goto do_unaryfp; 1574 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_W): 1575 mips32_op = OPC_CVT_S_W; 1576 goto do_unaryfp; 1577 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_L): 1578 mips32_op = OPC_CVT_S_L; 1579 do_unaryfp: 1580 gen_farith(ctx, mips32_op, -1, rs, rt, 0); 1581 break; 1582 1583 /* Conditional moves on floating-point codes */ 1584 case COND_FLOAT_MOV(MOVT, 0): 1585 case COND_FLOAT_MOV(MOVT, 1): 1586 case COND_FLOAT_MOV(MOVT, 2): 1587 case COND_FLOAT_MOV(MOVT, 3): 1588 case COND_FLOAT_MOV(MOVT, 4): 1589 case COND_FLOAT_MOV(MOVT, 5): 1590 case COND_FLOAT_MOV(MOVT, 6): 1591 case COND_FLOAT_MOV(MOVT, 7): 1592 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1593 gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 1); 1594 break; 1595 case COND_FLOAT_MOV(MOVF, 0): 1596 case COND_FLOAT_MOV(MOVF, 1): 1597 case COND_FLOAT_MOV(MOVF, 2): 1598 case COND_FLOAT_MOV(MOVF, 3): 1599 case COND_FLOAT_MOV(MOVF, 4): 1600 case COND_FLOAT_MOV(MOVF, 5): 1601 case COND_FLOAT_MOV(MOVF, 6): 1602 case COND_FLOAT_MOV(MOVF, 7): 1603 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1604 gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 0); 1605 break; 1606 default: 1607 MIPS_INVAL("pool32fxf"); 1608 gen_reserved_instruction(ctx); 1609 break; 1610 } 1611} 1612 1613static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) 1614{ 1615 int32_t offset; 1616 uint16_t insn; 1617 int rt, rs, rd, rr; 1618 int16_t imm; 1619 uint32_t op, minor, minor2, mips32_op; 1620 uint32_t cond, fmt, cc; 1621 1622 insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); 1623 ctx->opcode = (ctx->opcode << 16) | insn; 1624 1625 rt = (ctx->opcode >> 21) & 0x1f; 1626 rs = (ctx->opcode >> 16) & 0x1f; 1627 rd = (ctx->opcode >> 11) & 0x1f; 1628 rr = (ctx->opcode >> 6) & 0x1f; 1629 imm = (int16_t) ctx->opcode; 1630 1631 op = (ctx->opcode >> 26) & 0x3f; 1632 switch (op) { 1633 case POOL32A: 1634 minor = ctx->opcode & 0x3f; 1635 switch (minor) { 1636 case 0x00: 1637 minor = (ctx->opcode >> 6) & 0xf; 1638 switch (minor) { 1639 case SLL32: 1640 mips32_op = OPC_SLL; 1641 goto do_shifti; 1642 case SRA: 1643 mips32_op = OPC_SRA; 1644 goto do_shifti; 1645 case SRL32: 1646 mips32_op = OPC_SRL; 1647 goto do_shifti; 1648 case ROTR: 1649 mips32_op = OPC_ROTR; 1650 do_shifti: 1651 gen_shift_imm(ctx, mips32_op, rt, rs, rd); 1652 break; 1653 case SELEQZ: 1654 check_insn(ctx, ISA_MIPS_R6); 1655 gen_cond_move(ctx, OPC_SELEQZ, rd, rs, rt); 1656 break; 1657 case SELNEZ: 1658 check_insn(ctx, ISA_MIPS_R6); 1659 gen_cond_move(ctx, OPC_SELNEZ, rd, rs, rt); 1660 break; 1661 case R6_RDHWR: 1662 check_insn(ctx, ISA_MIPS_R6); 1663 gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3)); 1664 break; 1665 default: 1666 goto pool32a_invalid; 1667 } 1668 break; 1669 case 0x10: 1670 minor = (ctx->opcode >> 6) & 0xf; 1671 switch (minor) { 1672 /* Arithmetic */ 1673 case ADD: 1674 mips32_op = OPC_ADD; 1675 goto do_arith; 1676 case ADDU32: 1677 mips32_op = OPC_ADDU; 1678 goto do_arith; 1679 case SUB: 1680 mips32_op = OPC_SUB; 1681 goto do_arith; 1682 case SUBU32: 1683 mips32_op = OPC_SUBU; 1684 goto do_arith; 1685 case MUL: 1686 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1687 mips32_op = OPC_MUL; 1688 do_arith: 1689 gen_arith(ctx, mips32_op, rd, rs, rt); 1690 break; 1691 /* Shifts */ 1692 case SLLV: 1693 mips32_op = OPC_SLLV; 1694 goto do_shift; 1695 case SRLV: 1696 mips32_op = OPC_SRLV; 1697 goto do_shift; 1698 case SRAV: 1699 mips32_op = OPC_SRAV; 1700 goto do_shift; 1701 case ROTRV: 1702 mips32_op = OPC_ROTRV; 1703 do_shift: 1704 gen_shift(ctx, mips32_op, rd, rs, rt); 1705 break; 1706 /* Logical operations */ 1707 case AND: 1708 mips32_op = OPC_AND; 1709 goto do_logic; 1710 case OR32: 1711 mips32_op = OPC_OR; 1712 goto do_logic; 1713 case NOR: 1714 mips32_op = OPC_NOR; 1715 goto do_logic; 1716 case XOR32: 1717 mips32_op = OPC_XOR; 1718 do_logic: 1719 gen_logic(ctx, mips32_op, rd, rs, rt); 1720 break; 1721 /* Set less than */ 1722 case SLT: 1723 mips32_op = OPC_SLT; 1724 goto do_slt; 1725 case SLTU: 1726 mips32_op = OPC_SLTU; 1727 do_slt: 1728 gen_slt(ctx, mips32_op, rd, rs, rt); 1729 break; 1730 default: 1731 goto pool32a_invalid; 1732 } 1733 break; 1734 case 0x18: 1735 minor = (ctx->opcode >> 6) & 0xf; 1736 switch (minor) { 1737 /* Conditional moves */ 1738 case MOVN: /* MUL */ 1739 if (ctx->insn_flags & ISA_MIPS_R6) { 1740 /* MUL */ 1741 gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt); 1742 } else { 1743 /* MOVN */ 1744 gen_cond_move(ctx, OPC_MOVN, rd, rs, rt); 1745 } 1746 break; 1747 case MOVZ: /* MUH */ 1748 if (ctx->insn_flags & ISA_MIPS_R6) { 1749 /* MUH */ 1750 gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt); 1751 } else { 1752 /* MOVZ */ 1753 gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt); 1754 } 1755 break; 1756 case MULU: 1757 check_insn(ctx, ISA_MIPS_R6); 1758 gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt); 1759 break; 1760 case MUHU: 1761 check_insn(ctx, ISA_MIPS_R6); 1762 gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt); 1763 break; 1764 case LWXS: /* DIV */ 1765 if (ctx->insn_flags & ISA_MIPS_R6) { 1766 /* DIV */ 1767 gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt); 1768 } else { 1769 /* LWXS */ 1770 gen_ldxs(ctx, rs, rt, rd); 1771 } 1772 break; 1773 case MOD: 1774 check_insn(ctx, ISA_MIPS_R6); 1775 gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt); 1776 break; 1777 case R6_DIVU: 1778 check_insn(ctx, ISA_MIPS_R6); 1779 gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt); 1780 break; 1781 case MODU: 1782 check_insn(ctx, ISA_MIPS_R6); 1783 gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt); 1784 break; 1785 default: 1786 goto pool32a_invalid; 1787 } 1788 break; 1789 case INS: 1790 gen_bitops(ctx, OPC_INS, rt, rs, rr, rd); 1791 return; 1792 case LSA: 1793 check_insn(ctx, ISA_MIPS_R6); 1794 gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2)); 1795 break; 1796 case ALIGN: 1797 check_insn(ctx, ISA_MIPS_R6); 1798 gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2)); 1799 break; 1800 case EXT: 1801 gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd); 1802 return; 1803 case POOL32AXF: 1804 gen_pool32axf(env, ctx, rt, rs); 1805 break; 1806 case BREAK32: 1807 generate_exception_break(ctx, extract32(ctx->opcode, 6, 20)); 1808 break; 1809 case SIGRIE: 1810 check_insn(ctx, ISA_MIPS_R6); 1811 gen_reserved_instruction(ctx); 1812 break; 1813 default: 1814 pool32a_invalid: 1815 MIPS_INVAL("pool32a"); 1816 gen_reserved_instruction(ctx); 1817 break; 1818 } 1819 break; 1820 case POOL32B: 1821 minor = (ctx->opcode >> 12) & 0xf; 1822 switch (minor) { 1823 case CACHE: 1824 check_cp0_enabled(ctx); 1825 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 1826 gen_cache_operation(ctx, rt, rs, imm); 1827 } 1828 break; 1829 case LWC2: 1830 case SWC2: 1831 /* COP2: Not implemented. */ 1832 generate_exception_err(ctx, EXCP_CpU, 2); 1833 break; 1834#ifdef TARGET_MIPS64 1835 case LDP: 1836 case SDP: 1837 check_insn(ctx, ISA_MIPS3); 1838 check_mips_64(ctx); 1839#endif 1840 /* fall through */ 1841 case LWP: 1842 case SWP: 1843 gen_ldst_pair(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12)); 1844 break; 1845#ifdef TARGET_MIPS64 1846 case LDM: 1847 case SDM: 1848 check_insn(ctx, ISA_MIPS3); 1849 check_mips_64(ctx); 1850#endif 1851 /* fall through */ 1852 case LWM32: 1853 case SWM32: 1854 gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12)); 1855 break; 1856 default: 1857 MIPS_INVAL("pool32b"); 1858 gen_reserved_instruction(ctx); 1859 break; 1860 } 1861 break; 1862 case POOL32F: 1863 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { 1864 minor = ctx->opcode & 0x3f; 1865 check_cp1_enabled(ctx); 1866 switch (minor) { 1867 case ALNV_PS: 1868 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1869 mips32_op = OPC_ALNV_PS; 1870 goto do_madd; 1871 case MADD_S: 1872 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1873 mips32_op = OPC_MADD_S; 1874 goto do_madd; 1875 case MADD_D: 1876 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1877 mips32_op = OPC_MADD_D; 1878 goto do_madd; 1879 case MADD_PS: 1880 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1881 mips32_op = OPC_MADD_PS; 1882 goto do_madd; 1883 case MSUB_S: 1884 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1885 mips32_op = OPC_MSUB_S; 1886 goto do_madd; 1887 case MSUB_D: 1888 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1889 mips32_op = OPC_MSUB_D; 1890 goto do_madd; 1891 case MSUB_PS: 1892 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1893 mips32_op = OPC_MSUB_PS; 1894 goto do_madd; 1895 case NMADD_S: 1896 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1897 mips32_op = OPC_NMADD_S; 1898 goto do_madd; 1899 case NMADD_D: 1900 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1901 mips32_op = OPC_NMADD_D; 1902 goto do_madd; 1903 case NMADD_PS: 1904 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1905 mips32_op = OPC_NMADD_PS; 1906 goto do_madd; 1907 case NMSUB_S: 1908 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1909 mips32_op = OPC_NMSUB_S; 1910 goto do_madd; 1911 case NMSUB_D: 1912 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1913 mips32_op = OPC_NMSUB_D; 1914 goto do_madd; 1915 case NMSUB_PS: 1916 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1917 mips32_op = OPC_NMSUB_PS; 1918 do_madd: 1919 gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt); 1920 break; 1921 case CABS_COND_FMT: 1922 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1923 cond = (ctx->opcode >> 6) & 0xf; 1924 cc = (ctx->opcode >> 13) & 0x7; 1925 fmt = (ctx->opcode >> 10) & 0x3; 1926 switch (fmt) { 1927 case 0x0: 1928 gen_cmpabs_s(ctx, cond, rt, rs, cc); 1929 break; 1930 case 0x1: 1931 gen_cmpabs_d(ctx, cond, rt, rs, cc); 1932 break; 1933 case 0x2: 1934 gen_cmpabs_ps(ctx, cond, rt, rs, cc); 1935 break; 1936 default: 1937 goto pool32f_invalid; 1938 } 1939 break; 1940 case C_COND_FMT: 1941 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1942 cond = (ctx->opcode >> 6) & 0xf; 1943 cc = (ctx->opcode >> 13) & 0x7; 1944 fmt = (ctx->opcode >> 10) & 0x3; 1945 switch (fmt) { 1946 case 0x0: 1947 gen_cmp_s(ctx, cond, rt, rs, cc); 1948 break; 1949 case 0x1: 1950 gen_cmp_d(ctx, cond, rt, rs, cc); 1951 break; 1952 case 0x2: 1953 gen_cmp_ps(ctx, cond, rt, rs, cc); 1954 break; 1955 default: 1956 goto pool32f_invalid; 1957 } 1958 break; 1959 case CMP_CONDN_S: 1960 check_insn(ctx, ISA_MIPS_R6); 1961 gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); 1962 break; 1963 case CMP_CONDN_D: 1964 check_insn(ctx, ISA_MIPS_R6); 1965 gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); 1966 break; 1967 case POOL32FXF: 1968 gen_pool32fxf(ctx, rt, rs); 1969 break; 1970 case 0x00: 1971 /* PLL foo */ 1972 switch ((ctx->opcode >> 6) & 0x7) { 1973 case PLL_PS: 1974 mips32_op = OPC_PLL_PS; 1975 goto do_ps; 1976 case PLU_PS: 1977 mips32_op = OPC_PLU_PS; 1978 goto do_ps; 1979 case PUL_PS: 1980 mips32_op = OPC_PUL_PS; 1981 goto do_ps; 1982 case PUU_PS: 1983 mips32_op = OPC_PUU_PS; 1984 goto do_ps; 1985 case CVT_PS_S: 1986 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1987 mips32_op = OPC_CVT_PS_S; 1988 do_ps: 1989 gen_farith(ctx, mips32_op, rt, rs, rd, 0); 1990 break; 1991 default: 1992 goto pool32f_invalid; 1993 } 1994 break; 1995 case MIN_FMT: 1996 check_insn(ctx, ISA_MIPS_R6); 1997 switch ((ctx->opcode >> 9) & 0x3) { 1998 case FMT_SDPS_S: 1999 gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0); 2000 break; 2001 case FMT_SDPS_D: 2002 gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0); 2003 break; 2004 default: 2005 goto pool32f_invalid; 2006 } 2007 break; 2008 case 0x08: 2009 /* [LS][WDU]XC1 */ 2010 switch ((ctx->opcode >> 6) & 0x7) { 2011 case LWXC1: 2012 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2013 mips32_op = OPC_LWXC1; 2014 goto do_ldst_cp1; 2015 case SWXC1: 2016 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2017 mips32_op = OPC_SWXC1; 2018 goto do_ldst_cp1; 2019 case LDXC1: 2020 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2021 mips32_op = OPC_LDXC1; 2022 goto do_ldst_cp1; 2023 case SDXC1: 2024 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2025 mips32_op = OPC_SDXC1; 2026 goto do_ldst_cp1; 2027 case LUXC1: 2028 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2029 mips32_op = OPC_LUXC1; 2030 goto do_ldst_cp1; 2031 case SUXC1: 2032 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2033 mips32_op = OPC_SUXC1; 2034 do_ldst_cp1: 2035 gen_flt3_ldst(ctx, mips32_op, rd, rd, rt, rs); 2036 break; 2037 default: 2038 goto pool32f_invalid; 2039 } 2040 break; 2041 case MAX_FMT: 2042 check_insn(ctx, ISA_MIPS_R6); 2043 switch ((ctx->opcode >> 9) & 0x3) { 2044 case FMT_SDPS_S: 2045 gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0); 2046 break; 2047 case FMT_SDPS_D: 2048 gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0); 2049 break; 2050 default: 2051 goto pool32f_invalid; 2052 } 2053 break; 2054 case 0x18: 2055 /* 3D insns */ 2056 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2057 fmt = (ctx->opcode >> 9) & 0x3; 2058 switch ((ctx->opcode >> 6) & 0x7) { 2059 case RSQRT2_FMT: 2060 switch (fmt) { 2061 case FMT_SDPS_S: 2062 mips32_op = OPC_RSQRT2_S; 2063 goto do_3d; 2064 case FMT_SDPS_D: 2065 mips32_op = OPC_RSQRT2_D; 2066 goto do_3d; 2067 case FMT_SDPS_PS: 2068 mips32_op = OPC_RSQRT2_PS; 2069 goto do_3d; 2070 default: 2071 goto pool32f_invalid; 2072 } 2073 break; 2074 case RECIP2_FMT: 2075 switch (fmt) { 2076 case FMT_SDPS_S: 2077 mips32_op = OPC_RECIP2_S; 2078 goto do_3d; 2079 case FMT_SDPS_D: 2080 mips32_op = OPC_RECIP2_D; 2081 goto do_3d; 2082 case FMT_SDPS_PS: 2083 mips32_op = OPC_RECIP2_PS; 2084 goto do_3d; 2085 default: 2086 goto pool32f_invalid; 2087 } 2088 break; 2089 case ADDR_PS: 2090 mips32_op = OPC_ADDR_PS; 2091 goto do_3d; 2092 case MULR_PS: 2093 mips32_op = OPC_MULR_PS; 2094 do_3d: 2095 gen_farith(ctx, mips32_op, rt, rs, rd, 0); 2096 break; 2097 default: 2098 goto pool32f_invalid; 2099 } 2100 break; 2101 case 0x20: 2102 /* MOV[FT].fmt, PREFX, RINT.fmt, CLASS.fmt*/ 2103 cc = (ctx->opcode >> 13) & 0x7; 2104 fmt = (ctx->opcode >> 9) & 0x3; 2105 switch ((ctx->opcode >> 6) & 0x7) { 2106 case MOVF_FMT: /* RINT_FMT */ 2107 if (ctx->insn_flags & ISA_MIPS_R6) { 2108 /* RINT_FMT */ 2109 switch (fmt) { 2110 case FMT_SDPS_S: 2111 gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0); 2112 break; 2113 case FMT_SDPS_D: 2114 gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0); 2115 break; 2116 default: 2117 goto pool32f_invalid; 2118 } 2119 } else { 2120 /* MOVF_FMT */ 2121 switch (fmt) { 2122 case FMT_SDPS_S: 2123 gen_movcf_s(ctx, rs, rt, cc, 0); 2124 break; 2125 case FMT_SDPS_D: 2126 gen_movcf_d(ctx, rs, rt, cc, 0); 2127 break; 2128 case FMT_SDPS_PS: 2129 check_ps(ctx); 2130 gen_movcf_ps(ctx, rs, rt, cc, 0); 2131 break; 2132 default: 2133 goto pool32f_invalid; 2134 } 2135 } 2136 break; 2137 case MOVT_FMT: /* CLASS_FMT */ 2138 if (ctx->insn_flags & ISA_MIPS_R6) { 2139 /* CLASS_FMT */ 2140 switch (fmt) { 2141 case FMT_SDPS_S: 2142 gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0); 2143 break; 2144 case FMT_SDPS_D: 2145 gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0); 2146 break; 2147 default: 2148 goto pool32f_invalid; 2149 } 2150 } else { 2151 /* MOVT_FMT */ 2152 switch (fmt) { 2153 case FMT_SDPS_S: 2154 gen_movcf_s(ctx, rs, rt, cc, 1); 2155 break; 2156 case FMT_SDPS_D: 2157 gen_movcf_d(ctx, rs, rt, cc, 1); 2158 break; 2159 case FMT_SDPS_PS: 2160 check_ps(ctx); 2161 gen_movcf_ps(ctx, rs, rt, cc, 1); 2162 break; 2163 default: 2164 goto pool32f_invalid; 2165 } 2166 } 2167 break; 2168 case PREFX: 2169 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2170 break; 2171 default: 2172 goto pool32f_invalid; 2173 } 2174 break; 2175#define FINSN_3ARG_SDPS(prfx) \ 2176 switch ((ctx->opcode >> 8) & 0x3) { \ 2177 case FMT_SDPS_S: \ 2178 mips32_op = OPC_##prfx##_S; \ 2179 goto do_fpop; \ 2180 case FMT_SDPS_D: \ 2181 mips32_op = OPC_##prfx##_D; \ 2182 goto do_fpop; \ 2183 case FMT_SDPS_PS: \ 2184 check_ps(ctx); \ 2185 mips32_op = OPC_##prfx##_PS; \ 2186 goto do_fpop; \ 2187 default: \ 2188 goto pool32f_invalid; \ 2189 } 2190 case MINA_FMT: 2191 check_insn(ctx, ISA_MIPS_R6); 2192 switch ((ctx->opcode >> 9) & 0x3) { 2193 case FMT_SDPS_S: 2194 gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0); 2195 break; 2196 case FMT_SDPS_D: 2197 gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0); 2198 break; 2199 default: 2200 goto pool32f_invalid; 2201 } 2202 break; 2203 case MAXA_FMT: 2204 check_insn(ctx, ISA_MIPS_R6); 2205 switch ((ctx->opcode >> 9) & 0x3) { 2206 case FMT_SDPS_S: 2207 gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0); 2208 break; 2209 case FMT_SDPS_D: 2210 gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0); 2211 break; 2212 default: 2213 goto pool32f_invalid; 2214 } 2215 break; 2216 case 0x30: 2217 /* regular FP ops */ 2218 switch ((ctx->opcode >> 6) & 0x3) { 2219 case ADD_FMT: 2220 FINSN_3ARG_SDPS(ADD); 2221 break; 2222 case SUB_FMT: 2223 FINSN_3ARG_SDPS(SUB); 2224 break; 2225 case MUL_FMT: 2226 FINSN_3ARG_SDPS(MUL); 2227 break; 2228 case DIV_FMT: 2229 fmt = (ctx->opcode >> 8) & 0x3; 2230 if (fmt == 1) { 2231 mips32_op = OPC_DIV_D; 2232 } else if (fmt == 0) { 2233 mips32_op = OPC_DIV_S; 2234 } else { 2235 goto pool32f_invalid; 2236 } 2237 goto do_fpop; 2238 default: 2239 goto pool32f_invalid; 2240 } 2241 break; 2242 case 0x38: 2243 /* cmovs */ 2244 switch ((ctx->opcode >> 6) & 0x7) { 2245 case MOVN_FMT: /* SELEQZ_FMT */ 2246 if (ctx->insn_flags & ISA_MIPS_R6) { 2247 /* SELEQZ_FMT */ 2248 switch ((ctx->opcode >> 9) & 0x3) { 2249 case FMT_SDPS_S: 2250 gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs); 2251 break; 2252 case FMT_SDPS_D: 2253 gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs); 2254 break; 2255 default: 2256 goto pool32f_invalid; 2257 } 2258 } else { 2259 /* MOVN_FMT */ 2260 FINSN_3ARG_SDPS(MOVN); 2261 } 2262 break; 2263 case MOVN_FMT_04: 2264 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2265 FINSN_3ARG_SDPS(MOVN); 2266 break; 2267 case MOVZ_FMT: /* SELNEZ_FMT */ 2268 if (ctx->insn_flags & ISA_MIPS_R6) { 2269 /* SELNEZ_FMT */ 2270 switch ((ctx->opcode >> 9) & 0x3) { 2271 case FMT_SDPS_S: 2272 gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs); 2273 break; 2274 case FMT_SDPS_D: 2275 gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs); 2276 break; 2277 default: 2278 goto pool32f_invalid; 2279 } 2280 } else { 2281 /* MOVZ_FMT */ 2282 FINSN_3ARG_SDPS(MOVZ); 2283 } 2284 break; 2285 case MOVZ_FMT_05: 2286 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2287 FINSN_3ARG_SDPS(MOVZ); 2288 break; 2289 case SEL_FMT: 2290 check_insn(ctx, ISA_MIPS_R6); 2291 switch ((ctx->opcode >> 9) & 0x3) { 2292 case FMT_SDPS_S: 2293 gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs); 2294 break; 2295 case FMT_SDPS_D: 2296 gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs); 2297 break; 2298 default: 2299 goto pool32f_invalid; 2300 } 2301 break; 2302 case MADDF_FMT: 2303 check_insn(ctx, ISA_MIPS_R6); 2304 switch ((ctx->opcode >> 9) & 0x3) { 2305 case FMT_SDPS_S: 2306 mips32_op = OPC_MADDF_S; 2307 goto do_fpop; 2308 case FMT_SDPS_D: 2309 mips32_op = OPC_MADDF_D; 2310 goto do_fpop; 2311 default: 2312 goto pool32f_invalid; 2313 } 2314 break; 2315 case MSUBF_FMT: 2316 check_insn(ctx, ISA_MIPS_R6); 2317 switch ((ctx->opcode >> 9) & 0x3) { 2318 case FMT_SDPS_S: 2319 mips32_op = OPC_MSUBF_S; 2320 goto do_fpop; 2321 case FMT_SDPS_D: 2322 mips32_op = OPC_MSUBF_D; 2323 goto do_fpop; 2324 default: 2325 goto pool32f_invalid; 2326 } 2327 break; 2328 default: 2329 goto pool32f_invalid; 2330 } 2331 break; 2332 do_fpop: 2333 gen_farith(ctx, mips32_op, rt, rs, rd, 0); 2334 break; 2335 default: 2336 pool32f_invalid: 2337 MIPS_INVAL("pool32f"); 2338 gen_reserved_instruction(ctx); 2339 break; 2340 } 2341 } else { 2342 generate_exception_err(ctx, EXCP_CpU, 1); 2343 } 2344 break; 2345 case POOL32I: 2346 minor = (ctx->opcode >> 21) & 0x1f; 2347 switch (minor) { 2348 case BLTZ: 2349 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2350 gen_compute_branch(ctx, OPC_BLTZ, 4, rs, -1, imm << 1, 4); 2351 break; 2352 case BLTZAL: 2353 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2354 gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 4); 2355 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2356 break; 2357 case BLTZALS: 2358 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2359 gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 2); 2360 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2361 break; 2362 case BGEZ: 2363 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2364 gen_compute_branch(ctx, OPC_BGEZ, 4, rs, -1, imm << 1, 4); 2365 break; 2366 case BGEZAL: 2367 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2368 gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 4); 2369 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2370 break; 2371 case BGEZALS: 2372 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2373 gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 2); 2374 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2375 break; 2376 case BLEZ: 2377 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2378 gen_compute_branch(ctx, OPC_BLEZ, 4, rs, -1, imm << 1, 4); 2379 break; 2380 case BGTZ: 2381 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2382 gen_compute_branch(ctx, OPC_BGTZ, 4, rs, -1, imm << 1, 4); 2383 break; 2384 2385 /* Traps */ 2386 case TLTI: /* BC1EQZC */ 2387 if (ctx->insn_flags & ISA_MIPS_R6) { 2388 /* BC1EQZC */ 2389 check_cp1_enabled(ctx); 2390 gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rs, imm << 1, 0); 2391 } else { 2392 /* TLTI */ 2393 mips32_op = OPC_TLTI; 2394 goto do_trapi; 2395 } 2396 break; 2397 case TGEI: /* BC1NEZC */ 2398 if (ctx->insn_flags & ISA_MIPS_R6) { 2399 /* BC1NEZC */ 2400 check_cp1_enabled(ctx); 2401 gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rs, imm << 1, 0); 2402 } else { 2403 /* TGEI */ 2404 mips32_op = OPC_TGEI; 2405 goto do_trapi; 2406 } 2407 break; 2408 case TLTIU: 2409 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2410 mips32_op = OPC_TLTIU; 2411 goto do_trapi; 2412 case TGEIU: 2413 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2414 mips32_op = OPC_TGEIU; 2415 goto do_trapi; 2416 case TNEI: /* SYNCI */ 2417 if (ctx->insn_flags & ISA_MIPS_R6) { 2418 /* SYNCI */ 2419 /* 2420 * Break the TB to be able to sync copied instructions 2421 * immediately. 2422 */ 2423 ctx->base.is_jmp = DISAS_STOP; 2424 } else { 2425 /* TNEI */ 2426 mips32_op = OPC_TNEI; 2427 goto do_trapi; 2428 } 2429 break; 2430 case TEQI: 2431 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2432 mips32_op = OPC_TEQI; 2433 do_trapi: 2434 gen_trap(ctx, mips32_op, rs, -1, imm, 0); 2435 break; 2436 2437 case BNEZC: 2438 case BEQZC: 2439 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2440 gen_compute_branch(ctx, minor == BNEZC ? OPC_BNE : OPC_BEQ, 2441 4, rs, 0, imm << 1, 0); 2442 /* 2443 * Compact branches don't have a delay slot, so just let 2444 * the normal delay slot handling take us to the branch 2445 * target. 2446 */ 2447 break; 2448 case LUI: 2449 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2450 gen_logic_imm(ctx, OPC_LUI, rs, 0, imm); 2451 break; 2452 case SYNCI: 2453 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2454 /* 2455 * Break the TB to be able to sync copied instructions 2456 * immediately. 2457 */ 2458 ctx->base.is_jmp = DISAS_STOP; 2459 break; 2460 case BC2F: 2461 case BC2T: 2462 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2463 /* COP2: Not implemented. */ 2464 generate_exception_err(ctx, EXCP_CpU, 2); 2465 break; 2466 case BC1F: 2467 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2468 mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1FANY2 : OPC_BC1F; 2469 goto do_cp1branch; 2470 case BC1T: 2471 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2472 mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1TANY2 : OPC_BC1T; 2473 goto do_cp1branch; 2474 case BC1ANY4F: 2475 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2476 mips32_op = OPC_BC1FANY4; 2477 goto do_cp1mips3d; 2478 case BC1ANY4T: 2479 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2480 mips32_op = OPC_BC1TANY4; 2481 do_cp1mips3d: 2482 check_cop1x(ctx); 2483 check_insn(ctx, ASE_MIPS3D); 2484 /* Fall through */ 2485 do_cp1branch: 2486 if (env->CP0_Config1 & (1 << CP0C1_FP)) { 2487 check_cp1_enabled(ctx); 2488 gen_compute_branch1(ctx, mips32_op, 2489 (ctx->opcode >> 18) & 0x7, imm << 1); 2490 } else { 2491 generate_exception_err(ctx, EXCP_CpU, 1); 2492 } 2493 break; 2494 default: 2495 MIPS_INVAL("pool32i"); 2496 gen_reserved_instruction(ctx); 2497 break; 2498 } 2499 break; 2500 case POOL32C: 2501 minor = (ctx->opcode >> 12) & 0xf; 2502 offset = sextract32(ctx->opcode, 0, 2503 (ctx->insn_flags & ISA_MIPS_R6) ? 9 : 12); 2504 switch (minor) { 2505 case LWL: 2506 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2507 mips32_op = OPC_LWL; 2508 goto do_ld_lr; 2509 case SWL: 2510 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2511 mips32_op = OPC_SWL; 2512 goto do_st_lr; 2513 case LWR: 2514 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2515 mips32_op = OPC_LWR; 2516 goto do_ld_lr; 2517 case SWR: 2518 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2519 mips32_op = OPC_SWR; 2520 goto do_st_lr; 2521#if defined(TARGET_MIPS64) 2522 case LDL: 2523 check_insn(ctx, ISA_MIPS3); 2524 check_mips_64(ctx); 2525 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2526 mips32_op = OPC_LDL; 2527 goto do_ld_lr; 2528 case SDL: 2529 check_insn(ctx, ISA_MIPS3); 2530 check_mips_64(ctx); 2531 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2532 mips32_op = OPC_SDL; 2533 goto do_st_lr; 2534 case LDR: 2535 check_insn(ctx, ISA_MIPS3); 2536 check_mips_64(ctx); 2537 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2538 mips32_op = OPC_LDR; 2539 goto do_ld_lr; 2540 case SDR: 2541 check_insn(ctx, ISA_MIPS3); 2542 check_mips_64(ctx); 2543 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2544 mips32_op = OPC_SDR; 2545 goto do_st_lr; 2546 case LWU: 2547 check_insn(ctx, ISA_MIPS3); 2548 check_mips_64(ctx); 2549 mips32_op = OPC_LWU; 2550 goto do_ld_lr; 2551 case LLD: 2552 check_insn(ctx, ISA_MIPS3); 2553 check_mips_64(ctx); 2554 mips32_op = OPC_LLD; 2555 goto do_ld_lr; 2556#endif 2557 case LL: 2558 mips32_op = OPC_LL; 2559 goto do_ld_lr; 2560 do_ld_lr: 2561 gen_ld(ctx, mips32_op, rt, rs, offset); 2562 break; 2563 do_st_lr: 2564 gen_st(ctx, mips32_op, rt, rs, offset); 2565 break; 2566 case SC: 2567 gen_st_cond(ctx, rt, rs, offset, MO_TESL, false); 2568 break; 2569#if defined(TARGET_MIPS64) 2570 case SCD: 2571 check_insn(ctx, ISA_MIPS3); 2572 check_mips_64(ctx); 2573 gen_st_cond(ctx, rt, rs, offset, MO_TEUQ, false); 2574 break; 2575#endif 2576 case LD_EVA: 2577 if (!ctx->eva) { 2578 MIPS_INVAL("pool32c ld-eva"); 2579 gen_reserved_instruction(ctx); 2580 break; 2581 } 2582 check_cp0_enabled(ctx); 2583 2584 minor2 = (ctx->opcode >> 9) & 0x7; 2585 offset = sextract32(ctx->opcode, 0, 9); 2586 switch (minor2) { 2587 case LBUE: 2588 mips32_op = OPC_LBUE; 2589 goto do_ld_lr; 2590 case LHUE: 2591 mips32_op = OPC_LHUE; 2592 goto do_ld_lr; 2593 case LWLE: 2594 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2595 mips32_op = OPC_LWLE; 2596 goto do_ld_lr; 2597 case LWRE: 2598 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2599 mips32_op = OPC_LWRE; 2600 goto do_ld_lr; 2601 case LBE: 2602 mips32_op = OPC_LBE; 2603 goto do_ld_lr; 2604 case LHE: 2605 mips32_op = OPC_LHE; 2606 goto do_ld_lr; 2607 case LLE: 2608 mips32_op = OPC_LLE; 2609 goto do_ld_lr; 2610 case LWE: 2611 mips32_op = OPC_LWE; 2612 goto do_ld_lr; 2613 }; 2614 break; 2615 case ST_EVA: 2616 if (!ctx->eva) { 2617 MIPS_INVAL("pool32c st-eva"); 2618 gen_reserved_instruction(ctx); 2619 break; 2620 } 2621 check_cp0_enabled(ctx); 2622 2623 minor2 = (ctx->opcode >> 9) & 0x7; 2624 offset = sextract32(ctx->opcode, 0, 9); 2625 switch (minor2) { 2626 case SWLE: 2627 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2628 mips32_op = OPC_SWLE; 2629 goto do_st_lr; 2630 case SWRE: 2631 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2632 mips32_op = OPC_SWRE; 2633 goto do_st_lr; 2634 case PREFE: 2635 /* Treat as no-op */ 2636 if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) { 2637 /* hint codes 24-31 are reserved and signal RI */ 2638 generate_exception(ctx, EXCP_RI); 2639 } 2640 break; 2641 case CACHEE: 2642 /* Treat as no-op */ 2643 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 2644 gen_cache_operation(ctx, rt, rs, offset); 2645 } 2646 break; 2647 case SBE: 2648 mips32_op = OPC_SBE; 2649 goto do_st_lr; 2650 case SHE: 2651 mips32_op = OPC_SHE; 2652 goto do_st_lr; 2653 case SCE: 2654 gen_st_cond(ctx, rt, rs, offset, MO_TESL, true); 2655 break; 2656 case SWE: 2657 mips32_op = OPC_SWE; 2658 goto do_st_lr; 2659 }; 2660 break; 2661 case PREF: 2662 /* Treat as no-op */ 2663 if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) { 2664 /* hint codes 24-31 are reserved and signal RI */ 2665 generate_exception(ctx, EXCP_RI); 2666 } 2667 break; 2668 default: 2669 MIPS_INVAL("pool32c"); 2670 gen_reserved_instruction(ctx); 2671 break; 2672 } 2673 break; 2674 case ADDI32: /* AUI, LUI */ 2675 if (ctx->insn_flags & ISA_MIPS_R6) { 2676 /* AUI, LUI */ 2677 gen_logic_imm(ctx, OPC_LUI, rt, rs, imm); 2678 } else { 2679 /* ADDI32 */ 2680 mips32_op = OPC_ADDI; 2681 goto do_addi; 2682 } 2683 break; 2684 case ADDIU32: 2685 mips32_op = OPC_ADDIU; 2686 do_addi: 2687 gen_arith_imm(ctx, mips32_op, rt, rs, imm); 2688 break; 2689 2690 /* Logical operations */ 2691 case ORI32: 2692 mips32_op = OPC_ORI; 2693 goto do_logici; 2694 case XORI32: 2695 mips32_op = OPC_XORI; 2696 goto do_logici; 2697 case ANDI32: 2698 mips32_op = OPC_ANDI; 2699 do_logici: 2700 gen_logic_imm(ctx, mips32_op, rt, rs, imm); 2701 break; 2702 2703 /* Set less than immediate */ 2704 case SLTI32: 2705 mips32_op = OPC_SLTI; 2706 goto do_slti; 2707 case SLTIU32: 2708 mips32_op = OPC_SLTIU; 2709 do_slti: 2710 gen_slt_imm(ctx, mips32_op, rt, rs, imm); 2711 break; 2712 case JALX32: 2713 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2714 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; 2715 gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset, 4); 2716 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2717 break; 2718 case JALS32: /* BOVC, BEQC, BEQZALC */ 2719 if (ctx->insn_flags & ISA_MIPS_R6) { 2720 if (rs >= rt) { 2721 /* BOVC */ 2722 mips32_op = OPC_BOVC; 2723 } else if (rs < rt && rs == 0) { 2724 /* BEQZALC */ 2725 mips32_op = OPC_BEQZALC; 2726 } else { 2727 /* BEQC */ 2728 mips32_op = OPC_BEQC; 2729 } 2730 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2731 } else { 2732 /* JALS32 */ 2733 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 1; 2734 gen_compute_branch(ctx, OPC_JAL, 4, rt, rs, offset, 2); 2735 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2736 } 2737 break; 2738 case BEQ32: /* BC */ 2739 if (ctx->insn_flags & ISA_MIPS_R6) { 2740 /* BC */ 2741 gen_compute_compact_branch(ctx, OPC_BC, 0, 0, 2742 sextract32(ctx->opcode << 1, 0, 27)); 2743 } else { 2744 /* BEQ32 */ 2745 gen_compute_branch(ctx, OPC_BEQ, 4, rt, rs, imm << 1, 4); 2746 } 2747 break; 2748 case BNE32: /* BALC */ 2749 if (ctx->insn_flags & ISA_MIPS_R6) { 2750 /* BALC */ 2751 gen_compute_compact_branch(ctx, OPC_BALC, 0, 0, 2752 sextract32(ctx->opcode << 1, 0, 27)); 2753 } else { 2754 /* BNE32 */ 2755 gen_compute_branch(ctx, OPC_BNE, 4, rt, rs, imm << 1, 4); 2756 } 2757 break; 2758 case J32: /* BGTZC, BLTZC, BLTC */ 2759 if (ctx->insn_flags & ISA_MIPS_R6) { 2760 if (rs == 0 && rt != 0) { 2761 /* BGTZC */ 2762 mips32_op = OPC_BGTZC; 2763 } else if (rs != 0 && rt != 0 && rs == rt) { 2764 /* BLTZC */ 2765 mips32_op = OPC_BLTZC; 2766 } else { 2767 /* BLTC */ 2768 mips32_op = OPC_BLTC; 2769 } 2770 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2771 } else { 2772 /* J32 */ 2773 gen_compute_branch(ctx, OPC_J, 4, rt, rs, 2774 (int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4); 2775 } 2776 break; 2777 case JAL32: /* BLEZC, BGEZC, BGEC */ 2778 if (ctx->insn_flags & ISA_MIPS_R6) { 2779 if (rs == 0 && rt != 0) { 2780 /* BLEZC */ 2781 mips32_op = OPC_BLEZC; 2782 } else if (rs != 0 && rt != 0 && rs == rt) { 2783 /* BGEZC */ 2784 mips32_op = OPC_BGEZC; 2785 } else { 2786 /* BGEC */ 2787 mips32_op = OPC_BGEC; 2788 } 2789 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2790 } else { 2791 /* JAL32 */ 2792 gen_compute_branch(ctx, OPC_JAL, 4, rt, rs, 2793 (int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4); 2794 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2795 } 2796 break; 2797 /* Floating point (COP1) */ 2798 case LWC132: 2799 mips32_op = OPC_LWC1; 2800 goto do_cop1; 2801 case LDC132: 2802 mips32_op = OPC_LDC1; 2803 goto do_cop1; 2804 case SWC132: 2805 mips32_op = OPC_SWC1; 2806 goto do_cop1; 2807 case SDC132: 2808 mips32_op = OPC_SDC1; 2809 do_cop1: 2810 gen_cop1_ldst(ctx, mips32_op, rt, rs, imm); 2811 break; 2812 case ADDIUPC: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */ 2813 if (ctx->insn_flags & ISA_MIPS_R6) { 2814 /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */ 2815 switch ((ctx->opcode >> 16) & 0x1f) { 2816 case ADDIUPC_00: 2817 case ADDIUPC_01: 2818 case ADDIUPC_02: 2819 case ADDIUPC_03: 2820 case ADDIUPC_04: 2821 case ADDIUPC_05: 2822 case ADDIUPC_06: 2823 case ADDIUPC_07: 2824 gen_pcrel(ctx, OPC_ADDIUPC, ctx->base.pc_next & ~0x3, rt); 2825 break; 2826 case AUIPC: 2827 gen_pcrel(ctx, OPC_AUIPC, ctx->base.pc_next, rt); 2828 break; 2829 case ALUIPC: 2830 gen_pcrel(ctx, OPC_ALUIPC, ctx->base.pc_next, rt); 2831 break; 2832 case LWPC_08: 2833 case LWPC_09: 2834 case LWPC_0A: 2835 case LWPC_0B: 2836 case LWPC_0C: 2837 case LWPC_0D: 2838 case LWPC_0E: 2839 case LWPC_0F: 2840 gen_pcrel(ctx, R6_OPC_LWPC, ctx->base.pc_next & ~0x3, rt); 2841 break; 2842 default: 2843 generate_exception(ctx, EXCP_RI); 2844 break; 2845 } 2846 } else { 2847 /* ADDIUPC */ 2848 int reg = mmreg(ZIMM(ctx->opcode, 23, 3)); 2849 offset = SIMM(ctx->opcode, 0, 23) << 2; 2850 2851 gen_addiupc(ctx, reg, offset, 0, 0); 2852 } 2853 break; 2854 case BNVC: /* BNEC, BNEZALC */ 2855 check_insn(ctx, ISA_MIPS_R6); 2856 if (rs >= rt) { 2857 /* BNVC */ 2858 mips32_op = OPC_BNVC; 2859 } else if (rs < rt && rs == 0) { 2860 /* BNEZALC */ 2861 mips32_op = OPC_BNEZALC; 2862 } else { 2863 /* BNEC */ 2864 mips32_op = OPC_BNEC; 2865 } 2866 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2867 break; 2868 case R6_BNEZC: /* JIALC */ 2869 check_insn(ctx, ISA_MIPS_R6); 2870 if (rt != 0) { 2871 /* BNEZC */ 2872 gen_compute_compact_branch(ctx, OPC_BNEZC, rt, 0, 2873 sextract32(ctx->opcode << 1, 0, 22)); 2874 } else { 2875 /* JIALC */ 2876 gen_compute_compact_branch(ctx, OPC_JIALC, 0, rs, imm); 2877 } 2878 break; 2879 case R6_BEQZC: /* JIC */ 2880 check_insn(ctx, ISA_MIPS_R6); 2881 if (rt != 0) { 2882 /* BEQZC */ 2883 gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0, 2884 sextract32(ctx->opcode << 1, 0, 22)); 2885 } else { 2886 /* JIC */ 2887 gen_compute_compact_branch(ctx, OPC_JIC, 0, rs, imm); 2888 } 2889 break; 2890 case BLEZALC: /* BGEZALC, BGEUC */ 2891 check_insn(ctx, ISA_MIPS_R6); 2892 if (rs == 0 && rt != 0) { 2893 /* BLEZALC */ 2894 mips32_op = OPC_BLEZALC; 2895 } else if (rs != 0 && rt != 0 && rs == rt) { 2896 /* BGEZALC */ 2897 mips32_op = OPC_BGEZALC; 2898 } else { 2899 /* BGEUC */ 2900 mips32_op = OPC_BGEUC; 2901 } 2902 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2903 break; 2904 case BGTZALC: /* BLTZALC, BLTUC */ 2905 check_insn(ctx, ISA_MIPS_R6); 2906 if (rs == 0 && rt != 0) { 2907 /* BGTZALC */ 2908 mips32_op = OPC_BGTZALC; 2909 } else if (rs != 0 && rt != 0 && rs == rt) { 2910 /* BLTZALC */ 2911 mips32_op = OPC_BLTZALC; 2912 } else { 2913 /* BLTUC */ 2914 mips32_op = OPC_BLTUC; 2915 } 2916 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2917 break; 2918 /* Loads and stores */ 2919 case LB32: 2920 mips32_op = OPC_LB; 2921 goto do_ld; 2922 case LBU32: 2923 mips32_op = OPC_LBU; 2924 goto do_ld; 2925 case LH32: 2926 mips32_op = OPC_LH; 2927 goto do_ld; 2928 case LHU32: 2929 mips32_op = OPC_LHU; 2930 goto do_ld; 2931 case LW32: 2932 mips32_op = OPC_LW; 2933 goto do_ld; 2934#ifdef TARGET_MIPS64 2935 case LD32: 2936 check_insn(ctx, ISA_MIPS3); 2937 check_mips_64(ctx); 2938 mips32_op = OPC_LD; 2939 goto do_ld; 2940 case SD32: 2941 check_insn(ctx, ISA_MIPS3); 2942 check_mips_64(ctx); 2943 mips32_op = OPC_SD; 2944 goto do_st; 2945#endif 2946 case SB32: 2947 mips32_op = OPC_SB; 2948 goto do_st; 2949 case SH32: 2950 mips32_op = OPC_SH; 2951 goto do_st; 2952 case SW32: 2953 mips32_op = OPC_SW; 2954 goto do_st; 2955 do_ld: 2956 gen_ld(ctx, mips32_op, rt, rs, imm); 2957 break; 2958 do_st: 2959 gen_st(ctx, mips32_op, rt, rs, imm); 2960 break; 2961 default: 2962 gen_reserved_instruction(ctx); 2963 break; 2964 } 2965} 2966 2967static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) 2968{ 2969 uint32_t op; 2970 2971 /* make sure instructions are on a halfword boundary */ 2972 if (ctx->base.pc_next & 0x1) { 2973 env->CP0_BadVAddr = ctx->base.pc_next; 2974 generate_exception_end(ctx, EXCP_AdEL); 2975 return 2; 2976 } 2977 2978 op = (ctx->opcode >> 10) & 0x3f; 2979 /* Enforce properly-sized instructions in a delay slot */ 2980 if (ctx->hflags & MIPS_HFLAG_BDS_STRICT) { 2981 switch (op & 0x7) { /* MSB-3..MSB-5 */ 2982 case 0: 2983 /* POOL32A, POOL32B, POOL32I, POOL32C */ 2984 case 4: 2985 /* ADDI32, ADDIU32, ORI32, XORI32, SLTI32, SLTIU32, ANDI32, JALX32 */ 2986 case 5: 2987 /* LBU32, LHU32, POOL32F, JALS32, BEQ32, BNE32, J32, JAL32 */ 2988 case 6: 2989 /* SB32, SH32, ADDIUPC, SWC132, SDC132, SW32 */ 2990 case 7: 2991 /* LB32, LH32, LWC132, LDC132, LW32 */ 2992 if (ctx->hflags & MIPS_HFLAG_BDS16) { 2993 gen_reserved_instruction(ctx); 2994 return 2; 2995 } 2996 break; 2997 case 1: 2998 /* POOL16A, POOL16B, POOL16C, LWGP16, POOL16F */ 2999 case 2: 3000 /* LBU16, LHU16, LWSP16, LW16, SB16, SH16, SWSP16, SW16 */ 3001 case 3: 3002 /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */ 3003 if (ctx->hflags & MIPS_HFLAG_BDS32) { 3004 gen_reserved_instruction(ctx); 3005 return 2; 3006 } 3007 break; 3008 } 3009 } 3010 3011 switch (op) { 3012 case POOL16A: 3013 { 3014 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3015 int rs1 = mmreg(uMIPS_RS1(ctx->opcode)); 3016 int rs2 = mmreg(uMIPS_RS2(ctx->opcode)); 3017 uint32_t opc = 0; 3018 3019 switch (ctx->opcode & 0x1) { 3020 case ADDU16: 3021 opc = OPC_ADDU; 3022 break; 3023 case SUBU16: 3024 opc = OPC_SUBU; 3025 break; 3026 } 3027 if (ctx->insn_flags & ISA_MIPS_R6) { 3028 /* 3029 * In the Release 6, the register number location in 3030 * the instruction encoding has changed. 3031 */ 3032 gen_arith(ctx, opc, rs1, rd, rs2); 3033 } else { 3034 gen_arith(ctx, opc, rd, rs1, rs2); 3035 } 3036 } 3037 break; 3038 case POOL16B: 3039 { 3040 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3041 int rs = mmreg(uMIPS_RS(ctx->opcode)); 3042 int amount = (ctx->opcode >> 1) & 0x7; 3043 uint32_t opc = 0; 3044 amount = amount == 0 ? 8 : amount; 3045 3046 switch (ctx->opcode & 0x1) { 3047 case SLL16: 3048 opc = OPC_SLL; 3049 break; 3050 case SRL16: 3051 opc = OPC_SRL; 3052 break; 3053 } 3054 3055 gen_shift_imm(ctx, opc, rd, rs, amount); 3056 } 3057 break; 3058 case POOL16C: 3059 if (ctx->insn_flags & ISA_MIPS_R6) { 3060 gen_pool16c_r6_insn(ctx); 3061 } else { 3062 gen_pool16c_insn(ctx); 3063 } 3064 break; 3065 case LWGP16: 3066 { 3067 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3068 int rb = 28; /* GP */ 3069 int16_t offset = SIMM(ctx->opcode, 0, 7) << 2; 3070 3071 gen_ld(ctx, OPC_LW, rd, rb, offset); 3072 } 3073 break; 3074 case POOL16F: 3075 check_insn_opc_removed(ctx, ISA_MIPS_R6); 3076 if (ctx->opcode & 1) { 3077 gen_reserved_instruction(ctx); 3078 } else { 3079 /* MOVEP */ 3080 int enc_dest = uMIPS_RD(ctx->opcode); 3081 int enc_rt = uMIPS_RS2(ctx->opcode); 3082 int enc_rs = uMIPS_RS1(ctx->opcode); 3083 gen_movep(ctx, enc_dest, enc_rt, enc_rs); 3084 } 3085 break; 3086 case LBU16: 3087 { 3088 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3089 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3090 int16_t offset = ZIMM(ctx->opcode, 0, 4); 3091 offset = (offset == 0xf ? -1 : offset); 3092 3093 gen_ld(ctx, OPC_LBU, rd, rb, offset); 3094 } 3095 break; 3096 case LHU16: 3097 { 3098 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3099 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3100 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1; 3101 3102 gen_ld(ctx, OPC_LHU, rd, rb, offset); 3103 } 3104 break; 3105 case LWSP16: 3106 { 3107 int rd = (ctx->opcode >> 5) & 0x1f; 3108 int rb = 29; /* SP */ 3109 int16_t offset = ZIMM(ctx->opcode, 0, 5) << 2; 3110 3111 gen_ld(ctx, OPC_LW, rd, rb, offset); 3112 } 3113 break; 3114 case LW16: 3115 { 3116 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3117 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3118 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2; 3119 3120 gen_ld(ctx, OPC_LW, rd, rb, offset); 3121 } 3122 break; 3123 case SB16: 3124 { 3125 int rd = mmreg2(uMIPS_RD(ctx->opcode)); 3126 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3127 int16_t offset = ZIMM(ctx->opcode, 0, 4); 3128 3129 gen_st(ctx, OPC_SB, rd, rb, offset); 3130 } 3131 break; 3132 case SH16: 3133 { 3134 int rd = mmreg2(uMIPS_RD(ctx->opcode)); 3135 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3136 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1; 3137 3138 gen_st(ctx, OPC_SH, rd, rb, offset); 3139 } 3140 break; 3141 case SWSP16: 3142 { 3143 int rd = (ctx->opcode >> 5) & 0x1f; 3144 int rb = 29; /* SP */ 3145 int16_t offset = ZIMM(ctx->opcode, 0, 5) << 2; 3146 3147 gen_st(ctx, OPC_SW, rd, rb, offset); 3148 } 3149 break; 3150 case SW16: 3151 { 3152 int rd = mmreg2(uMIPS_RD(ctx->opcode)); 3153 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3154 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2; 3155 3156 gen_st(ctx, OPC_SW, rd, rb, offset); 3157 } 3158 break; 3159 case MOVE16: 3160 { 3161 int rd = uMIPS_RD5(ctx->opcode); 3162 int rs = uMIPS_RS5(ctx->opcode); 3163 3164 gen_arith(ctx, OPC_ADDU, rd, rs, 0); 3165 } 3166 break; 3167 case ANDI16: 3168 gen_andi16(ctx); 3169 break; 3170 case POOL16D: 3171 switch (ctx->opcode & 0x1) { 3172 case ADDIUS5: 3173 gen_addius5(ctx); 3174 break; 3175 case ADDIUSP: 3176 gen_addiusp(ctx); 3177 break; 3178 } 3179 break; 3180 case POOL16E: 3181 switch (ctx->opcode & 0x1) { 3182 case ADDIUR2: 3183 gen_addiur2(ctx); 3184 break; 3185 case ADDIUR1SP: 3186 gen_addiur1sp(ctx); 3187 break; 3188 } 3189 break; 3190 case B16: /* BC16 */ 3191 gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, 3192 sextract32(ctx->opcode, 0, 10) << 1, 3193 (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4); 3194 break; 3195 case BNEZ16: /* BNEZC16 */ 3196 case BEQZ16: /* BEQZC16 */ 3197 gen_compute_branch(ctx, op == BNEZ16 ? OPC_BNE : OPC_BEQ, 2, 3198 mmreg(uMIPS_RD(ctx->opcode)), 3199 0, sextract32(ctx->opcode, 0, 7) << 1, 3200 (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4); 3201 3202 break; 3203 case LI16: 3204 { 3205 int reg = mmreg(uMIPS_RD(ctx->opcode)); 3206 int imm = ZIMM(ctx->opcode, 0, 7); 3207 3208 imm = (imm == 0x7f ? -1 : imm); 3209 tcg_gen_movi_tl(cpu_gpr[reg], imm); 3210 } 3211 break; 3212 case RES_29: 3213 case RES_31: 3214 case RES_39: 3215 gen_reserved_instruction(ctx); 3216 break; 3217 default: 3218 decode_micromips32_opc(env, ctx); 3219 return 4; 3220 } 3221 3222 return 2; 3223} 3224