1/* 2 * microMIPS translation routines 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * Copyright (c) 2006 Marius Groeger (FPU operations) 6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) 7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) 8 * 9 * SPDX-License-Identifier: LGPL-2.1-or-later 10 */ 11 12/* 13 * microMIPS32/microMIPS64 major opcodes 14 * 15 * 1. MIPS Architecture for Programmers Volume II-B: 16 * The microMIPS32 Instruction Set (Revision 3.05) 17 * 18 * Table 6.2 microMIPS32 Encoding of Major Opcode Field 19 * 20 * 2. MIPS Architecture For Programmers Volume II-A: 21 * The MIPS64 Instruction Set (Revision 3.51) 22 */ 23 24enum { 25 POOL32A = 0x00, 26 POOL16A = 0x01, 27 LBU16 = 0x02, 28 MOVE16 = 0x03, 29 ADDI32 = 0x04, 30 R6_LUI = 0x04, 31 AUI = 0x04, 32 LBU32 = 0x05, 33 SB32 = 0x06, 34 LB32 = 0x07, 35 36 POOL32B = 0x08, 37 POOL16B = 0x09, 38 LHU16 = 0x0a, 39 ANDI16 = 0x0b, 40 ADDIU32 = 0x0c, 41 LHU32 = 0x0d, 42 SH32 = 0x0e, 43 LH32 = 0x0f, 44 45 POOL32I = 0x10, 46 POOL16C = 0x11, 47 LWSP16 = 0x12, 48 POOL16D = 0x13, 49 ORI32 = 0x14, 50 POOL32F = 0x15, 51 POOL32S = 0x16, /* MIPS64 */ 52 DADDIU32 = 0x17, /* MIPS64 */ 53 54 POOL32C = 0x18, 55 LWGP16 = 0x19, 56 LW16 = 0x1a, 57 POOL16E = 0x1b, 58 XORI32 = 0x1c, 59 JALS32 = 0x1d, 60 BOVC = 0x1d, 61 BEQC = 0x1d, 62 BEQZALC = 0x1d, 63 ADDIUPC = 0x1e, 64 PCREL = 0x1e, 65 BNVC = 0x1f, 66 BNEC = 0x1f, 67 BNEZALC = 0x1f, 68 69 R6_BEQZC = 0x20, 70 JIC = 0x20, 71 POOL16F = 0x21, 72 SB16 = 0x22, 73 BEQZ16 = 0x23, 74 BEQZC16 = 0x23, 75 SLTI32 = 0x24, 76 BEQ32 = 0x25, 77 BC = 0x25, 78 SWC132 = 0x26, 79 LWC132 = 0x27, 80 81 /* 0x29 is reserved */ 82 RES_29 = 0x29, 83 R6_BNEZC = 0x28, 84 JIALC = 0x28, 85 SH16 = 0x2a, 86 BNEZ16 = 0x2b, 87 BNEZC16 = 0x2b, 88 SLTIU32 = 0x2c, 89 BNE32 = 0x2d, 90 BALC = 0x2d, 91 SDC132 = 0x2e, 92 LDC132 = 0x2f, 93 94 /* 0x31 is reserved */ 95 RES_31 = 0x31, 96 BLEZALC = 0x30, 97 BGEZALC = 0x30, 98 BGEUC = 0x30, 99 SWSP16 = 0x32, 100 B16 = 0x33, 101 BC16 = 0x33, 102 ANDI32 = 0x34, 103 J32 = 0x35, 104 BGTZC = 0x35, 105 BLTZC = 0x35, 106 BLTC = 0x35, 107 SD32 = 0x36, /* MIPS64 */ 108 LD32 = 0x37, /* MIPS64 */ 109 110 /* 0x39 is reserved */ 111 RES_39 = 0x39, 112 BGTZALC = 0x38, 113 BLTZALC = 0x38, 114 BLTUC = 0x38, 115 SW16 = 0x3a, 116 LI16 = 0x3b, 117 JALX32 = 0x3c, 118 JAL32 = 0x3d, 119 BLEZC = 0x3d, 120 BGEZC = 0x3d, 121 BGEC = 0x3d, 122 SW32 = 0x3e, 123 LW32 = 0x3f 124}; 125 126/* PCREL Instructions perform PC-Relative address calculation. bits 20..16 */ 127enum { 128 ADDIUPC_00 = 0x00, 129 ADDIUPC_01 = 0x01, 130 ADDIUPC_02 = 0x02, 131 ADDIUPC_03 = 0x03, 132 ADDIUPC_04 = 0x04, 133 ADDIUPC_05 = 0x05, 134 ADDIUPC_06 = 0x06, 135 ADDIUPC_07 = 0x07, 136 AUIPC = 0x1e, 137 ALUIPC = 0x1f, 138 LWPC_08 = 0x08, 139 LWPC_09 = 0x09, 140 LWPC_0A = 0x0A, 141 LWPC_0B = 0x0B, 142 LWPC_0C = 0x0C, 143 LWPC_0D = 0x0D, 144 LWPC_0E = 0x0E, 145 LWPC_0F = 0x0F, 146}; 147 148/* POOL32A encoding of minor opcode field */ 149 150enum { 151 /* 152 * These opcodes are distinguished only by bits 9..6; those bits are 153 * what are recorded below. 154 */ 155 SLL32 = 0x0, 156 SRL32 = 0x1, 157 SRA = 0x2, 158 ROTR = 0x3, 159 SELEQZ = 0x5, 160 SELNEZ = 0x6, 161 R6_RDHWR = 0x7, 162 163 SLLV = 0x0, 164 SRLV = 0x1, 165 SRAV = 0x2, 166 ROTRV = 0x3, 167 ADD = 0x4, 168 ADDU32 = 0x5, 169 SUB = 0x6, 170 SUBU32 = 0x7, 171 MUL = 0x8, 172 AND = 0x9, 173 OR32 = 0xa, 174 NOR = 0xb, 175 XOR32 = 0xc, 176 SLT = 0xd, 177 SLTU = 0xe, 178 179 MOVN = 0x0, 180 R6_MUL = 0x0, 181 MOVZ = 0x1, 182 MUH = 0x1, 183 MULU = 0x2, 184 MUHU = 0x3, 185 LWXS = 0x4, 186 R6_DIV = 0x4, 187 MOD = 0x5, 188 R6_DIVU = 0x6, 189 MODU = 0x7, 190 191 /* The following can be distinguished by their lower 6 bits. */ 192 BREAK32 = 0x07, 193 INS = 0x0c, 194 LSA = 0x0f, 195 ALIGN = 0x1f, 196 EXT = 0x2c, 197 POOL32AXF = 0x3c, 198 SIGRIE = 0x3f 199}; 200 201/* POOL32AXF encoding of minor opcode field extension */ 202 203/* 204 * 1. MIPS Architecture for Programmers Volume II-B: 205 * The microMIPS32 Instruction Set (Revision 3.05) 206 * 207 * Table 6.5 POOL32Axf Encoding of Minor Opcode Extension Field 208 * 209 * 2. MIPS Architecture for Programmers VolumeIV-e: 210 * The MIPS DSP Application-Specific Extension 211 * to the microMIPS32 Architecture (Revision 2.34) 212 * 213 * Table 5.5 POOL32Axf Encoding of Minor Opcode Extension Field 214 */ 215 216enum { 217 /* bits 11..6 */ 218 TEQ = 0x00, 219 TGE = 0x08, 220 TGEU = 0x10, 221 TLT = 0x20, 222 TLTU = 0x28, 223 TNE = 0x30, 224 225 MFC0 = 0x03, 226 MTC0 = 0x0b, 227 228 /* begin of microMIPS32 DSP */ 229 230 /* bits 13..12 for 0x01 */ 231 MFHI_ACC = 0x0, 232 MFLO_ACC = 0x1, 233 MTHI_ACC = 0x2, 234 MTLO_ACC = 0x3, 235 236 /* bits 13..12 for 0x2a */ 237 MADD_ACC = 0x0, 238 MADDU_ACC = 0x1, 239 MSUB_ACC = 0x2, 240 MSUBU_ACC = 0x3, 241 242 /* bits 13..12 for 0x32 */ 243 MULT_ACC = 0x0, 244 MULTU_ACC = 0x1, 245 246 /* end of microMIPS32 DSP */ 247 248 /* bits 15..12 for 0x2c */ 249 BITSWAP = 0x0, 250 SEB = 0x2, 251 SEH = 0x3, 252 CLO = 0x4, 253 CLZ = 0x5, 254 RDHWR = 0x6, 255 WSBH = 0x7, 256 MULT = 0x8, 257 MULTU = 0x9, 258 DIV = 0xa, 259 DIVU = 0xb, 260 MADD = 0xc, 261 MADDU = 0xd, 262 MSUB = 0xe, 263 MSUBU = 0xf, 264 265 /* bits 15..12 for 0x34 */ 266 MFC2 = 0x4, 267 MTC2 = 0x5, 268 MFHC2 = 0x8, 269 MTHC2 = 0x9, 270 CFC2 = 0xc, 271 CTC2 = 0xd, 272 273 /* bits 15..12 for 0x3c */ 274 JALR = 0x0, 275 JR = 0x0, /* alias */ 276 JALRC = 0x0, 277 JRC = 0x0, 278 JALR_HB = 0x1, 279 JALRC_HB = 0x1, 280 JALRS = 0x4, 281 JALRS_HB = 0x5, 282 283 /* bits 15..12 for 0x05 */ 284 RDPGPR = 0xe, 285 WRPGPR = 0xf, 286 287 /* bits 15..12 for 0x0d */ 288 TLBP = 0x0, 289 TLBR = 0x1, 290 TLBWI = 0x2, 291 TLBWR = 0x3, 292 TLBINV = 0x4, 293 TLBINVF = 0x5, 294 WAIT = 0x9, 295 IRET = 0xd, 296 DERET = 0xe, 297 ERET = 0xf, 298 299 /* bits 15..12 for 0x15 */ 300 DMT = 0x0, 301 DVPE = 0x1, 302 EMT = 0x2, 303 EVPE = 0x3, 304 305 /* bits 15..12 for 0x1d */ 306 DI = 0x4, 307 EI = 0x5, 308 309 /* bits 15..12 for 0x2d */ 310 SYNC = 0x6, 311 SYSCALL = 0x8, 312 SDBBP = 0xd, 313 314 /* bits 15..12 for 0x35 */ 315 MFHI32 = 0x0, 316 MFLO32 = 0x1, 317 MTHI32 = 0x2, 318 MTLO32 = 0x3, 319}; 320 321/* POOL32B encoding of minor opcode field (bits 15..12) */ 322 323enum { 324 LWC2 = 0x0, 325 LWP = 0x1, 326 LDP = 0x4, 327 LWM32 = 0x5, 328 CACHE = 0x6, 329 LDM = 0x7, 330 SWC2 = 0x8, 331 SWP = 0x9, 332 SDP = 0xc, 333 SWM32 = 0xd, 334 SDM = 0xf 335}; 336 337/* POOL32C encoding of minor opcode field (bits 15..12) */ 338 339enum { 340 LWL = 0x0, 341 SWL = 0x8, 342 LWR = 0x1, 343 SWR = 0x9, 344 PREF = 0x2, 345 ST_EVA = 0xa, 346 LL = 0x3, 347 SC = 0xb, 348 LDL = 0x4, 349 SDL = 0xc, 350 LDR = 0x5, 351 SDR = 0xd, 352 LD_EVA = 0x6, 353 LWU = 0xe, 354 LLD = 0x7, 355 SCD = 0xf 356}; 357 358/* POOL32C LD-EVA encoding of minor opcode field (bits 11..9) */ 359 360enum { 361 LBUE = 0x0, 362 LHUE = 0x1, 363 LWLE = 0x2, 364 LWRE = 0x3, 365 LBE = 0x4, 366 LHE = 0x5, 367 LLE = 0x6, 368 LWE = 0x7, 369}; 370 371/* POOL32C ST-EVA encoding of minor opcode field (bits 11..9) */ 372 373enum { 374 SWLE = 0x0, 375 SWRE = 0x1, 376 PREFE = 0x2, 377 CACHEE = 0x3, 378 SBE = 0x4, 379 SHE = 0x5, 380 SCE = 0x6, 381 SWE = 0x7, 382}; 383 384/* POOL32F encoding of minor opcode field (bits 5..0) */ 385 386enum { 387 /* These are the bit 7..6 values */ 388 ADD_FMT = 0x0, 389 390 SUB_FMT = 0x1, 391 392 MUL_FMT = 0x2, 393 394 DIV_FMT = 0x3, 395 396 /* These are the bit 8..6 values */ 397 MOVN_FMT = 0x0, 398 RSQRT2_FMT = 0x0, 399 MOVF_FMT = 0x0, 400 RINT_FMT = 0x0, 401 SELNEZ_FMT = 0x0, 402 403 MOVZ_FMT = 0x1, 404 LWXC1 = 0x1, 405 MOVT_FMT = 0x1, 406 CLASS_FMT = 0x1, 407 SELEQZ_FMT = 0x1, 408 409 PLL_PS = 0x2, 410 SWXC1 = 0x2, 411 SEL_FMT = 0x2, 412 413 PLU_PS = 0x3, 414 LDXC1 = 0x3, 415 416 MOVN_FMT_04 = 0x4, 417 PUL_PS = 0x4, 418 SDXC1 = 0x4, 419 RECIP2_FMT = 0x4, 420 421 MOVZ_FMT_05 = 0x05, 422 PUU_PS = 0x5, 423 LUXC1 = 0x5, 424 425 CVT_PS_S = 0x6, 426 SUXC1 = 0x6, 427 ADDR_PS = 0x6, 428 PREFX = 0x6, 429 MADDF_FMT = 0x6, 430 431 MULR_PS = 0x7, 432 MSUBF_FMT = 0x7, 433 434 MADD_S = 0x01, 435 MADD_D = 0x09, 436 MADD_PS = 0x11, 437 ALNV_PS = 0x19, 438 MSUB_S = 0x21, 439 MSUB_D = 0x29, 440 MSUB_PS = 0x31, 441 442 NMADD_S = 0x02, 443 NMADD_D = 0x0a, 444 NMADD_PS = 0x12, 445 NMSUB_S = 0x22, 446 NMSUB_D = 0x2a, 447 NMSUB_PS = 0x32, 448 449 MIN_FMT = 0x3, 450 MAX_FMT = 0xb, 451 MINA_FMT = 0x23, 452 MAXA_FMT = 0x2b, 453 POOL32FXF = 0x3b, 454 455 CABS_COND_FMT = 0x1c, /* MIPS3D */ 456 C_COND_FMT = 0x3c, 457 458 CMP_CONDN_S = 0x5, 459 CMP_CONDN_D = 0x15 460}; 461 462/* POOL32Fxf encoding of minor opcode extension field */ 463 464enum { 465 CVT_L = 0x04, 466 RSQRT_FMT = 0x08, 467 FLOOR_L = 0x0c, 468 CVT_PW_PS = 0x1c, 469 CVT_W = 0x24, 470 SQRT_FMT = 0x28, 471 FLOOR_W = 0x2c, 472 CVT_PS_PW = 0x3c, 473 CFC1 = 0x40, 474 RECIP_FMT = 0x48, 475 CEIL_L = 0x4c, 476 CTC1 = 0x60, 477 CEIL_W = 0x6c, 478 MFC1 = 0x80, 479 CVT_S_PL = 0x84, 480 TRUNC_L = 0x8c, 481 MTC1 = 0xa0, 482 CVT_S_PU = 0xa4, 483 TRUNC_W = 0xac, 484 MFHC1 = 0xc0, 485 ROUND_L = 0xcc, 486 MTHC1 = 0xe0, 487 ROUND_W = 0xec, 488 489 MOV_FMT = 0x01, 490 MOVF = 0x05, 491 ABS_FMT = 0x0d, 492 RSQRT1_FMT = 0x1d, 493 MOVT = 0x25, 494 NEG_FMT = 0x2d, 495 CVT_D = 0x4d, 496 RECIP1_FMT = 0x5d, 497 CVT_S = 0x6d 498}; 499 500/* POOL32I encoding of minor opcode field (bits 25..21) */ 501 502enum { 503 BLTZ = 0x00, 504 BLTZAL = 0x01, 505 BGEZ = 0x02, 506 BGEZAL = 0x03, 507 BLEZ = 0x04, 508 BNEZC = 0x05, 509 BGTZ = 0x06, 510 BEQZC = 0x07, 511 TLTI = 0x08, 512 BC1EQZC = 0x08, 513 TGEI = 0x09, 514 BC1NEZC = 0x09, 515 TLTIU = 0x0a, 516 BC2EQZC = 0x0a, 517 TGEIU = 0x0b, 518 BC2NEZC = 0x0a, 519 TNEI = 0x0c, 520 R6_SYNCI = 0x0c, 521 LUI = 0x0d, 522 TEQI = 0x0e, 523 SYNCI = 0x10, 524 BLTZALS = 0x11, 525 BGEZALS = 0x13, 526 BC2F = 0x14, 527 BC2T = 0x15, 528 /* These overlap and are distinguished by bit16 of the instruction */ 529 BC1F = 0x1c, 530 BC1T = 0x1d, 531 BC1ANY2F = 0x1c, 532 BC1ANY2T = 0x1d, 533 BC1ANY4F = 0x1e, 534 BC1ANY4T = 0x1f 535}; 536 537/* POOL16A encoding of minor opcode field */ 538 539enum { 540 ADDU16 = 0x0, 541 SUBU16 = 0x1 542}; 543 544/* POOL16B encoding of minor opcode field */ 545 546enum { 547 SLL16 = 0x0, 548 SRL16 = 0x1 549}; 550 551/* POOL16C encoding of minor opcode field */ 552 553enum { 554 NOT16 = 0x00, 555 XOR16 = 0x04, 556 AND16 = 0x08, 557 OR16 = 0x0c, 558 LWM16 = 0x10, 559 SWM16 = 0x14, 560 JR16 = 0x18, 561 JRC16 = 0x1a, 562 JALR16 = 0x1c, 563 JALR16S = 0x1e, 564 MFHI16 = 0x20, 565 MFLO16 = 0x24, 566 BREAK16 = 0x28, 567 SDBBP16 = 0x2c, 568 JRADDIUSP = 0x30 569}; 570 571/* R6 POOL16C encoding of minor opcode field (bits 0..5) */ 572 573enum { 574 R6_NOT16 = 0x00, 575 R6_AND16 = 0x01, 576 R6_LWM16 = 0x02, 577 R6_JRC16 = 0x03, 578 MOVEP = 0x04, 579 MOVEP_05 = 0x05, 580 MOVEP_06 = 0x06, 581 MOVEP_07 = 0x07, 582 R6_XOR16 = 0x08, 583 R6_OR16 = 0x09, 584 R6_SWM16 = 0x0a, 585 JALRC16 = 0x0b, 586 MOVEP_0C = 0x0c, 587 MOVEP_0D = 0x0d, 588 MOVEP_0E = 0x0e, 589 MOVEP_0F = 0x0f, 590 JRCADDIUSP = 0x13, 591 R6_BREAK16 = 0x1b, 592 R6_SDBBP16 = 0x3b 593}; 594 595/* POOL16D encoding of minor opcode field */ 596 597enum { 598 ADDIUS5 = 0x0, 599 ADDIUSP = 0x1 600}; 601 602/* POOL16E encoding of minor opcode field */ 603 604enum { 605 ADDIUR2 = 0x0, 606 ADDIUR1SP = 0x1 607}; 608 609static int mmreg(int r) 610{ 611 static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; 612 613 return map[r]; 614} 615 616/* Used for 16-bit store instructions. */ 617static int mmreg2(int r) 618{ 619 static const int map[] = { 0, 17, 2, 3, 4, 5, 6, 7 }; 620 621 return map[r]; 622} 623 624#define uMIPS_RD(op) ((op >> 7) & 0x7) 625#define uMIPS_RS(op) ((op >> 4) & 0x7) 626#define uMIPS_RS2(op) uMIPS_RS(op) 627#define uMIPS_RS1(op) ((op >> 1) & 0x7) 628#define uMIPS_RD5(op) ((op >> 5) & 0x1f) 629#define uMIPS_RS5(op) (op & 0x1f) 630 631/* Signed immediate */ 632#define SIMM(op, start, width) \ 633 ((int32_t)(((op >> start) & ((~0U) >> (32 - width))) \ 634 << (32 - width)) \ 635 >> (32 - width)) 636/* Zero-extended immediate */ 637#define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32 - width))) 638 639static void gen_addiur1sp(DisasContext *ctx) 640{ 641 int rd = mmreg(uMIPS_RD(ctx->opcode)); 642 643 gen_arith_imm(ctx, OPC_ADDIU, rd, 29, ((ctx->opcode >> 1) & 0x3f) << 2); 644} 645 646static void gen_addiur2(DisasContext *ctx) 647{ 648 static const int decoded_imm[] = { 1, 4, 8, 12, 16, 20, 24, -1 }; 649 int rd = mmreg(uMIPS_RD(ctx->opcode)); 650 int rs = mmreg(uMIPS_RS(ctx->opcode)); 651 652 gen_arith_imm(ctx, OPC_ADDIU, rd, rs, decoded_imm[ZIMM(ctx->opcode, 1, 3)]); 653} 654 655static void gen_addiusp(DisasContext *ctx) 656{ 657 int encoded = ZIMM(ctx->opcode, 1, 9); 658 int decoded; 659 660 if (encoded <= 1) { 661 decoded = 256 + encoded; 662 } else if (encoded <= 255) { 663 decoded = encoded; 664 } else if (encoded <= 509) { 665 decoded = encoded - 512; 666 } else { 667 decoded = encoded - 768; 668 } 669 670 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, decoded << 2); 671} 672 673static void gen_addius5(DisasContext *ctx) 674{ 675 int imm = SIMM(ctx->opcode, 1, 4); 676 int rd = (ctx->opcode >> 5) & 0x1f; 677 678 gen_arith_imm(ctx, OPC_ADDIU, rd, rd, imm); 679} 680 681static void gen_andi16(DisasContext *ctx) 682{ 683 static const int decoded_imm[] = { 128, 1, 2, 3, 4, 7, 8, 15, 16, 684 31, 32, 63, 64, 255, 32768, 65535 }; 685 int rd = mmreg(uMIPS_RD(ctx->opcode)); 686 int rs = mmreg(uMIPS_RS(ctx->opcode)); 687 int encoded = ZIMM(ctx->opcode, 0, 4); 688 689 gen_logic_imm(ctx, OPC_ANDI, rd, rs, decoded_imm[encoded]); 690} 691 692static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist, 693 int base, int16_t offset) 694{ 695 TCGv t0, t1; 696 TCGv_i32 t2; 697 698 if (ctx->hflags & MIPS_HFLAG_BMASK) { 699 gen_reserved_instruction(ctx); 700 return; 701 } 702 703 t0 = tcg_temp_new(); 704 705 gen_base_offset_addr(ctx, t0, base, offset); 706 707 t1 = tcg_const_tl(reglist); 708 t2 = tcg_const_i32(ctx->mem_idx); 709 710 save_cpu_state(ctx, 1); 711 switch (opc) { 712 case LWM32: 713 gen_helper_lwm(cpu_env, t0, t1, t2); 714 break; 715 case SWM32: 716 gen_helper_swm(cpu_env, t0, t1, t2); 717 break; 718#ifdef TARGET_MIPS64 719 case LDM: 720 gen_helper_ldm(cpu_env, t0, t1, t2); 721 break; 722 case SDM: 723 gen_helper_sdm(cpu_env, t0, t1, t2); 724 break; 725#endif 726 } 727 tcg_temp_free(t0); 728 tcg_temp_free(t1); 729 tcg_temp_free_i32(t2); 730} 731 732 733static void gen_pool16c_insn(DisasContext *ctx) 734{ 735 int rd = mmreg((ctx->opcode >> 3) & 0x7); 736 int rs = mmreg(ctx->opcode & 0x7); 737 738 switch (((ctx->opcode) >> 4) & 0x3f) { 739 case NOT16 + 0: 740 case NOT16 + 1: 741 case NOT16 + 2: 742 case NOT16 + 3: 743 gen_logic(ctx, OPC_NOR, rd, rs, 0); 744 break; 745 case XOR16 + 0: 746 case XOR16 + 1: 747 case XOR16 + 2: 748 case XOR16 + 3: 749 gen_logic(ctx, OPC_XOR, rd, rd, rs); 750 break; 751 case AND16 + 0: 752 case AND16 + 1: 753 case AND16 + 2: 754 case AND16 + 3: 755 gen_logic(ctx, OPC_AND, rd, rd, rs); 756 break; 757 case OR16 + 0: 758 case OR16 + 1: 759 case OR16 + 2: 760 case OR16 + 3: 761 gen_logic(ctx, OPC_OR, rd, rd, rs); 762 break; 763 case LWM16 + 0: 764 case LWM16 + 1: 765 case LWM16 + 2: 766 case LWM16 + 3: 767 { 768 static const int lwm_convert[] = { 0x11, 0x12, 0x13, 0x14 }; 769 int offset = ZIMM(ctx->opcode, 0, 4); 770 771 gen_ldst_multiple(ctx, LWM32, lwm_convert[(ctx->opcode >> 4) & 0x3], 772 29, offset << 2); 773 } 774 break; 775 case SWM16 + 0: 776 case SWM16 + 1: 777 case SWM16 + 2: 778 case SWM16 + 3: 779 { 780 static const int swm_convert[] = { 0x11, 0x12, 0x13, 0x14 }; 781 int offset = ZIMM(ctx->opcode, 0, 4); 782 783 gen_ldst_multiple(ctx, SWM32, swm_convert[(ctx->opcode >> 4) & 0x3], 784 29, offset << 2); 785 } 786 break; 787 case JR16 + 0: 788 case JR16 + 1: 789 { 790 int reg = ctx->opcode & 0x1f; 791 792 gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0, 4); 793 } 794 break; 795 case JRC16 + 0: 796 case JRC16 + 1: 797 { 798 int reg = ctx->opcode & 0x1f; 799 gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0, 0); 800 /* 801 * Let normal delay slot handling in our caller take us 802 * to the branch target. 803 */ 804 } 805 break; 806 case JALR16 + 0: 807 case JALR16 + 1: 808 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 4); 809 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 810 break; 811 case JALR16S + 0: 812 case JALR16S + 1: 813 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 2); 814 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 815 break; 816 case MFHI16 + 0: 817 case MFHI16 + 1: 818 gen_HILO(ctx, OPC_MFHI, 0, uMIPS_RS5(ctx->opcode)); 819 break; 820 case MFLO16 + 0: 821 case MFLO16 + 1: 822 gen_HILO(ctx, OPC_MFLO, 0, uMIPS_RS5(ctx->opcode)); 823 break; 824 case BREAK16: 825 generate_exception_break(ctx, extract32(ctx->opcode, 0, 4)); 826 break; 827 case SDBBP16: 828 if (is_uhi(extract32(ctx->opcode, 0, 4))) { 829 ctx->base.is_jmp = DISAS_SEMIHOST; 830 } else { 831 /* 832 * XXX: not clear which exception should be raised 833 * when in debug mode... 834 */ 835 check_insn(ctx, ISA_MIPS_R1); 836 generate_exception_end(ctx, EXCP_DBp); 837 } 838 break; 839 case JRADDIUSP + 0: 840 case JRADDIUSP + 1: 841 { 842 int imm = ZIMM(ctx->opcode, 0, 5); 843 gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0); 844 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2); 845 /* 846 * Let normal delay slot handling in our caller take us 847 * to the branch target. 848 */ 849 } 850 break; 851 default: 852 gen_reserved_instruction(ctx); 853 break; 854 } 855} 856 857static inline void gen_movep(DisasContext *ctx, int enc_dest, int enc_rt, 858 int enc_rs) 859{ 860 int rd, re; 861 static const int rd_enc[] = { 5, 5, 6, 4, 4, 4, 4, 4 }; 862 static const int re_enc[] = { 6, 7, 7, 21, 22, 5, 6, 7 }; 863 static const int rs_rt_enc[] = { 0, 17, 2, 3, 16, 18, 19, 20 }; 864 865 rd = rd_enc[enc_dest]; 866 re = re_enc[enc_dest]; 867 gen_load_gpr(cpu_gpr[rd], rs_rt_enc[enc_rs]); 868 gen_load_gpr(cpu_gpr[re], rs_rt_enc[enc_rt]); 869} 870 871static void gen_pool16c_r6_insn(DisasContext *ctx) 872{ 873 int rt = mmreg((ctx->opcode >> 7) & 0x7); 874 int rs = mmreg((ctx->opcode >> 4) & 0x7); 875 876 switch (ctx->opcode & 0xf) { 877 case R6_NOT16: 878 gen_logic(ctx, OPC_NOR, rt, rs, 0); 879 break; 880 case R6_AND16: 881 gen_logic(ctx, OPC_AND, rt, rt, rs); 882 break; 883 case R6_LWM16: 884 { 885 int lwm_converted = 0x11 + extract32(ctx->opcode, 8, 2); 886 int offset = extract32(ctx->opcode, 4, 4); 887 gen_ldst_multiple(ctx, LWM32, lwm_converted, 29, offset << 2); 888 } 889 break; 890 case R6_JRC16: /* JRCADDIUSP */ 891 if ((ctx->opcode >> 4) & 1) { 892 /* JRCADDIUSP */ 893 int imm = extract32(ctx->opcode, 5, 5); 894 gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0); 895 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2); 896 } else { 897 /* JRC16 */ 898 rs = extract32(ctx->opcode, 5, 5); 899 gen_compute_branch(ctx, OPC_JR, 2, rs, 0, 0, 0); 900 } 901 break; 902 case MOVEP: 903 case MOVEP_05: 904 case MOVEP_06: 905 case MOVEP_07: 906 case MOVEP_0C: 907 case MOVEP_0D: 908 case MOVEP_0E: 909 case MOVEP_0F: 910 { 911 int enc_dest = uMIPS_RD(ctx->opcode); 912 int enc_rt = uMIPS_RS2(ctx->opcode); 913 int enc_rs = (ctx->opcode & 3) | ((ctx->opcode >> 1) & 4); 914 gen_movep(ctx, enc_dest, enc_rt, enc_rs); 915 } 916 break; 917 case R6_XOR16: 918 gen_logic(ctx, OPC_XOR, rt, rt, rs); 919 break; 920 case R6_OR16: 921 gen_logic(ctx, OPC_OR, rt, rt, rs); 922 break; 923 case R6_SWM16: 924 { 925 int swm_converted = 0x11 + extract32(ctx->opcode, 8, 2); 926 int offset = extract32(ctx->opcode, 4, 4); 927 gen_ldst_multiple(ctx, SWM32, swm_converted, 29, offset << 2); 928 } 929 break; 930 case JALRC16: /* BREAK16, SDBBP16 */ 931 switch (ctx->opcode & 0x3f) { 932 case JALRC16: 933 case JALRC16 + 0x20: 934 /* JALRC16 */ 935 gen_compute_branch(ctx, OPC_JALR, 2, (ctx->opcode >> 5) & 0x1f, 936 31, 0, 0); 937 break; 938 case R6_BREAK16: 939 /* BREAK16 */ 940 generate_exception_break(ctx, extract32(ctx->opcode, 6, 4)); 941 break; 942 case R6_SDBBP16: 943 /* SDBBP16 */ 944 if (is_uhi(extract32(ctx->opcode, 6, 4))) { 945 ctx->base.is_jmp = DISAS_SEMIHOST; 946 } else { 947 if (ctx->hflags & MIPS_HFLAG_SBRI) { 948 generate_exception(ctx, EXCP_RI); 949 } else { 950 generate_exception(ctx, EXCP_DBp); 951 } 952 } 953 break; 954 } 955 break; 956 default: 957 generate_exception(ctx, EXCP_RI); 958 break; 959 } 960} 961 962static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, 963 int base, int16_t offset) 964{ 965 TCGv t0, t1; 966 967 if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31) { 968 gen_reserved_instruction(ctx); 969 return; 970 } 971 972 t0 = tcg_temp_new(); 973 t1 = tcg_temp_new(); 974 975 gen_base_offset_addr(ctx, t0, base, offset); 976 977 switch (opc) { 978 case LWP: 979 if (rd == base) { 980 gen_reserved_instruction(ctx); 981 return; 982 } 983 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); 984 gen_store_gpr(t1, rd); 985 tcg_gen_movi_tl(t1, 4); 986 gen_op_addr_add(ctx, t0, t0, t1); 987 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); 988 gen_store_gpr(t1, rd + 1); 989 break; 990 case SWP: 991 gen_load_gpr(t1, rd); 992 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); 993 tcg_gen_movi_tl(t1, 4); 994 gen_op_addr_add(ctx, t0, t0, t1); 995 gen_load_gpr(t1, rd + 1); 996 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); 997 break; 998#ifdef TARGET_MIPS64 999 case LDP: 1000 if (rd == base) { 1001 gen_reserved_instruction(ctx); 1002 return; 1003 } 1004 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ); 1005 gen_store_gpr(t1, rd); 1006 tcg_gen_movi_tl(t1, 8); 1007 gen_op_addr_add(ctx, t0, t0, t1); 1008 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ); 1009 gen_store_gpr(t1, rd + 1); 1010 break; 1011 case SDP: 1012 gen_load_gpr(t1, rd); 1013 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ); 1014 tcg_gen_movi_tl(t1, 8); 1015 gen_op_addr_add(ctx, t0, t0, t1); 1016 gen_load_gpr(t1, rd + 1); 1017 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ); 1018 break; 1019#endif 1020 } 1021 tcg_temp_free(t0); 1022 tcg_temp_free(t1); 1023} 1024 1025static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) 1026{ 1027 int extension = (ctx->opcode >> 6) & 0x3f; 1028 int minor = (ctx->opcode >> 12) & 0xf; 1029 uint32_t mips32_op; 1030 1031 switch (extension) { 1032 case TEQ: 1033 mips32_op = OPC_TEQ; 1034 goto do_trap; 1035 case TGE: 1036 mips32_op = OPC_TGE; 1037 goto do_trap; 1038 case TGEU: 1039 mips32_op = OPC_TGEU; 1040 goto do_trap; 1041 case TLT: 1042 mips32_op = OPC_TLT; 1043 goto do_trap; 1044 case TLTU: 1045 mips32_op = OPC_TLTU; 1046 goto do_trap; 1047 case TNE: 1048 mips32_op = OPC_TNE; 1049 do_trap: 1050 gen_trap(ctx, mips32_op, rs, rt, -1, extract32(ctx->opcode, 12, 4)); 1051 break; 1052#ifndef CONFIG_USER_ONLY 1053 case MFC0: 1054 case MFC0 + 32: 1055 check_cp0_enabled(ctx); 1056 if (rt == 0) { 1057 /* Treat as NOP. */ 1058 break; 1059 } 1060 gen_mfc0(ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7); 1061 break; 1062 case MTC0: 1063 case MTC0 + 32: 1064 check_cp0_enabled(ctx); 1065 { 1066 TCGv t0 = tcg_temp_new(); 1067 1068 gen_load_gpr(t0, rt); 1069 gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7); 1070 tcg_temp_free(t0); 1071 } 1072 break; 1073#endif 1074 case 0x2a: 1075 switch (minor & 3) { 1076 case MADD_ACC: 1077 gen_muldiv(ctx, OPC_MADD, (ctx->opcode >> 14) & 3, rs, rt); 1078 break; 1079 case MADDU_ACC: 1080 gen_muldiv(ctx, OPC_MADDU, (ctx->opcode >> 14) & 3, rs, rt); 1081 break; 1082 case MSUB_ACC: 1083 gen_muldiv(ctx, OPC_MSUB, (ctx->opcode >> 14) & 3, rs, rt); 1084 break; 1085 case MSUBU_ACC: 1086 gen_muldiv(ctx, OPC_MSUBU, (ctx->opcode >> 14) & 3, rs, rt); 1087 break; 1088 default: 1089 goto pool32axf_invalid; 1090 } 1091 break; 1092 case 0x32: 1093 switch (minor & 3) { 1094 case MULT_ACC: 1095 gen_muldiv(ctx, OPC_MULT, (ctx->opcode >> 14) & 3, rs, rt); 1096 break; 1097 case MULTU_ACC: 1098 gen_muldiv(ctx, OPC_MULTU, (ctx->opcode >> 14) & 3, rs, rt); 1099 break; 1100 default: 1101 goto pool32axf_invalid; 1102 } 1103 break; 1104 case 0x2c: 1105 switch (minor) { 1106 case BITSWAP: 1107 check_insn(ctx, ISA_MIPS_R6); 1108 gen_bitswap(ctx, OPC_BITSWAP, rs, rt); 1109 break; 1110 case SEB: 1111 gen_bshfl(ctx, OPC_SEB, rs, rt); 1112 break; 1113 case SEH: 1114 gen_bshfl(ctx, OPC_SEH, rs, rt); 1115 break; 1116 case CLO: 1117 mips32_op = OPC_CLO; 1118 goto do_cl; 1119 case CLZ: 1120 mips32_op = OPC_CLZ; 1121 do_cl: 1122 check_insn(ctx, ISA_MIPS_R1); 1123 gen_cl(ctx, mips32_op, rt, rs); 1124 break; 1125 case RDHWR: 1126 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1127 gen_rdhwr(ctx, rt, rs, 0); 1128 break; 1129 case WSBH: 1130 gen_bshfl(ctx, OPC_WSBH, rs, rt); 1131 break; 1132 case MULT: 1133 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1134 mips32_op = OPC_MULT; 1135 goto do_mul; 1136 case MULTU: 1137 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1138 mips32_op = OPC_MULTU; 1139 goto do_mul; 1140 case DIV: 1141 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1142 mips32_op = OPC_DIV; 1143 goto do_div; 1144 case DIVU: 1145 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1146 mips32_op = OPC_DIVU; 1147 goto do_div; 1148 do_div: 1149 check_insn(ctx, ISA_MIPS_R1); 1150 gen_muldiv(ctx, mips32_op, 0, rs, rt); 1151 break; 1152 case MADD: 1153 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1154 mips32_op = OPC_MADD; 1155 goto do_mul; 1156 case MADDU: 1157 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1158 mips32_op = OPC_MADDU; 1159 goto do_mul; 1160 case MSUB: 1161 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1162 mips32_op = OPC_MSUB; 1163 goto do_mul; 1164 case MSUBU: 1165 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1166 mips32_op = OPC_MSUBU; 1167 do_mul: 1168 check_insn(ctx, ISA_MIPS_R1); 1169 gen_muldiv(ctx, mips32_op, 0, rs, rt); 1170 break; 1171 default: 1172 goto pool32axf_invalid; 1173 } 1174 break; 1175 case 0x34: 1176 switch (minor) { 1177 case MFC2: 1178 case MTC2: 1179 case MFHC2: 1180 case MTHC2: 1181 case CFC2: 1182 case CTC2: 1183 generate_exception_err(ctx, EXCP_CpU, 2); 1184 break; 1185 default: 1186 goto pool32axf_invalid; 1187 } 1188 break; 1189 case 0x3c: 1190 switch (minor) { 1191 case JALR: /* JALRC */ 1192 case JALR_HB: /* JALRC_HB */ 1193 if (ctx->insn_flags & ISA_MIPS_R6) { 1194 /* JALRC, JALRC_HB */ 1195 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0); 1196 } else { 1197 /* JALR, JALR_HB */ 1198 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 4); 1199 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 1200 } 1201 break; 1202 case JALRS: 1203 case JALRS_HB: 1204 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1205 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2); 1206 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 1207 break; 1208 default: 1209 goto pool32axf_invalid; 1210 } 1211 break; 1212 case 0x05: 1213 switch (minor) { 1214 case RDPGPR: 1215 check_cp0_enabled(ctx); 1216 check_insn(ctx, ISA_MIPS_R2); 1217 gen_load_srsgpr(rs, rt); 1218 break; 1219 case WRPGPR: 1220 check_cp0_enabled(ctx); 1221 check_insn(ctx, ISA_MIPS_R2); 1222 gen_store_srsgpr(rs, rt); 1223 break; 1224 default: 1225 goto pool32axf_invalid; 1226 } 1227 break; 1228#ifndef CONFIG_USER_ONLY 1229 case 0x0d: 1230 switch (minor) { 1231 case TLBP: 1232 mips32_op = OPC_TLBP; 1233 goto do_cp0; 1234 case TLBR: 1235 mips32_op = OPC_TLBR; 1236 goto do_cp0; 1237 case TLBWI: 1238 mips32_op = OPC_TLBWI; 1239 goto do_cp0; 1240 case TLBWR: 1241 mips32_op = OPC_TLBWR; 1242 goto do_cp0; 1243 case TLBINV: 1244 mips32_op = OPC_TLBINV; 1245 goto do_cp0; 1246 case TLBINVF: 1247 mips32_op = OPC_TLBINVF; 1248 goto do_cp0; 1249 case WAIT: 1250 mips32_op = OPC_WAIT; 1251 goto do_cp0; 1252 case DERET: 1253 mips32_op = OPC_DERET; 1254 goto do_cp0; 1255 case ERET: 1256 mips32_op = OPC_ERET; 1257 do_cp0: 1258 gen_cp0(env, ctx, mips32_op, rt, rs); 1259 break; 1260 default: 1261 goto pool32axf_invalid; 1262 } 1263 break; 1264 case 0x1d: 1265 switch (minor) { 1266 case DI: 1267 check_cp0_enabled(ctx); 1268 { 1269 TCGv t0 = tcg_temp_new(); 1270 1271 save_cpu_state(ctx, 1); 1272 gen_helper_di(t0, cpu_env); 1273 gen_store_gpr(t0, rs); 1274 /* 1275 * Stop translation as we may have switched the execution 1276 * mode. 1277 */ 1278 ctx->base.is_jmp = DISAS_STOP; 1279 tcg_temp_free(t0); 1280 } 1281 break; 1282 case EI: 1283 check_cp0_enabled(ctx); 1284 { 1285 TCGv t0 = tcg_temp_new(); 1286 1287 save_cpu_state(ctx, 1); 1288 gen_helper_ei(t0, cpu_env); 1289 gen_store_gpr(t0, rs); 1290 /* 1291 * DISAS_STOP isn't sufficient, we need to ensure we break out 1292 * of translated code to check for pending interrupts. 1293 */ 1294 gen_save_pc(ctx->base.pc_next + 4); 1295 ctx->base.is_jmp = DISAS_EXIT; 1296 tcg_temp_free(t0); 1297 } 1298 break; 1299 default: 1300 goto pool32axf_invalid; 1301 } 1302 break; 1303#endif 1304 case 0x2d: 1305 switch (minor) { 1306 case SYNC: 1307 gen_sync(extract32(ctx->opcode, 16, 5)); 1308 break; 1309 case SYSCALL: 1310 generate_exception_end(ctx, EXCP_SYSCALL); 1311 break; 1312 case SDBBP: 1313 if (is_uhi(extract32(ctx->opcode, 16, 10))) { 1314 ctx->base.is_jmp = DISAS_SEMIHOST; 1315 } else { 1316 check_insn(ctx, ISA_MIPS_R1); 1317 if (ctx->hflags & MIPS_HFLAG_SBRI) { 1318 gen_reserved_instruction(ctx); 1319 } else { 1320 generate_exception_end(ctx, EXCP_DBp); 1321 } 1322 } 1323 break; 1324 default: 1325 goto pool32axf_invalid; 1326 } 1327 break; 1328 case 0x01: 1329 switch (minor & 3) { 1330 case MFHI_ACC: 1331 gen_HILO(ctx, OPC_MFHI, minor >> 2, rs); 1332 break; 1333 case MFLO_ACC: 1334 gen_HILO(ctx, OPC_MFLO, minor >> 2, rs); 1335 break; 1336 case MTHI_ACC: 1337 gen_HILO(ctx, OPC_MTHI, minor >> 2, rs); 1338 break; 1339 case MTLO_ACC: 1340 gen_HILO(ctx, OPC_MTLO, minor >> 2, rs); 1341 break; 1342 default: 1343 goto pool32axf_invalid; 1344 } 1345 break; 1346 case 0x35: 1347 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1348 switch (minor) { 1349 case MFHI32: 1350 gen_HILO(ctx, OPC_MFHI, 0, rs); 1351 break; 1352 case MFLO32: 1353 gen_HILO(ctx, OPC_MFLO, 0, rs); 1354 break; 1355 case MTHI32: 1356 gen_HILO(ctx, OPC_MTHI, 0, rs); 1357 break; 1358 case MTLO32: 1359 gen_HILO(ctx, OPC_MTLO, 0, rs); 1360 break; 1361 default: 1362 goto pool32axf_invalid; 1363 } 1364 break; 1365 default: 1366 pool32axf_invalid: 1367 MIPS_INVAL("pool32axf"); 1368 gen_reserved_instruction(ctx); 1369 break; 1370 } 1371} 1372 1373static void gen_pool32fxf(DisasContext *ctx, int rt, int rs) 1374{ 1375 int extension = (ctx->opcode >> 6) & 0x3ff; 1376 uint32_t mips32_op; 1377 1378#define FLOAT_1BIT_FMT(opc, fmt) ((fmt << 8) | opc) 1379#define FLOAT_2BIT_FMT(opc, fmt) ((fmt << 7) | opc) 1380#define COND_FLOAT_MOV(opc, cond) ((cond << 7) | opc) 1381 1382 switch (extension) { 1383 case FLOAT_1BIT_FMT(CFC1, 0): 1384 mips32_op = OPC_CFC1; 1385 goto do_cp1; 1386 case FLOAT_1BIT_FMT(CTC1, 0): 1387 mips32_op = OPC_CTC1; 1388 goto do_cp1; 1389 case FLOAT_1BIT_FMT(MFC1, 0): 1390 mips32_op = OPC_MFC1; 1391 goto do_cp1; 1392 case FLOAT_1BIT_FMT(MTC1, 0): 1393 mips32_op = OPC_MTC1; 1394 goto do_cp1; 1395 case FLOAT_1BIT_FMT(MFHC1, 0): 1396 mips32_op = OPC_MFHC1; 1397 goto do_cp1; 1398 case FLOAT_1BIT_FMT(MTHC1, 0): 1399 mips32_op = OPC_MTHC1; 1400 do_cp1: 1401 gen_cp1(ctx, mips32_op, rt, rs); 1402 break; 1403 1404 /* Reciprocal square root */ 1405 case FLOAT_1BIT_FMT(RSQRT_FMT, FMT_SD_S): 1406 mips32_op = OPC_RSQRT_S; 1407 goto do_unaryfp; 1408 case FLOAT_1BIT_FMT(RSQRT_FMT, FMT_SD_D): 1409 mips32_op = OPC_RSQRT_D; 1410 goto do_unaryfp; 1411 1412 /* Square root */ 1413 case FLOAT_1BIT_FMT(SQRT_FMT, FMT_SD_S): 1414 mips32_op = OPC_SQRT_S; 1415 goto do_unaryfp; 1416 case FLOAT_1BIT_FMT(SQRT_FMT, FMT_SD_D): 1417 mips32_op = OPC_SQRT_D; 1418 goto do_unaryfp; 1419 1420 /* Reciprocal */ 1421 case FLOAT_1BIT_FMT(RECIP_FMT, FMT_SD_S): 1422 mips32_op = OPC_RECIP_S; 1423 goto do_unaryfp; 1424 case FLOAT_1BIT_FMT(RECIP_FMT, FMT_SD_D): 1425 mips32_op = OPC_RECIP_D; 1426 goto do_unaryfp; 1427 1428 /* Floor */ 1429 case FLOAT_1BIT_FMT(FLOOR_L, FMT_SD_S): 1430 mips32_op = OPC_FLOOR_L_S; 1431 goto do_unaryfp; 1432 case FLOAT_1BIT_FMT(FLOOR_L, FMT_SD_D): 1433 mips32_op = OPC_FLOOR_L_D; 1434 goto do_unaryfp; 1435 case FLOAT_1BIT_FMT(FLOOR_W, FMT_SD_S): 1436 mips32_op = OPC_FLOOR_W_S; 1437 goto do_unaryfp; 1438 case FLOAT_1BIT_FMT(FLOOR_W, FMT_SD_D): 1439 mips32_op = OPC_FLOOR_W_D; 1440 goto do_unaryfp; 1441 1442 /* Ceiling */ 1443 case FLOAT_1BIT_FMT(CEIL_L, FMT_SD_S): 1444 mips32_op = OPC_CEIL_L_S; 1445 goto do_unaryfp; 1446 case FLOAT_1BIT_FMT(CEIL_L, FMT_SD_D): 1447 mips32_op = OPC_CEIL_L_D; 1448 goto do_unaryfp; 1449 case FLOAT_1BIT_FMT(CEIL_W, FMT_SD_S): 1450 mips32_op = OPC_CEIL_W_S; 1451 goto do_unaryfp; 1452 case FLOAT_1BIT_FMT(CEIL_W, FMT_SD_D): 1453 mips32_op = OPC_CEIL_W_D; 1454 goto do_unaryfp; 1455 1456 /* Truncation */ 1457 case FLOAT_1BIT_FMT(TRUNC_L, FMT_SD_S): 1458 mips32_op = OPC_TRUNC_L_S; 1459 goto do_unaryfp; 1460 case FLOAT_1BIT_FMT(TRUNC_L, FMT_SD_D): 1461 mips32_op = OPC_TRUNC_L_D; 1462 goto do_unaryfp; 1463 case FLOAT_1BIT_FMT(TRUNC_W, FMT_SD_S): 1464 mips32_op = OPC_TRUNC_W_S; 1465 goto do_unaryfp; 1466 case FLOAT_1BIT_FMT(TRUNC_W, FMT_SD_D): 1467 mips32_op = OPC_TRUNC_W_D; 1468 goto do_unaryfp; 1469 1470 /* Round */ 1471 case FLOAT_1BIT_FMT(ROUND_L, FMT_SD_S): 1472 mips32_op = OPC_ROUND_L_S; 1473 goto do_unaryfp; 1474 case FLOAT_1BIT_FMT(ROUND_L, FMT_SD_D): 1475 mips32_op = OPC_ROUND_L_D; 1476 goto do_unaryfp; 1477 case FLOAT_1BIT_FMT(ROUND_W, FMT_SD_S): 1478 mips32_op = OPC_ROUND_W_S; 1479 goto do_unaryfp; 1480 case FLOAT_1BIT_FMT(ROUND_W, FMT_SD_D): 1481 mips32_op = OPC_ROUND_W_D; 1482 goto do_unaryfp; 1483 1484 /* Integer to floating-point conversion */ 1485 case FLOAT_1BIT_FMT(CVT_L, FMT_SD_S): 1486 mips32_op = OPC_CVT_L_S; 1487 goto do_unaryfp; 1488 case FLOAT_1BIT_FMT(CVT_L, FMT_SD_D): 1489 mips32_op = OPC_CVT_L_D; 1490 goto do_unaryfp; 1491 case FLOAT_1BIT_FMT(CVT_W, FMT_SD_S): 1492 mips32_op = OPC_CVT_W_S; 1493 goto do_unaryfp; 1494 case FLOAT_1BIT_FMT(CVT_W, FMT_SD_D): 1495 mips32_op = OPC_CVT_W_D; 1496 goto do_unaryfp; 1497 1498 /* Paired-foo conversions */ 1499 case FLOAT_1BIT_FMT(CVT_S_PL, 0): 1500 mips32_op = OPC_CVT_S_PL; 1501 goto do_unaryfp; 1502 case FLOAT_1BIT_FMT(CVT_S_PU, 0): 1503 mips32_op = OPC_CVT_S_PU; 1504 goto do_unaryfp; 1505 case FLOAT_1BIT_FMT(CVT_PW_PS, 0): 1506 mips32_op = OPC_CVT_PW_PS; 1507 goto do_unaryfp; 1508 case FLOAT_1BIT_FMT(CVT_PS_PW, 0): 1509 mips32_op = OPC_CVT_PS_PW; 1510 goto do_unaryfp; 1511 1512 /* Floating-point moves */ 1513 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_S): 1514 mips32_op = OPC_MOV_S; 1515 goto do_unaryfp; 1516 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_D): 1517 mips32_op = OPC_MOV_D; 1518 goto do_unaryfp; 1519 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_PS): 1520 mips32_op = OPC_MOV_PS; 1521 goto do_unaryfp; 1522 1523 /* Absolute value */ 1524 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_S): 1525 mips32_op = OPC_ABS_S; 1526 goto do_unaryfp; 1527 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_D): 1528 mips32_op = OPC_ABS_D; 1529 goto do_unaryfp; 1530 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_PS): 1531 mips32_op = OPC_ABS_PS; 1532 goto do_unaryfp; 1533 1534 /* Negation */ 1535 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_S): 1536 mips32_op = OPC_NEG_S; 1537 goto do_unaryfp; 1538 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_D): 1539 mips32_op = OPC_NEG_D; 1540 goto do_unaryfp; 1541 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_PS): 1542 mips32_op = OPC_NEG_PS; 1543 goto do_unaryfp; 1544 1545 /* Reciprocal square root step */ 1546 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_S): 1547 mips32_op = OPC_RSQRT1_S; 1548 goto do_unaryfp; 1549 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_D): 1550 mips32_op = OPC_RSQRT1_D; 1551 goto do_unaryfp; 1552 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_PS): 1553 mips32_op = OPC_RSQRT1_PS; 1554 goto do_unaryfp; 1555 1556 /* Reciprocal step */ 1557 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_S): 1558 mips32_op = OPC_RECIP1_S; 1559 goto do_unaryfp; 1560 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_D): 1561 mips32_op = OPC_RECIP1_S; 1562 goto do_unaryfp; 1563 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_PS): 1564 mips32_op = OPC_RECIP1_PS; 1565 goto do_unaryfp; 1566 1567 /* Conversions from double */ 1568 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_S): 1569 mips32_op = OPC_CVT_D_S; 1570 goto do_unaryfp; 1571 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_W): 1572 mips32_op = OPC_CVT_D_W; 1573 goto do_unaryfp; 1574 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_L): 1575 mips32_op = OPC_CVT_D_L; 1576 goto do_unaryfp; 1577 1578 /* Conversions from single */ 1579 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_D): 1580 mips32_op = OPC_CVT_S_D; 1581 goto do_unaryfp; 1582 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_W): 1583 mips32_op = OPC_CVT_S_W; 1584 goto do_unaryfp; 1585 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_L): 1586 mips32_op = OPC_CVT_S_L; 1587 do_unaryfp: 1588 gen_farith(ctx, mips32_op, -1, rs, rt, 0); 1589 break; 1590 1591 /* Conditional moves on floating-point codes */ 1592 case COND_FLOAT_MOV(MOVT, 0): 1593 case COND_FLOAT_MOV(MOVT, 1): 1594 case COND_FLOAT_MOV(MOVT, 2): 1595 case COND_FLOAT_MOV(MOVT, 3): 1596 case COND_FLOAT_MOV(MOVT, 4): 1597 case COND_FLOAT_MOV(MOVT, 5): 1598 case COND_FLOAT_MOV(MOVT, 6): 1599 case COND_FLOAT_MOV(MOVT, 7): 1600 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1601 gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 1); 1602 break; 1603 case COND_FLOAT_MOV(MOVF, 0): 1604 case COND_FLOAT_MOV(MOVF, 1): 1605 case COND_FLOAT_MOV(MOVF, 2): 1606 case COND_FLOAT_MOV(MOVF, 3): 1607 case COND_FLOAT_MOV(MOVF, 4): 1608 case COND_FLOAT_MOV(MOVF, 5): 1609 case COND_FLOAT_MOV(MOVF, 6): 1610 case COND_FLOAT_MOV(MOVF, 7): 1611 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1612 gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 0); 1613 break; 1614 default: 1615 MIPS_INVAL("pool32fxf"); 1616 gen_reserved_instruction(ctx); 1617 break; 1618 } 1619} 1620 1621static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) 1622{ 1623 int32_t offset; 1624 uint16_t insn; 1625 int rt, rs, rd, rr; 1626 int16_t imm; 1627 uint32_t op, minor, minor2, mips32_op; 1628 uint32_t cond, fmt, cc; 1629 1630 insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); 1631 ctx->opcode = (ctx->opcode << 16) | insn; 1632 1633 rt = (ctx->opcode >> 21) & 0x1f; 1634 rs = (ctx->opcode >> 16) & 0x1f; 1635 rd = (ctx->opcode >> 11) & 0x1f; 1636 rr = (ctx->opcode >> 6) & 0x1f; 1637 imm = (int16_t) ctx->opcode; 1638 1639 op = (ctx->opcode >> 26) & 0x3f; 1640 switch (op) { 1641 case POOL32A: 1642 minor = ctx->opcode & 0x3f; 1643 switch (minor) { 1644 case 0x00: 1645 minor = (ctx->opcode >> 6) & 0xf; 1646 switch (minor) { 1647 case SLL32: 1648 mips32_op = OPC_SLL; 1649 goto do_shifti; 1650 case SRA: 1651 mips32_op = OPC_SRA; 1652 goto do_shifti; 1653 case SRL32: 1654 mips32_op = OPC_SRL; 1655 goto do_shifti; 1656 case ROTR: 1657 mips32_op = OPC_ROTR; 1658 do_shifti: 1659 gen_shift_imm(ctx, mips32_op, rt, rs, rd); 1660 break; 1661 case SELEQZ: 1662 check_insn(ctx, ISA_MIPS_R6); 1663 gen_cond_move(ctx, OPC_SELEQZ, rd, rs, rt); 1664 break; 1665 case SELNEZ: 1666 check_insn(ctx, ISA_MIPS_R6); 1667 gen_cond_move(ctx, OPC_SELNEZ, rd, rs, rt); 1668 break; 1669 case R6_RDHWR: 1670 check_insn(ctx, ISA_MIPS_R6); 1671 gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3)); 1672 break; 1673 default: 1674 goto pool32a_invalid; 1675 } 1676 break; 1677 case 0x10: 1678 minor = (ctx->opcode >> 6) & 0xf; 1679 switch (minor) { 1680 /* Arithmetic */ 1681 case ADD: 1682 mips32_op = OPC_ADD; 1683 goto do_arith; 1684 case ADDU32: 1685 mips32_op = OPC_ADDU; 1686 goto do_arith; 1687 case SUB: 1688 mips32_op = OPC_SUB; 1689 goto do_arith; 1690 case SUBU32: 1691 mips32_op = OPC_SUBU; 1692 goto do_arith; 1693 case MUL: 1694 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1695 mips32_op = OPC_MUL; 1696 do_arith: 1697 gen_arith(ctx, mips32_op, rd, rs, rt); 1698 break; 1699 /* Shifts */ 1700 case SLLV: 1701 mips32_op = OPC_SLLV; 1702 goto do_shift; 1703 case SRLV: 1704 mips32_op = OPC_SRLV; 1705 goto do_shift; 1706 case SRAV: 1707 mips32_op = OPC_SRAV; 1708 goto do_shift; 1709 case ROTRV: 1710 mips32_op = OPC_ROTRV; 1711 do_shift: 1712 gen_shift(ctx, mips32_op, rd, rs, rt); 1713 break; 1714 /* Logical operations */ 1715 case AND: 1716 mips32_op = OPC_AND; 1717 goto do_logic; 1718 case OR32: 1719 mips32_op = OPC_OR; 1720 goto do_logic; 1721 case NOR: 1722 mips32_op = OPC_NOR; 1723 goto do_logic; 1724 case XOR32: 1725 mips32_op = OPC_XOR; 1726 do_logic: 1727 gen_logic(ctx, mips32_op, rd, rs, rt); 1728 break; 1729 /* Set less than */ 1730 case SLT: 1731 mips32_op = OPC_SLT; 1732 goto do_slt; 1733 case SLTU: 1734 mips32_op = OPC_SLTU; 1735 do_slt: 1736 gen_slt(ctx, mips32_op, rd, rs, rt); 1737 break; 1738 default: 1739 goto pool32a_invalid; 1740 } 1741 break; 1742 case 0x18: 1743 minor = (ctx->opcode >> 6) & 0xf; 1744 switch (minor) { 1745 /* Conditional moves */ 1746 case MOVN: /* MUL */ 1747 if (ctx->insn_flags & ISA_MIPS_R6) { 1748 /* MUL */ 1749 gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt); 1750 } else { 1751 /* MOVN */ 1752 gen_cond_move(ctx, OPC_MOVN, rd, rs, rt); 1753 } 1754 break; 1755 case MOVZ: /* MUH */ 1756 if (ctx->insn_flags & ISA_MIPS_R6) { 1757 /* MUH */ 1758 gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt); 1759 } else { 1760 /* MOVZ */ 1761 gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt); 1762 } 1763 break; 1764 case MULU: 1765 check_insn(ctx, ISA_MIPS_R6); 1766 gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt); 1767 break; 1768 case MUHU: 1769 check_insn(ctx, ISA_MIPS_R6); 1770 gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt); 1771 break; 1772 case LWXS: /* DIV */ 1773 if (ctx->insn_flags & ISA_MIPS_R6) { 1774 /* DIV */ 1775 gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt); 1776 } else { 1777 /* LWXS */ 1778 gen_ldxs(ctx, rs, rt, rd); 1779 } 1780 break; 1781 case MOD: 1782 check_insn(ctx, ISA_MIPS_R6); 1783 gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt); 1784 break; 1785 case R6_DIVU: 1786 check_insn(ctx, ISA_MIPS_R6); 1787 gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt); 1788 break; 1789 case MODU: 1790 check_insn(ctx, ISA_MIPS_R6); 1791 gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt); 1792 break; 1793 default: 1794 goto pool32a_invalid; 1795 } 1796 break; 1797 case INS: 1798 gen_bitops(ctx, OPC_INS, rt, rs, rr, rd); 1799 return; 1800 case LSA: 1801 check_insn(ctx, ISA_MIPS_R6); 1802 gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2)); 1803 break; 1804 case ALIGN: 1805 check_insn(ctx, ISA_MIPS_R6); 1806 gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2)); 1807 break; 1808 case EXT: 1809 gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd); 1810 return; 1811 case POOL32AXF: 1812 gen_pool32axf(env, ctx, rt, rs); 1813 break; 1814 case BREAK32: 1815 generate_exception_break(ctx, extract32(ctx->opcode, 6, 20)); 1816 break; 1817 case SIGRIE: 1818 check_insn(ctx, ISA_MIPS_R6); 1819 gen_reserved_instruction(ctx); 1820 break; 1821 default: 1822 pool32a_invalid: 1823 MIPS_INVAL("pool32a"); 1824 gen_reserved_instruction(ctx); 1825 break; 1826 } 1827 break; 1828 case POOL32B: 1829 minor = (ctx->opcode >> 12) & 0xf; 1830 switch (minor) { 1831 case CACHE: 1832 check_cp0_enabled(ctx); 1833 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 1834 gen_cache_operation(ctx, rt, rs, imm); 1835 } 1836 break; 1837 case LWC2: 1838 case SWC2: 1839 /* COP2: Not implemented. */ 1840 generate_exception_err(ctx, EXCP_CpU, 2); 1841 break; 1842#ifdef TARGET_MIPS64 1843 case LDP: 1844 case SDP: 1845 check_insn(ctx, ISA_MIPS3); 1846 check_mips_64(ctx); 1847#endif 1848 /* fall through */ 1849 case LWP: 1850 case SWP: 1851 gen_ldst_pair(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12)); 1852 break; 1853#ifdef TARGET_MIPS64 1854 case LDM: 1855 case SDM: 1856 check_insn(ctx, ISA_MIPS3); 1857 check_mips_64(ctx); 1858#endif 1859 /* fall through */ 1860 case LWM32: 1861 case SWM32: 1862 gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12)); 1863 break; 1864 default: 1865 MIPS_INVAL("pool32b"); 1866 gen_reserved_instruction(ctx); 1867 break; 1868 } 1869 break; 1870 case POOL32F: 1871 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { 1872 minor = ctx->opcode & 0x3f; 1873 check_cp1_enabled(ctx); 1874 switch (minor) { 1875 case ALNV_PS: 1876 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1877 mips32_op = OPC_ALNV_PS; 1878 goto do_madd; 1879 case MADD_S: 1880 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1881 mips32_op = OPC_MADD_S; 1882 goto do_madd; 1883 case MADD_D: 1884 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1885 mips32_op = OPC_MADD_D; 1886 goto do_madd; 1887 case MADD_PS: 1888 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1889 mips32_op = OPC_MADD_PS; 1890 goto do_madd; 1891 case MSUB_S: 1892 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1893 mips32_op = OPC_MSUB_S; 1894 goto do_madd; 1895 case MSUB_D: 1896 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1897 mips32_op = OPC_MSUB_D; 1898 goto do_madd; 1899 case MSUB_PS: 1900 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1901 mips32_op = OPC_MSUB_PS; 1902 goto do_madd; 1903 case NMADD_S: 1904 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1905 mips32_op = OPC_NMADD_S; 1906 goto do_madd; 1907 case NMADD_D: 1908 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1909 mips32_op = OPC_NMADD_D; 1910 goto do_madd; 1911 case NMADD_PS: 1912 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1913 mips32_op = OPC_NMADD_PS; 1914 goto do_madd; 1915 case NMSUB_S: 1916 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1917 mips32_op = OPC_NMSUB_S; 1918 goto do_madd; 1919 case NMSUB_D: 1920 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1921 mips32_op = OPC_NMSUB_D; 1922 goto do_madd; 1923 case NMSUB_PS: 1924 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1925 mips32_op = OPC_NMSUB_PS; 1926 do_madd: 1927 gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt); 1928 break; 1929 case CABS_COND_FMT: 1930 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1931 cond = (ctx->opcode >> 6) & 0xf; 1932 cc = (ctx->opcode >> 13) & 0x7; 1933 fmt = (ctx->opcode >> 10) & 0x3; 1934 switch (fmt) { 1935 case 0x0: 1936 gen_cmpabs_s(ctx, cond, rt, rs, cc); 1937 break; 1938 case 0x1: 1939 gen_cmpabs_d(ctx, cond, rt, rs, cc); 1940 break; 1941 case 0x2: 1942 gen_cmpabs_ps(ctx, cond, rt, rs, cc); 1943 break; 1944 default: 1945 goto pool32f_invalid; 1946 } 1947 break; 1948 case C_COND_FMT: 1949 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1950 cond = (ctx->opcode >> 6) & 0xf; 1951 cc = (ctx->opcode >> 13) & 0x7; 1952 fmt = (ctx->opcode >> 10) & 0x3; 1953 switch (fmt) { 1954 case 0x0: 1955 gen_cmp_s(ctx, cond, rt, rs, cc); 1956 break; 1957 case 0x1: 1958 gen_cmp_d(ctx, cond, rt, rs, cc); 1959 break; 1960 case 0x2: 1961 gen_cmp_ps(ctx, cond, rt, rs, cc); 1962 break; 1963 default: 1964 goto pool32f_invalid; 1965 } 1966 break; 1967 case CMP_CONDN_S: 1968 check_insn(ctx, ISA_MIPS_R6); 1969 gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); 1970 break; 1971 case CMP_CONDN_D: 1972 check_insn(ctx, ISA_MIPS_R6); 1973 gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); 1974 break; 1975 case POOL32FXF: 1976 gen_pool32fxf(ctx, rt, rs); 1977 break; 1978 case 0x00: 1979 /* PLL foo */ 1980 switch ((ctx->opcode >> 6) & 0x7) { 1981 case PLL_PS: 1982 mips32_op = OPC_PLL_PS; 1983 goto do_ps; 1984 case PLU_PS: 1985 mips32_op = OPC_PLU_PS; 1986 goto do_ps; 1987 case PUL_PS: 1988 mips32_op = OPC_PUL_PS; 1989 goto do_ps; 1990 case PUU_PS: 1991 mips32_op = OPC_PUU_PS; 1992 goto do_ps; 1993 case CVT_PS_S: 1994 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1995 mips32_op = OPC_CVT_PS_S; 1996 do_ps: 1997 gen_farith(ctx, mips32_op, rt, rs, rd, 0); 1998 break; 1999 default: 2000 goto pool32f_invalid; 2001 } 2002 break; 2003 case MIN_FMT: 2004 check_insn(ctx, ISA_MIPS_R6); 2005 switch ((ctx->opcode >> 9) & 0x3) { 2006 case FMT_SDPS_S: 2007 gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0); 2008 break; 2009 case FMT_SDPS_D: 2010 gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0); 2011 break; 2012 default: 2013 goto pool32f_invalid; 2014 } 2015 break; 2016 case 0x08: 2017 /* [LS][WDU]XC1 */ 2018 switch ((ctx->opcode >> 6) & 0x7) { 2019 case LWXC1: 2020 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2021 mips32_op = OPC_LWXC1; 2022 goto do_ldst_cp1; 2023 case SWXC1: 2024 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2025 mips32_op = OPC_SWXC1; 2026 goto do_ldst_cp1; 2027 case LDXC1: 2028 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2029 mips32_op = OPC_LDXC1; 2030 goto do_ldst_cp1; 2031 case SDXC1: 2032 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2033 mips32_op = OPC_SDXC1; 2034 goto do_ldst_cp1; 2035 case LUXC1: 2036 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2037 mips32_op = OPC_LUXC1; 2038 goto do_ldst_cp1; 2039 case SUXC1: 2040 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2041 mips32_op = OPC_SUXC1; 2042 do_ldst_cp1: 2043 gen_flt3_ldst(ctx, mips32_op, rd, rd, rt, rs); 2044 break; 2045 default: 2046 goto pool32f_invalid; 2047 } 2048 break; 2049 case MAX_FMT: 2050 check_insn(ctx, ISA_MIPS_R6); 2051 switch ((ctx->opcode >> 9) & 0x3) { 2052 case FMT_SDPS_S: 2053 gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0); 2054 break; 2055 case FMT_SDPS_D: 2056 gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0); 2057 break; 2058 default: 2059 goto pool32f_invalid; 2060 } 2061 break; 2062 case 0x18: 2063 /* 3D insns */ 2064 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2065 fmt = (ctx->opcode >> 9) & 0x3; 2066 switch ((ctx->opcode >> 6) & 0x7) { 2067 case RSQRT2_FMT: 2068 switch (fmt) { 2069 case FMT_SDPS_S: 2070 mips32_op = OPC_RSQRT2_S; 2071 goto do_3d; 2072 case FMT_SDPS_D: 2073 mips32_op = OPC_RSQRT2_D; 2074 goto do_3d; 2075 case FMT_SDPS_PS: 2076 mips32_op = OPC_RSQRT2_PS; 2077 goto do_3d; 2078 default: 2079 goto pool32f_invalid; 2080 } 2081 break; 2082 case RECIP2_FMT: 2083 switch (fmt) { 2084 case FMT_SDPS_S: 2085 mips32_op = OPC_RECIP2_S; 2086 goto do_3d; 2087 case FMT_SDPS_D: 2088 mips32_op = OPC_RECIP2_D; 2089 goto do_3d; 2090 case FMT_SDPS_PS: 2091 mips32_op = OPC_RECIP2_PS; 2092 goto do_3d; 2093 default: 2094 goto pool32f_invalid; 2095 } 2096 break; 2097 case ADDR_PS: 2098 mips32_op = OPC_ADDR_PS; 2099 goto do_3d; 2100 case MULR_PS: 2101 mips32_op = OPC_MULR_PS; 2102 do_3d: 2103 gen_farith(ctx, mips32_op, rt, rs, rd, 0); 2104 break; 2105 default: 2106 goto pool32f_invalid; 2107 } 2108 break; 2109 case 0x20: 2110 /* MOV[FT].fmt, PREFX, RINT.fmt, CLASS.fmt*/ 2111 cc = (ctx->opcode >> 13) & 0x7; 2112 fmt = (ctx->opcode >> 9) & 0x3; 2113 switch ((ctx->opcode >> 6) & 0x7) { 2114 case MOVF_FMT: /* RINT_FMT */ 2115 if (ctx->insn_flags & ISA_MIPS_R6) { 2116 /* RINT_FMT */ 2117 switch (fmt) { 2118 case FMT_SDPS_S: 2119 gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0); 2120 break; 2121 case FMT_SDPS_D: 2122 gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0); 2123 break; 2124 default: 2125 goto pool32f_invalid; 2126 } 2127 } else { 2128 /* MOVF_FMT */ 2129 switch (fmt) { 2130 case FMT_SDPS_S: 2131 gen_movcf_s(ctx, rs, rt, cc, 0); 2132 break; 2133 case FMT_SDPS_D: 2134 gen_movcf_d(ctx, rs, rt, cc, 0); 2135 break; 2136 case FMT_SDPS_PS: 2137 check_ps(ctx); 2138 gen_movcf_ps(ctx, rs, rt, cc, 0); 2139 break; 2140 default: 2141 goto pool32f_invalid; 2142 } 2143 } 2144 break; 2145 case MOVT_FMT: /* CLASS_FMT */ 2146 if (ctx->insn_flags & ISA_MIPS_R6) { 2147 /* CLASS_FMT */ 2148 switch (fmt) { 2149 case FMT_SDPS_S: 2150 gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0); 2151 break; 2152 case FMT_SDPS_D: 2153 gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0); 2154 break; 2155 default: 2156 goto pool32f_invalid; 2157 } 2158 } else { 2159 /* MOVT_FMT */ 2160 switch (fmt) { 2161 case FMT_SDPS_S: 2162 gen_movcf_s(ctx, rs, rt, cc, 1); 2163 break; 2164 case FMT_SDPS_D: 2165 gen_movcf_d(ctx, rs, rt, cc, 1); 2166 break; 2167 case FMT_SDPS_PS: 2168 check_ps(ctx); 2169 gen_movcf_ps(ctx, rs, rt, cc, 1); 2170 break; 2171 default: 2172 goto pool32f_invalid; 2173 } 2174 } 2175 break; 2176 case PREFX: 2177 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2178 break; 2179 default: 2180 goto pool32f_invalid; 2181 } 2182 break; 2183#define FINSN_3ARG_SDPS(prfx) \ 2184 switch ((ctx->opcode >> 8) & 0x3) { \ 2185 case FMT_SDPS_S: \ 2186 mips32_op = OPC_##prfx##_S; \ 2187 goto do_fpop; \ 2188 case FMT_SDPS_D: \ 2189 mips32_op = OPC_##prfx##_D; \ 2190 goto do_fpop; \ 2191 case FMT_SDPS_PS: \ 2192 check_ps(ctx); \ 2193 mips32_op = OPC_##prfx##_PS; \ 2194 goto do_fpop; \ 2195 default: \ 2196 goto pool32f_invalid; \ 2197 } 2198 case MINA_FMT: 2199 check_insn(ctx, ISA_MIPS_R6); 2200 switch ((ctx->opcode >> 9) & 0x3) { 2201 case FMT_SDPS_S: 2202 gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0); 2203 break; 2204 case FMT_SDPS_D: 2205 gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0); 2206 break; 2207 default: 2208 goto pool32f_invalid; 2209 } 2210 break; 2211 case MAXA_FMT: 2212 check_insn(ctx, ISA_MIPS_R6); 2213 switch ((ctx->opcode >> 9) & 0x3) { 2214 case FMT_SDPS_S: 2215 gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0); 2216 break; 2217 case FMT_SDPS_D: 2218 gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0); 2219 break; 2220 default: 2221 goto pool32f_invalid; 2222 } 2223 break; 2224 case 0x30: 2225 /* regular FP ops */ 2226 switch ((ctx->opcode >> 6) & 0x3) { 2227 case ADD_FMT: 2228 FINSN_3ARG_SDPS(ADD); 2229 break; 2230 case SUB_FMT: 2231 FINSN_3ARG_SDPS(SUB); 2232 break; 2233 case MUL_FMT: 2234 FINSN_3ARG_SDPS(MUL); 2235 break; 2236 case DIV_FMT: 2237 fmt = (ctx->opcode >> 8) & 0x3; 2238 if (fmt == 1) { 2239 mips32_op = OPC_DIV_D; 2240 } else if (fmt == 0) { 2241 mips32_op = OPC_DIV_S; 2242 } else { 2243 goto pool32f_invalid; 2244 } 2245 goto do_fpop; 2246 default: 2247 goto pool32f_invalid; 2248 } 2249 break; 2250 case 0x38: 2251 /* cmovs */ 2252 switch ((ctx->opcode >> 6) & 0x7) { 2253 case MOVN_FMT: /* SELEQZ_FMT */ 2254 if (ctx->insn_flags & ISA_MIPS_R6) { 2255 /* SELEQZ_FMT */ 2256 switch ((ctx->opcode >> 9) & 0x3) { 2257 case FMT_SDPS_S: 2258 gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs); 2259 break; 2260 case FMT_SDPS_D: 2261 gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs); 2262 break; 2263 default: 2264 goto pool32f_invalid; 2265 } 2266 } else { 2267 /* MOVN_FMT */ 2268 FINSN_3ARG_SDPS(MOVN); 2269 } 2270 break; 2271 case MOVN_FMT_04: 2272 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2273 FINSN_3ARG_SDPS(MOVN); 2274 break; 2275 case MOVZ_FMT: /* SELNEZ_FMT */ 2276 if (ctx->insn_flags & ISA_MIPS_R6) { 2277 /* SELNEZ_FMT */ 2278 switch ((ctx->opcode >> 9) & 0x3) { 2279 case FMT_SDPS_S: 2280 gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs); 2281 break; 2282 case FMT_SDPS_D: 2283 gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs); 2284 break; 2285 default: 2286 goto pool32f_invalid; 2287 } 2288 } else { 2289 /* MOVZ_FMT */ 2290 FINSN_3ARG_SDPS(MOVZ); 2291 } 2292 break; 2293 case MOVZ_FMT_05: 2294 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2295 FINSN_3ARG_SDPS(MOVZ); 2296 break; 2297 case SEL_FMT: 2298 check_insn(ctx, ISA_MIPS_R6); 2299 switch ((ctx->opcode >> 9) & 0x3) { 2300 case FMT_SDPS_S: 2301 gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs); 2302 break; 2303 case FMT_SDPS_D: 2304 gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs); 2305 break; 2306 default: 2307 goto pool32f_invalid; 2308 } 2309 break; 2310 case MADDF_FMT: 2311 check_insn(ctx, ISA_MIPS_R6); 2312 switch ((ctx->opcode >> 9) & 0x3) { 2313 case FMT_SDPS_S: 2314 mips32_op = OPC_MADDF_S; 2315 goto do_fpop; 2316 case FMT_SDPS_D: 2317 mips32_op = OPC_MADDF_D; 2318 goto do_fpop; 2319 default: 2320 goto pool32f_invalid; 2321 } 2322 break; 2323 case MSUBF_FMT: 2324 check_insn(ctx, ISA_MIPS_R6); 2325 switch ((ctx->opcode >> 9) & 0x3) { 2326 case FMT_SDPS_S: 2327 mips32_op = OPC_MSUBF_S; 2328 goto do_fpop; 2329 case FMT_SDPS_D: 2330 mips32_op = OPC_MSUBF_D; 2331 goto do_fpop; 2332 default: 2333 goto pool32f_invalid; 2334 } 2335 break; 2336 default: 2337 goto pool32f_invalid; 2338 } 2339 break; 2340 do_fpop: 2341 gen_farith(ctx, mips32_op, rt, rs, rd, 0); 2342 break; 2343 default: 2344 pool32f_invalid: 2345 MIPS_INVAL("pool32f"); 2346 gen_reserved_instruction(ctx); 2347 break; 2348 } 2349 } else { 2350 generate_exception_err(ctx, EXCP_CpU, 1); 2351 } 2352 break; 2353 case POOL32I: 2354 minor = (ctx->opcode >> 21) & 0x1f; 2355 switch (minor) { 2356 case BLTZ: 2357 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2358 gen_compute_branch(ctx, OPC_BLTZ, 4, rs, -1, imm << 1, 4); 2359 break; 2360 case BLTZAL: 2361 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2362 gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 4); 2363 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2364 break; 2365 case BLTZALS: 2366 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2367 gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 2); 2368 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2369 break; 2370 case BGEZ: 2371 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2372 gen_compute_branch(ctx, OPC_BGEZ, 4, rs, -1, imm << 1, 4); 2373 break; 2374 case BGEZAL: 2375 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2376 gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 4); 2377 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2378 break; 2379 case BGEZALS: 2380 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2381 gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 2); 2382 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2383 break; 2384 case BLEZ: 2385 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2386 gen_compute_branch(ctx, OPC_BLEZ, 4, rs, -1, imm << 1, 4); 2387 break; 2388 case BGTZ: 2389 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2390 gen_compute_branch(ctx, OPC_BGTZ, 4, rs, -1, imm << 1, 4); 2391 break; 2392 2393 /* Traps */ 2394 case TLTI: /* BC1EQZC */ 2395 if (ctx->insn_flags & ISA_MIPS_R6) { 2396 /* BC1EQZC */ 2397 check_cp1_enabled(ctx); 2398 gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rs, imm << 1, 0); 2399 } else { 2400 /* TLTI */ 2401 mips32_op = OPC_TLTI; 2402 goto do_trapi; 2403 } 2404 break; 2405 case TGEI: /* BC1NEZC */ 2406 if (ctx->insn_flags & ISA_MIPS_R6) { 2407 /* BC1NEZC */ 2408 check_cp1_enabled(ctx); 2409 gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rs, imm << 1, 0); 2410 } else { 2411 /* TGEI */ 2412 mips32_op = OPC_TGEI; 2413 goto do_trapi; 2414 } 2415 break; 2416 case TLTIU: 2417 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2418 mips32_op = OPC_TLTIU; 2419 goto do_trapi; 2420 case TGEIU: 2421 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2422 mips32_op = OPC_TGEIU; 2423 goto do_trapi; 2424 case TNEI: /* SYNCI */ 2425 if (ctx->insn_flags & ISA_MIPS_R6) { 2426 /* SYNCI */ 2427 /* 2428 * Break the TB to be able to sync copied instructions 2429 * immediately. 2430 */ 2431 ctx->base.is_jmp = DISAS_STOP; 2432 } else { 2433 /* TNEI */ 2434 mips32_op = OPC_TNEI; 2435 goto do_trapi; 2436 } 2437 break; 2438 case TEQI: 2439 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2440 mips32_op = OPC_TEQI; 2441 do_trapi: 2442 gen_trap(ctx, mips32_op, rs, -1, imm, 0); 2443 break; 2444 2445 case BNEZC: 2446 case BEQZC: 2447 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2448 gen_compute_branch(ctx, minor == BNEZC ? OPC_BNE : OPC_BEQ, 2449 4, rs, 0, imm << 1, 0); 2450 /* 2451 * Compact branches don't have a delay slot, so just let 2452 * the normal delay slot handling take us to the branch 2453 * target. 2454 */ 2455 break; 2456 case LUI: 2457 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2458 gen_logic_imm(ctx, OPC_LUI, rs, 0, imm); 2459 break; 2460 case SYNCI: 2461 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2462 /* 2463 * Break the TB to be able to sync copied instructions 2464 * immediately. 2465 */ 2466 ctx->base.is_jmp = DISAS_STOP; 2467 break; 2468 case BC2F: 2469 case BC2T: 2470 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2471 /* COP2: Not implemented. */ 2472 generate_exception_err(ctx, EXCP_CpU, 2); 2473 break; 2474 case BC1F: 2475 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2476 mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1FANY2 : OPC_BC1F; 2477 goto do_cp1branch; 2478 case BC1T: 2479 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2480 mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1TANY2 : OPC_BC1T; 2481 goto do_cp1branch; 2482 case BC1ANY4F: 2483 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2484 mips32_op = OPC_BC1FANY4; 2485 goto do_cp1mips3d; 2486 case BC1ANY4T: 2487 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2488 mips32_op = OPC_BC1TANY4; 2489 do_cp1mips3d: 2490 check_cop1x(ctx); 2491 check_insn(ctx, ASE_MIPS3D); 2492 /* Fall through */ 2493 do_cp1branch: 2494 if (env->CP0_Config1 & (1 << CP0C1_FP)) { 2495 check_cp1_enabled(ctx); 2496 gen_compute_branch1(ctx, mips32_op, 2497 (ctx->opcode >> 18) & 0x7, imm << 1); 2498 } else { 2499 generate_exception_err(ctx, EXCP_CpU, 1); 2500 } 2501 break; 2502 default: 2503 MIPS_INVAL("pool32i"); 2504 gen_reserved_instruction(ctx); 2505 break; 2506 } 2507 break; 2508 case POOL32C: 2509 minor = (ctx->opcode >> 12) & 0xf; 2510 offset = sextract32(ctx->opcode, 0, 2511 (ctx->insn_flags & ISA_MIPS_R6) ? 9 : 12); 2512 switch (minor) { 2513 case LWL: 2514 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2515 mips32_op = OPC_LWL; 2516 goto do_ld_lr; 2517 case SWL: 2518 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2519 mips32_op = OPC_SWL; 2520 goto do_st_lr; 2521 case LWR: 2522 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2523 mips32_op = OPC_LWR; 2524 goto do_ld_lr; 2525 case SWR: 2526 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2527 mips32_op = OPC_SWR; 2528 goto do_st_lr; 2529#if defined(TARGET_MIPS64) 2530 case LDL: 2531 check_insn(ctx, ISA_MIPS3); 2532 check_mips_64(ctx); 2533 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2534 mips32_op = OPC_LDL; 2535 goto do_ld_lr; 2536 case SDL: 2537 check_insn(ctx, ISA_MIPS3); 2538 check_mips_64(ctx); 2539 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2540 mips32_op = OPC_SDL; 2541 goto do_st_lr; 2542 case LDR: 2543 check_insn(ctx, ISA_MIPS3); 2544 check_mips_64(ctx); 2545 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2546 mips32_op = OPC_LDR; 2547 goto do_ld_lr; 2548 case SDR: 2549 check_insn(ctx, ISA_MIPS3); 2550 check_mips_64(ctx); 2551 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2552 mips32_op = OPC_SDR; 2553 goto do_st_lr; 2554 case LWU: 2555 check_insn(ctx, ISA_MIPS3); 2556 check_mips_64(ctx); 2557 mips32_op = OPC_LWU; 2558 goto do_ld_lr; 2559 case LLD: 2560 check_insn(ctx, ISA_MIPS3); 2561 check_mips_64(ctx); 2562 mips32_op = OPC_LLD; 2563 goto do_ld_lr; 2564#endif 2565 case LL: 2566 mips32_op = OPC_LL; 2567 goto do_ld_lr; 2568 do_ld_lr: 2569 gen_ld(ctx, mips32_op, rt, rs, offset); 2570 break; 2571 do_st_lr: 2572 gen_st(ctx, mips32_op, rt, rs, offset); 2573 break; 2574 case SC: 2575 gen_st_cond(ctx, rt, rs, offset, MO_TESL, false); 2576 break; 2577#if defined(TARGET_MIPS64) 2578 case SCD: 2579 check_insn(ctx, ISA_MIPS3); 2580 check_mips_64(ctx); 2581 gen_st_cond(ctx, rt, rs, offset, MO_TEUQ, false); 2582 break; 2583#endif 2584 case LD_EVA: 2585 if (!ctx->eva) { 2586 MIPS_INVAL("pool32c ld-eva"); 2587 gen_reserved_instruction(ctx); 2588 break; 2589 } 2590 check_cp0_enabled(ctx); 2591 2592 minor2 = (ctx->opcode >> 9) & 0x7; 2593 offset = sextract32(ctx->opcode, 0, 9); 2594 switch (minor2) { 2595 case LBUE: 2596 mips32_op = OPC_LBUE; 2597 goto do_ld_lr; 2598 case LHUE: 2599 mips32_op = OPC_LHUE; 2600 goto do_ld_lr; 2601 case LWLE: 2602 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2603 mips32_op = OPC_LWLE; 2604 goto do_ld_lr; 2605 case LWRE: 2606 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2607 mips32_op = OPC_LWRE; 2608 goto do_ld_lr; 2609 case LBE: 2610 mips32_op = OPC_LBE; 2611 goto do_ld_lr; 2612 case LHE: 2613 mips32_op = OPC_LHE; 2614 goto do_ld_lr; 2615 case LLE: 2616 mips32_op = OPC_LLE; 2617 goto do_ld_lr; 2618 case LWE: 2619 mips32_op = OPC_LWE; 2620 goto do_ld_lr; 2621 }; 2622 break; 2623 case ST_EVA: 2624 if (!ctx->eva) { 2625 MIPS_INVAL("pool32c st-eva"); 2626 gen_reserved_instruction(ctx); 2627 break; 2628 } 2629 check_cp0_enabled(ctx); 2630 2631 minor2 = (ctx->opcode >> 9) & 0x7; 2632 offset = sextract32(ctx->opcode, 0, 9); 2633 switch (minor2) { 2634 case SWLE: 2635 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2636 mips32_op = OPC_SWLE; 2637 goto do_st_lr; 2638 case SWRE: 2639 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2640 mips32_op = OPC_SWRE; 2641 goto do_st_lr; 2642 case PREFE: 2643 /* Treat as no-op */ 2644 if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) { 2645 /* hint codes 24-31 are reserved and signal RI */ 2646 generate_exception(ctx, EXCP_RI); 2647 } 2648 break; 2649 case CACHEE: 2650 /* Treat as no-op */ 2651 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 2652 gen_cache_operation(ctx, rt, rs, offset); 2653 } 2654 break; 2655 case SBE: 2656 mips32_op = OPC_SBE; 2657 goto do_st_lr; 2658 case SHE: 2659 mips32_op = OPC_SHE; 2660 goto do_st_lr; 2661 case SCE: 2662 gen_st_cond(ctx, rt, rs, offset, MO_TESL, true); 2663 break; 2664 case SWE: 2665 mips32_op = OPC_SWE; 2666 goto do_st_lr; 2667 }; 2668 break; 2669 case PREF: 2670 /* Treat as no-op */ 2671 if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) { 2672 /* hint codes 24-31 are reserved and signal RI */ 2673 generate_exception(ctx, EXCP_RI); 2674 } 2675 break; 2676 default: 2677 MIPS_INVAL("pool32c"); 2678 gen_reserved_instruction(ctx); 2679 break; 2680 } 2681 break; 2682 case ADDI32: /* AUI, LUI */ 2683 if (ctx->insn_flags & ISA_MIPS_R6) { 2684 /* AUI, LUI */ 2685 gen_logic_imm(ctx, OPC_LUI, rt, rs, imm); 2686 } else { 2687 /* ADDI32 */ 2688 mips32_op = OPC_ADDI; 2689 goto do_addi; 2690 } 2691 break; 2692 case ADDIU32: 2693 mips32_op = OPC_ADDIU; 2694 do_addi: 2695 gen_arith_imm(ctx, mips32_op, rt, rs, imm); 2696 break; 2697 2698 /* Logical operations */ 2699 case ORI32: 2700 mips32_op = OPC_ORI; 2701 goto do_logici; 2702 case XORI32: 2703 mips32_op = OPC_XORI; 2704 goto do_logici; 2705 case ANDI32: 2706 mips32_op = OPC_ANDI; 2707 do_logici: 2708 gen_logic_imm(ctx, mips32_op, rt, rs, imm); 2709 break; 2710 2711 /* Set less than immediate */ 2712 case SLTI32: 2713 mips32_op = OPC_SLTI; 2714 goto do_slti; 2715 case SLTIU32: 2716 mips32_op = OPC_SLTIU; 2717 do_slti: 2718 gen_slt_imm(ctx, mips32_op, rt, rs, imm); 2719 break; 2720 case JALX32: 2721 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2722 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; 2723 gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset, 4); 2724 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2725 break; 2726 case JALS32: /* BOVC, BEQC, BEQZALC */ 2727 if (ctx->insn_flags & ISA_MIPS_R6) { 2728 if (rs >= rt) { 2729 /* BOVC */ 2730 mips32_op = OPC_BOVC; 2731 } else if (rs < rt && rs == 0) { 2732 /* BEQZALC */ 2733 mips32_op = OPC_BEQZALC; 2734 } else { 2735 /* BEQC */ 2736 mips32_op = OPC_BEQC; 2737 } 2738 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2739 } else { 2740 /* JALS32 */ 2741 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 1; 2742 gen_compute_branch(ctx, OPC_JAL, 4, rt, rs, offset, 2); 2743 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2744 } 2745 break; 2746 case BEQ32: /* BC */ 2747 if (ctx->insn_flags & ISA_MIPS_R6) { 2748 /* BC */ 2749 gen_compute_compact_branch(ctx, OPC_BC, 0, 0, 2750 sextract32(ctx->opcode << 1, 0, 27)); 2751 } else { 2752 /* BEQ32 */ 2753 gen_compute_branch(ctx, OPC_BEQ, 4, rt, rs, imm << 1, 4); 2754 } 2755 break; 2756 case BNE32: /* BALC */ 2757 if (ctx->insn_flags & ISA_MIPS_R6) { 2758 /* BALC */ 2759 gen_compute_compact_branch(ctx, OPC_BALC, 0, 0, 2760 sextract32(ctx->opcode << 1, 0, 27)); 2761 } else { 2762 /* BNE32 */ 2763 gen_compute_branch(ctx, OPC_BNE, 4, rt, rs, imm << 1, 4); 2764 } 2765 break; 2766 case J32: /* BGTZC, BLTZC, BLTC */ 2767 if (ctx->insn_flags & ISA_MIPS_R6) { 2768 if (rs == 0 && rt != 0) { 2769 /* BGTZC */ 2770 mips32_op = OPC_BGTZC; 2771 } else if (rs != 0 && rt != 0 && rs == rt) { 2772 /* BLTZC */ 2773 mips32_op = OPC_BLTZC; 2774 } else { 2775 /* BLTC */ 2776 mips32_op = OPC_BLTC; 2777 } 2778 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2779 } else { 2780 /* J32 */ 2781 gen_compute_branch(ctx, OPC_J, 4, rt, rs, 2782 (int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4); 2783 } 2784 break; 2785 case JAL32: /* BLEZC, BGEZC, BGEC */ 2786 if (ctx->insn_flags & ISA_MIPS_R6) { 2787 if (rs == 0 && rt != 0) { 2788 /* BLEZC */ 2789 mips32_op = OPC_BLEZC; 2790 } else if (rs != 0 && rt != 0 && rs == rt) { 2791 /* BGEZC */ 2792 mips32_op = OPC_BGEZC; 2793 } else { 2794 /* BGEC */ 2795 mips32_op = OPC_BGEC; 2796 } 2797 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2798 } else { 2799 /* JAL32 */ 2800 gen_compute_branch(ctx, OPC_JAL, 4, rt, rs, 2801 (int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4); 2802 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2803 } 2804 break; 2805 /* Floating point (COP1) */ 2806 case LWC132: 2807 mips32_op = OPC_LWC1; 2808 goto do_cop1; 2809 case LDC132: 2810 mips32_op = OPC_LDC1; 2811 goto do_cop1; 2812 case SWC132: 2813 mips32_op = OPC_SWC1; 2814 goto do_cop1; 2815 case SDC132: 2816 mips32_op = OPC_SDC1; 2817 do_cop1: 2818 gen_cop1_ldst(ctx, mips32_op, rt, rs, imm); 2819 break; 2820 case ADDIUPC: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */ 2821 if (ctx->insn_flags & ISA_MIPS_R6) { 2822 /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */ 2823 switch ((ctx->opcode >> 16) & 0x1f) { 2824 case ADDIUPC_00: 2825 case ADDIUPC_01: 2826 case ADDIUPC_02: 2827 case ADDIUPC_03: 2828 case ADDIUPC_04: 2829 case ADDIUPC_05: 2830 case ADDIUPC_06: 2831 case ADDIUPC_07: 2832 gen_pcrel(ctx, OPC_ADDIUPC, ctx->base.pc_next & ~0x3, rt); 2833 break; 2834 case AUIPC: 2835 gen_pcrel(ctx, OPC_AUIPC, ctx->base.pc_next, rt); 2836 break; 2837 case ALUIPC: 2838 gen_pcrel(ctx, OPC_ALUIPC, ctx->base.pc_next, rt); 2839 break; 2840 case LWPC_08: 2841 case LWPC_09: 2842 case LWPC_0A: 2843 case LWPC_0B: 2844 case LWPC_0C: 2845 case LWPC_0D: 2846 case LWPC_0E: 2847 case LWPC_0F: 2848 gen_pcrel(ctx, R6_OPC_LWPC, ctx->base.pc_next & ~0x3, rt); 2849 break; 2850 default: 2851 generate_exception(ctx, EXCP_RI); 2852 break; 2853 } 2854 } else { 2855 /* ADDIUPC */ 2856 int reg = mmreg(ZIMM(ctx->opcode, 23, 3)); 2857 offset = SIMM(ctx->opcode, 0, 23) << 2; 2858 2859 gen_addiupc(ctx, reg, offset, 0, 0); 2860 } 2861 break; 2862 case BNVC: /* BNEC, BNEZALC */ 2863 check_insn(ctx, ISA_MIPS_R6); 2864 if (rs >= rt) { 2865 /* BNVC */ 2866 mips32_op = OPC_BNVC; 2867 } else if (rs < rt && rs == 0) { 2868 /* BNEZALC */ 2869 mips32_op = OPC_BNEZALC; 2870 } else { 2871 /* BNEC */ 2872 mips32_op = OPC_BNEC; 2873 } 2874 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2875 break; 2876 case R6_BNEZC: /* JIALC */ 2877 check_insn(ctx, ISA_MIPS_R6); 2878 if (rt != 0) { 2879 /* BNEZC */ 2880 gen_compute_compact_branch(ctx, OPC_BNEZC, rt, 0, 2881 sextract32(ctx->opcode << 1, 0, 22)); 2882 } else { 2883 /* JIALC */ 2884 gen_compute_compact_branch(ctx, OPC_JIALC, 0, rs, imm); 2885 } 2886 break; 2887 case R6_BEQZC: /* JIC */ 2888 check_insn(ctx, ISA_MIPS_R6); 2889 if (rt != 0) { 2890 /* BEQZC */ 2891 gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0, 2892 sextract32(ctx->opcode << 1, 0, 22)); 2893 } else { 2894 /* JIC */ 2895 gen_compute_compact_branch(ctx, OPC_JIC, 0, rs, imm); 2896 } 2897 break; 2898 case BLEZALC: /* BGEZALC, BGEUC */ 2899 check_insn(ctx, ISA_MIPS_R6); 2900 if (rs == 0 && rt != 0) { 2901 /* BLEZALC */ 2902 mips32_op = OPC_BLEZALC; 2903 } else if (rs != 0 && rt != 0 && rs == rt) { 2904 /* BGEZALC */ 2905 mips32_op = OPC_BGEZALC; 2906 } else { 2907 /* BGEUC */ 2908 mips32_op = OPC_BGEUC; 2909 } 2910 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2911 break; 2912 case BGTZALC: /* BLTZALC, BLTUC */ 2913 check_insn(ctx, ISA_MIPS_R6); 2914 if (rs == 0 && rt != 0) { 2915 /* BGTZALC */ 2916 mips32_op = OPC_BGTZALC; 2917 } else if (rs != 0 && rt != 0 && rs == rt) { 2918 /* BLTZALC */ 2919 mips32_op = OPC_BLTZALC; 2920 } else { 2921 /* BLTUC */ 2922 mips32_op = OPC_BLTUC; 2923 } 2924 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2925 break; 2926 /* Loads and stores */ 2927 case LB32: 2928 mips32_op = OPC_LB; 2929 goto do_ld; 2930 case LBU32: 2931 mips32_op = OPC_LBU; 2932 goto do_ld; 2933 case LH32: 2934 mips32_op = OPC_LH; 2935 goto do_ld; 2936 case LHU32: 2937 mips32_op = OPC_LHU; 2938 goto do_ld; 2939 case LW32: 2940 mips32_op = OPC_LW; 2941 goto do_ld; 2942#ifdef TARGET_MIPS64 2943 case LD32: 2944 check_insn(ctx, ISA_MIPS3); 2945 check_mips_64(ctx); 2946 mips32_op = OPC_LD; 2947 goto do_ld; 2948 case SD32: 2949 check_insn(ctx, ISA_MIPS3); 2950 check_mips_64(ctx); 2951 mips32_op = OPC_SD; 2952 goto do_st; 2953#endif 2954 case SB32: 2955 mips32_op = OPC_SB; 2956 goto do_st; 2957 case SH32: 2958 mips32_op = OPC_SH; 2959 goto do_st; 2960 case SW32: 2961 mips32_op = OPC_SW; 2962 goto do_st; 2963 do_ld: 2964 gen_ld(ctx, mips32_op, rt, rs, imm); 2965 break; 2966 do_st: 2967 gen_st(ctx, mips32_op, rt, rs, imm); 2968 break; 2969 default: 2970 gen_reserved_instruction(ctx); 2971 break; 2972 } 2973} 2974 2975static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) 2976{ 2977 uint32_t op; 2978 2979 /* make sure instructions are on a halfword boundary */ 2980 if (ctx->base.pc_next & 0x1) { 2981 env->CP0_BadVAddr = ctx->base.pc_next; 2982 generate_exception_end(ctx, EXCP_AdEL); 2983 return 2; 2984 } 2985 2986 op = (ctx->opcode >> 10) & 0x3f; 2987 /* Enforce properly-sized instructions in a delay slot */ 2988 if (ctx->hflags & MIPS_HFLAG_BDS_STRICT) { 2989 switch (op & 0x7) { /* MSB-3..MSB-5 */ 2990 case 0: 2991 /* POOL32A, POOL32B, POOL32I, POOL32C */ 2992 case 4: 2993 /* ADDI32, ADDIU32, ORI32, XORI32, SLTI32, SLTIU32, ANDI32, JALX32 */ 2994 case 5: 2995 /* LBU32, LHU32, POOL32F, JALS32, BEQ32, BNE32, J32, JAL32 */ 2996 case 6: 2997 /* SB32, SH32, ADDIUPC, SWC132, SDC132, SW32 */ 2998 case 7: 2999 /* LB32, LH32, LWC132, LDC132, LW32 */ 3000 if (ctx->hflags & MIPS_HFLAG_BDS16) { 3001 gen_reserved_instruction(ctx); 3002 return 2; 3003 } 3004 break; 3005 case 1: 3006 /* POOL16A, POOL16B, POOL16C, LWGP16, POOL16F */ 3007 case 2: 3008 /* LBU16, LHU16, LWSP16, LW16, SB16, SH16, SWSP16, SW16 */ 3009 case 3: 3010 /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */ 3011 if (ctx->hflags & MIPS_HFLAG_BDS32) { 3012 gen_reserved_instruction(ctx); 3013 return 2; 3014 } 3015 break; 3016 } 3017 } 3018 3019 switch (op) { 3020 case POOL16A: 3021 { 3022 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3023 int rs1 = mmreg(uMIPS_RS1(ctx->opcode)); 3024 int rs2 = mmreg(uMIPS_RS2(ctx->opcode)); 3025 uint32_t opc = 0; 3026 3027 switch (ctx->opcode & 0x1) { 3028 case ADDU16: 3029 opc = OPC_ADDU; 3030 break; 3031 case SUBU16: 3032 opc = OPC_SUBU; 3033 break; 3034 } 3035 if (ctx->insn_flags & ISA_MIPS_R6) { 3036 /* 3037 * In the Release 6, the register number location in 3038 * the instruction encoding has changed. 3039 */ 3040 gen_arith(ctx, opc, rs1, rd, rs2); 3041 } else { 3042 gen_arith(ctx, opc, rd, rs1, rs2); 3043 } 3044 } 3045 break; 3046 case POOL16B: 3047 { 3048 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3049 int rs = mmreg(uMIPS_RS(ctx->opcode)); 3050 int amount = (ctx->opcode >> 1) & 0x7; 3051 uint32_t opc = 0; 3052 amount = amount == 0 ? 8 : amount; 3053 3054 switch (ctx->opcode & 0x1) { 3055 case SLL16: 3056 opc = OPC_SLL; 3057 break; 3058 case SRL16: 3059 opc = OPC_SRL; 3060 break; 3061 } 3062 3063 gen_shift_imm(ctx, opc, rd, rs, amount); 3064 } 3065 break; 3066 case POOL16C: 3067 if (ctx->insn_flags & ISA_MIPS_R6) { 3068 gen_pool16c_r6_insn(ctx); 3069 } else { 3070 gen_pool16c_insn(ctx); 3071 } 3072 break; 3073 case LWGP16: 3074 { 3075 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3076 int rb = 28; /* GP */ 3077 int16_t offset = SIMM(ctx->opcode, 0, 7) << 2; 3078 3079 gen_ld(ctx, OPC_LW, rd, rb, offset); 3080 } 3081 break; 3082 case POOL16F: 3083 check_insn_opc_removed(ctx, ISA_MIPS_R6); 3084 if (ctx->opcode & 1) { 3085 gen_reserved_instruction(ctx); 3086 } else { 3087 /* MOVEP */ 3088 int enc_dest = uMIPS_RD(ctx->opcode); 3089 int enc_rt = uMIPS_RS2(ctx->opcode); 3090 int enc_rs = uMIPS_RS1(ctx->opcode); 3091 gen_movep(ctx, enc_dest, enc_rt, enc_rs); 3092 } 3093 break; 3094 case LBU16: 3095 { 3096 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3097 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3098 int16_t offset = ZIMM(ctx->opcode, 0, 4); 3099 offset = (offset == 0xf ? -1 : offset); 3100 3101 gen_ld(ctx, OPC_LBU, rd, rb, offset); 3102 } 3103 break; 3104 case LHU16: 3105 { 3106 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3107 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3108 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1; 3109 3110 gen_ld(ctx, OPC_LHU, rd, rb, offset); 3111 } 3112 break; 3113 case LWSP16: 3114 { 3115 int rd = (ctx->opcode >> 5) & 0x1f; 3116 int rb = 29; /* SP */ 3117 int16_t offset = ZIMM(ctx->opcode, 0, 5) << 2; 3118 3119 gen_ld(ctx, OPC_LW, rd, rb, offset); 3120 } 3121 break; 3122 case LW16: 3123 { 3124 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3125 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3126 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2; 3127 3128 gen_ld(ctx, OPC_LW, rd, rb, offset); 3129 } 3130 break; 3131 case SB16: 3132 { 3133 int rd = mmreg2(uMIPS_RD(ctx->opcode)); 3134 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3135 int16_t offset = ZIMM(ctx->opcode, 0, 4); 3136 3137 gen_st(ctx, OPC_SB, rd, rb, offset); 3138 } 3139 break; 3140 case SH16: 3141 { 3142 int rd = mmreg2(uMIPS_RD(ctx->opcode)); 3143 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3144 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1; 3145 3146 gen_st(ctx, OPC_SH, rd, rb, offset); 3147 } 3148 break; 3149 case SWSP16: 3150 { 3151 int rd = (ctx->opcode >> 5) & 0x1f; 3152 int rb = 29; /* SP */ 3153 int16_t offset = ZIMM(ctx->opcode, 0, 5) << 2; 3154 3155 gen_st(ctx, OPC_SW, rd, rb, offset); 3156 } 3157 break; 3158 case SW16: 3159 { 3160 int rd = mmreg2(uMIPS_RD(ctx->opcode)); 3161 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3162 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2; 3163 3164 gen_st(ctx, OPC_SW, rd, rb, offset); 3165 } 3166 break; 3167 case MOVE16: 3168 { 3169 int rd = uMIPS_RD5(ctx->opcode); 3170 int rs = uMIPS_RS5(ctx->opcode); 3171 3172 gen_arith(ctx, OPC_ADDU, rd, rs, 0); 3173 } 3174 break; 3175 case ANDI16: 3176 gen_andi16(ctx); 3177 break; 3178 case POOL16D: 3179 switch (ctx->opcode & 0x1) { 3180 case ADDIUS5: 3181 gen_addius5(ctx); 3182 break; 3183 case ADDIUSP: 3184 gen_addiusp(ctx); 3185 break; 3186 } 3187 break; 3188 case POOL16E: 3189 switch (ctx->opcode & 0x1) { 3190 case ADDIUR2: 3191 gen_addiur2(ctx); 3192 break; 3193 case ADDIUR1SP: 3194 gen_addiur1sp(ctx); 3195 break; 3196 } 3197 break; 3198 case B16: /* BC16 */ 3199 gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, 3200 sextract32(ctx->opcode, 0, 10) << 1, 3201 (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4); 3202 break; 3203 case BNEZ16: /* BNEZC16 */ 3204 case BEQZ16: /* BEQZC16 */ 3205 gen_compute_branch(ctx, op == BNEZ16 ? OPC_BNE : OPC_BEQ, 2, 3206 mmreg(uMIPS_RD(ctx->opcode)), 3207 0, sextract32(ctx->opcode, 0, 7) << 1, 3208 (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4); 3209 3210 break; 3211 case LI16: 3212 { 3213 int reg = mmreg(uMIPS_RD(ctx->opcode)); 3214 int imm = ZIMM(ctx->opcode, 0, 7); 3215 3216 imm = (imm == 0x7f ? -1 : imm); 3217 tcg_gen_movi_tl(cpu_gpr[reg], imm); 3218 } 3219 break; 3220 case RES_29: 3221 case RES_31: 3222 case RES_39: 3223 gen_reserved_instruction(ctx); 3224 break; 3225 default: 3226 decode_micromips32_opc(env, ctx); 3227 return 4; 3228 } 3229 3230 return 2; 3231} 3232