1/* 2 * microMIPS translation routines 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * Copyright (c) 2006 Marius Groeger (FPU operations) 6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) 7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) 8 * 9 * SPDX-License-Identifier: LGPL-2.1-or-later 10 */ 11 12/* 13 * microMIPS32/microMIPS64 major opcodes 14 * 15 * 1. MIPS Architecture for Programmers Volume II-B: 16 * The microMIPS32 Instruction Set (Revision 3.05) 17 * 18 * Table 6.2 microMIPS32 Encoding of Major Opcode Field 19 * 20 * 2. MIPS Architecture For Programmers Volume II-A: 21 * The MIPS64 Instruction Set (Revision 3.51) 22 */ 23 24enum { 25 POOL32A = 0x00, 26 POOL16A = 0x01, 27 LBU16 = 0x02, 28 MOVE16 = 0x03, 29 ADDI32 = 0x04, 30 R6_LUI = 0x04, 31 AUI = 0x04, 32 LBU32 = 0x05, 33 SB32 = 0x06, 34 LB32 = 0x07, 35 36 POOL32B = 0x08, 37 POOL16B = 0x09, 38 LHU16 = 0x0a, 39 ANDI16 = 0x0b, 40 ADDIU32 = 0x0c, 41 LHU32 = 0x0d, 42 SH32 = 0x0e, 43 LH32 = 0x0f, 44 45 POOL32I = 0x10, 46 POOL16C = 0x11, 47 LWSP16 = 0x12, 48 POOL16D = 0x13, 49 ORI32 = 0x14, 50 POOL32F = 0x15, 51 POOL32S = 0x16, /* MIPS64 */ 52 DADDIU32 = 0x17, /* MIPS64 */ 53 54 POOL32C = 0x18, 55 LWGP16 = 0x19, 56 LW16 = 0x1a, 57 POOL16E = 0x1b, 58 XORI32 = 0x1c, 59 JALS32 = 0x1d, 60 BOVC = 0x1d, 61 BEQC = 0x1d, 62 BEQZALC = 0x1d, 63 ADDIUPC = 0x1e, 64 PCREL = 0x1e, 65 BNVC = 0x1f, 66 BNEC = 0x1f, 67 BNEZALC = 0x1f, 68 69 R6_BEQZC = 0x20, 70 JIC = 0x20, 71 POOL16F = 0x21, 72 SB16 = 0x22, 73 BEQZ16 = 0x23, 74 BEQZC16 = 0x23, 75 SLTI32 = 0x24, 76 BEQ32 = 0x25, 77 BC = 0x25, 78 SWC132 = 0x26, 79 LWC132 = 0x27, 80 81 /* 0x29 is reserved */ 82 RES_29 = 0x29, 83 R6_BNEZC = 0x28, 84 JIALC = 0x28, 85 SH16 = 0x2a, 86 BNEZ16 = 0x2b, 87 BNEZC16 = 0x2b, 88 SLTIU32 = 0x2c, 89 BNE32 = 0x2d, 90 BALC = 0x2d, 91 SDC132 = 0x2e, 92 LDC132 = 0x2f, 93 94 /* 0x31 is reserved */ 95 RES_31 = 0x31, 96 BLEZALC = 0x30, 97 BGEZALC = 0x30, 98 BGEUC = 0x30, 99 SWSP16 = 0x32, 100 B16 = 0x33, 101 BC16 = 0x33, 102 ANDI32 = 0x34, 103 J32 = 0x35, 104 BGTZC = 0x35, 105 BLTZC = 0x35, 106 BLTC = 0x35, 107 SD32 = 0x36, /* MIPS64 */ 108 LD32 = 0x37, /* MIPS64 */ 109 110 /* 0x39 is reserved */ 111 RES_39 = 0x39, 112 BGTZALC = 0x38, 113 BLTZALC = 0x38, 114 BLTUC = 0x38, 115 SW16 = 0x3a, 116 LI16 = 0x3b, 117 JALX32 = 0x3c, 118 JAL32 = 0x3d, 119 BLEZC = 0x3d, 120 BGEZC = 0x3d, 121 BGEC = 0x3d, 122 SW32 = 0x3e, 123 LW32 = 0x3f 124}; 125 126/* PCREL Instructions perform PC-Relative address calculation. bits 20..16 */ 127enum { 128 ADDIUPC_00 = 0x00, 129 ADDIUPC_01 = 0x01, 130 ADDIUPC_02 = 0x02, 131 ADDIUPC_03 = 0x03, 132 ADDIUPC_04 = 0x04, 133 ADDIUPC_05 = 0x05, 134 ADDIUPC_06 = 0x06, 135 ADDIUPC_07 = 0x07, 136 AUIPC = 0x1e, 137 ALUIPC = 0x1f, 138 LWPC_08 = 0x08, 139 LWPC_09 = 0x09, 140 LWPC_0A = 0x0A, 141 LWPC_0B = 0x0B, 142 LWPC_0C = 0x0C, 143 LWPC_0D = 0x0D, 144 LWPC_0E = 0x0E, 145 LWPC_0F = 0x0F, 146}; 147 148/* POOL32A encoding of minor opcode field */ 149 150enum { 151 /* 152 * These opcodes are distinguished only by bits 9..6; those bits are 153 * what are recorded below. 154 */ 155 SLL32 = 0x0, 156 SRL32 = 0x1, 157 SRA = 0x2, 158 ROTR = 0x3, 159 SELEQZ = 0x5, 160 SELNEZ = 0x6, 161 R6_RDHWR = 0x7, 162 163 SLLV = 0x0, 164 SRLV = 0x1, 165 SRAV = 0x2, 166 ROTRV = 0x3, 167 ADD = 0x4, 168 ADDU32 = 0x5, 169 SUB = 0x6, 170 SUBU32 = 0x7, 171 MUL = 0x8, 172 AND = 0x9, 173 OR32 = 0xa, 174 NOR = 0xb, 175 XOR32 = 0xc, 176 SLT = 0xd, 177 SLTU = 0xe, 178 179 MOVN = 0x0, 180 R6_MUL = 0x0, 181 MOVZ = 0x1, 182 MUH = 0x1, 183 MULU = 0x2, 184 MUHU = 0x3, 185 LWXS = 0x4, 186 R6_DIV = 0x4, 187 MOD = 0x5, 188 R6_DIVU = 0x6, 189 MODU = 0x7, 190 191 /* The following can be distinguished by their lower 6 bits. */ 192 BREAK32 = 0x07, 193 INS = 0x0c, 194 LSA = 0x0f, 195 ALIGN = 0x1f, 196 EXT = 0x2c, 197 POOL32AXF = 0x3c, 198 SIGRIE = 0x3f 199}; 200 201/* POOL32AXF encoding of minor opcode field extension */ 202 203/* 204 * 1. MIPS Architecture for Programmers Volume II-B: 205 * The microMIPS32 Instruction Set (Revision 3.05) 206 * 207 * Table 6.5 POOL32Axf Encoding of Minor Opcode Extension Field 208 * 209 * 2. MIPS Architecture for Programmers VolumeIV-e: 210 * The MIPS DSP Application-Specific Extension 211 * to the microMIPS32 Architecture (Revision 2.34) 212 * 213 * Table 5.5 POOL32Axf Encoding of Minor Opcode Extension Field 214 */ 215 216enum { 217 /* bits 11..6 */ 218 TEQ = 0x00, 219 TGE = 0x08, 220 TGEU = 0x10, 221 TLT = 0x20, 222 TLTU = 0x28, 223 TNE = 0x30, 224 225 MFC0 = 0x03, 226 MTC0 = 0x0b, 227 228 /* begin of microMIPS32 DSP */ 229 230 /* bits 13..12 for 0x01 */ 231 MFHI_ACC = 0x0, 232 MFLO_ACC = 0x1, 233 MTHI_ACC = 0x2, 234 MTLO_ACC = 0x3, 235 236 /* bits 13..12 for 0x2a */ 237 MADD_ACC = 0x0, 238 MADDU_ACC = 0x1, 239 MSUB_ACC = 0x2, 240 MSUBU_ACC = 0x3, 241 242 /* bits 13..12 for 0x32 */ 243 MULT_ACC = 0x0, 244 MULTU_ACC = 0x1, 245 246 /* end of microMIPS32 DSP */ 247 248 /* bits 15..12 for 0x2c */ 249 BITSWAP = 0x0, 250 SEB = 0x2, 251 SEH = 0x3, 252 CLO = 0x4, 253 CLZ = 0x5, 254 RDHWR = 0x6, 255 WSBH = 0x7, 256 MULT = 0x8, 257 MULTU = 0x9, 258 DIV = 0xa, 259 DIVU = 0xb, 260 MADD = 0xc, 261 MADDU = 0xd, 262 MSUB = 0xe, 263 MSUBU = 0xf, 264 265 /* bits 15..12 for 0x34 */ 266 MFC2 = 0x4, 267 MTC2 = 0x5, 268 MFHC2 = 0x8, 269 MTHC2 = 0x9, 270 CFC2 = 0xc, 271 CTC2 = 0xd, 272 273 /* bits 15..12 for 0x3c */ 274 JALR = 0x0, 275 JR = 0x0, /* alias */ 276 JALRC = 0x0, 277 JRC = 0x0, 278 JALR_HB = 0x1, 279 JALRC_HB = 0x1, 280 JALRS = 0x4, 281 JALRS_HB = 0x5, 282 283 /* bits 15..12 for 0x05 */ 284 RDPGPR = 0xe, 285 WRPGPR = 0xf, 286 287 /* bits 15..12 for 0x0d */ 288 TLBP = 0x0, 289 TLBR = 0x1, 290 TLBWI = 0x2, 291 TLBWR = 0x3, 292 TLBINV = 0x4, 293 TLBINVF = 0x5, 294 WAIT = 0x9, 295 IRET = 0xd, 296 DERET = 0xe, 297 ERET = 0xf, 298 299 /* bits 15..12 for 0x15 */ 300 DMT = 0x0, 301 DVPE = 0x1, 302 EMT = 0x2, 303 EVPE = 0x3, 304 305 /* bits 15..12 for 0x1d */ 306 DI = 0x4, 307 EI = 0x5, 308 309 /* bits 15..12 for 0x2d */ 310 SYNC = 0x6, 311 SYSCALL = 0x8, 312 SDBBP = 0xd, 313 314 /* bits 15..12 for 0x35 */ 315 MFHI32 = 0x0, 316 MFLO32 = 0x1, 317 MTHI32 = 0x2, 318 MTLO32 = 0x3, 319}; 320 321/* POOL32B encoding of minor opcode field (bits 15..12) */ 322 323enum { 324 LWC2 = 0x0, 325 LWP = 0x1, 326 LDP = 0x4, 327 LWM32 = 0x5, 328 CACHE = 0x6, 329 LDM = 0x7, 330 SWC2 = 0x8, 331 SWP = 0x9, 332 SDP = 0xc, 333 SWM32 = 0xd, 334 SDM = 0xf 335}; 336 337/* POOL32C encoding of minor opcode field (bits 15..12) */ 338 339enum { 340 LWL = 0x0, 341 SWL = 0x8, 342 LWR = 0x1, 343 SWR = 0x9, 344 PREF = 0x2, 345 ST_EVA = 0xa, 346 LL = 0x3, 347 SC = 0xb, 348 LDL = 0x4, 349 SDL = 0xc, 350 LDR = 0x5, 351 SDR = 0xd, 352 LD_EVA = 0x6, 353 LWU = 0xe, 354 LLD = 0x7, 355 SCD = 0xf 356}; 357 358/* POOL32C LD-EVA encoding of minor opcode field (bits 11..9) */ 359 360enum { 361 LBUE = 0x0, 362 LHUE = 0x1, 363 LWLE = 0x2, 364 LWRE = 0x3, 365 LBE = 0x4, 366 LHE = 0x5, 367 LLE = 0x6, 368 LWE = 0x7, 369}; 370 371/* POOL32C ST-EVA encoding of minor opcode field (bits 11..9) */ 372 373enum { 374 SWLE = 0x0, 375 SWRE = 0x1, 376 PREFE = 0x2, 377 CACHEE = 0x3, 378 SBE = 0x4, 379 SHE = 0x5, 380 SCE = 0x6, 381 SWE = 0x7, 382}; 383 384/* POOL32F encoding of minor opcode field (bits 5..0) */ 385 386enum { 387 /* These are the bit 7..6 values */ 388 ADD_FMT = 0x0, 389 390 SUB_FMT = 0x1, 391 392 MUL_FMT = 0x2, 393 394 DIV_FMT = 0x3, 395 396 /* These are the bit 8..6 values */ 397 MOVN_FMT = 0x0, 398 RSQRT2_FMT = 0x0, 399 MOVF_FMT = 0x0, 400 RINT_FMT = 0x0, 401 SELNEZ_FMT = 0x0, 402 403 MOVZ_FMT = 0x1, 404 LWXC1 = 0x1, 405 MOVT_FMT = 0x1, 406 CLASS_FMT = 0x1, 407 SELEQZ_FMT = 0x1, 408 409 PLL_PS = 0x2, 410 SWXC1 = 0x2, 411 SEL_FMT = 0x2, 412 413 PLU_PS = 0x3, 414 LDXC1 = 0x3, 415 416 MOVN_FMT_04 = 0x4, 417 PUL_PS = 0x4, 418 SDXC1 = 0x4, 419 RECIP2_FMT = 0x4, 420 421 MOVZ_FMT_05 = 0x05, 422 PUU_PS = 0x5, 423 LUXC1 = 0x5, 424 425 CVT_PS_S = 0x6, 426 SUXC1 = 0x6, 427 ADDR_PS = 0x6, 428 PREFX = 0x6, 429 MADDF_FMT = 0x6, 430 431 MULR_PS = 0x7, 432 MSUBF_FMT = 0x7, 433 434 MADD_S = 0x01, 435 MADD_D = 0x09, 436 MADD_PS = 0x11, 437 ALNV_PS = 0x19, 438 MSUB_S = 0x21, 439 MSUB_D = 0x29, 440 MSUB_PS = 0x31, 441 442 NMADD_S = 0x02, 443 NMADD_D = 0x0a, 444 NMADD_PS = 0x12, 445 NMSUB_S = 0x22, 446 NMSUB_D = 0x2a, 447 NMSUB_PS = 0x32, 448 449 MIN_FMT = 0x3, 450 MAX_FMT = 0xb, 451 MINA_FMT = 0x23, 452 MAXA_FMT = 0x2b, 453 POOL32FXF = 0x3b, 454 455 CABS_COND_FMT = 0x1c, /* MIPS3D */ 456 C_COND_FMT = 0x3c, 457 458 CMP_CONDN_S = 0x5, 459 CMP_CONDN_D = 0x15 460}; 461 462/* POOL32Fxf encoding of minor opcode extension field */ 463 464enum { 465 CVT_L = 0x04, 466 RSQRT_FMT = 0x08, 467 FLOOR_L = 0x0c, 468 CVT_PW_PS = 0x1c, 469 CVT_W = 0x24, 470 SQRT_FMT = 0x28, 471 FLOOR_W = 0x2c, 472 CVT_PS_PW = 0x3c, 473 CFC1 = 0x40, 474 RECIP_FMT = 0x48, 475 CEIL_L = 0x4c, 476 CTC1 = 0x60, 477 CEIL_W = 0x6c, 478 MFC1 = 0x80, 479 CVT_S_PL = 0x84, 480 TRUNC_L = 0x8c, 481 MTC1 = 0xa0, 482 CVT_S_PU = 0xa4, 483 TRUNC_W = 0xac, 484 MFHC1 = 0xc0, 485 ROUND_L = 0xcc, 486 MTHC1 = 0xe0, 487 ROUND_W = 0xec, 488 489 MOV_FMT = 0x01, 490 MOVF = 0x05, 491 ABS_FMT = 0x0d, 492 RSQRT1_FMT = 0x1d, 493 MOVT = 0x25, 494 NEG_FMT = 0x2d, 495 CVT_D = 0x4d, 496 RECIP1_FMT = 0x5d, 497 CVT_S = 0x6d 498}; 499 500/* POOL32I encoding of minor opcode field (bits 25..21) */ 501 502enum { 503 BLTZ = 0x00, 504 BLTZAL = 0x01, 505 BGEZ = 0x02, 506 BGEZAL = 0x03, 507 BLEZ = 0x04, 508 BNEZC = 0x05, 509 BGTZ = 0x06, 510 BEQZC = 0x07, 511 TLTI = 0x08, 512 BC1EQZC = 0x08, 513 TGEI = 0x09, 514 BC1NEZC = 0x09, 515 TLTIU = 0x0a, 516 BC2EQZC = 0x0a, 517 TGEIU = 0x0b, 518 BC2NEZC = 0x0a, 519 TNEI = 0x0c, 520 R6_SYNCI = 0x0c, 521 LUI = 0x0d, 522 TEQI = 0x0e, 523 SYNCI = 0x10, 524 BLTZALS = 0x11, 525 BGEZALS = 0x13, 526 BC2F = 0x14, 527 BC2T = 0x15, 528 /* These overlap and are distinguished by bit16 of the instruction */ 529 BC1F = 0x1c, 530 BC1T = 0x1d, 531 BC1ANY2F = 0x1c, 532 BC1ANY2T = 0x1d, 533 BC1ANY4F = 0x1e, 534 BC1ANY4T = 0x1f 535}; 536 537/* POOL16A encoding of minor opcode field */ 538 539enum { 540 ADDU16 = 0x0, 541 SUBU16 = 0x1 542}; 543 544/* POOL16B encoding of minor opcode field */ 545 546enum { 547 SLL16 = 0x0, 548 SRL16 = 0x1 549}; 550 551/* POOL16C encoding of minor opcode field */ 552 553enum { 554 NOT16 = 0x00, 555 XOR16 = 0x04, 556 AND16 = 0x08, 557 OR16 = 0x0c, 558 LWM16 = 0x10, 559 SWM16 = 0x14, 560 JR16 = 0x18, 561 JRC16 = 0x1a, 562 JALR16 = 0x1c, 563 JALR16S = 0x1e, 564 MFHI16 = 0x20, 565 MFLO16 = 0x24, 566 BREAK16 = 0x28, 567 SDBBP16 = 0x2c, 568 JRADDIUSP = 0x30 569}; 570 571/* R6 POOL16C encoding of minor opcode field (bits 0..5) */ 572 573enum { 574 R6_NOT16 = 0x00, 575 R6_AND16 = 0x01, 576 R6_LWM16 = 0x02, 577 R6_JRC16 = 0x03, 578 MOVEP = 0x04, 579 MOVEP_05 = 0x05, 580 MOVEP_06 = 0x06, 581 MOVEP_07 = 0x07, 582 R6_XOR16 = 0x08, 583 R6_OR16 = 0x09, 584 R6_SWM16 = 0x0a, 585 JALRC16 = 0x0b, 586 MOVEP_0C = 0x0c, 587 MOVEP_0D = 0x0d, 588 MOVEP_0E = 0x0e, 589 MOVEP_0F = 0x0f, 590 JRCADDIUSP = 0x13, 591 R6_BREAK16 = 0x1b, 592 R6_SDBBP16 = 0x3b 593}; 594 595/* POOL16D encoding of minor opcode field */ 596 597enum { 598 ADDIUS5 = 0x0, 599 ADDIUSP = 0x1 600}; 601 602/* POOL16E encoding of minor opcode field */ 603 604enum { 605 ADDIUR2 = 0x0, 606 ADDIUR1SP = 0x1 607}; 608 609static int mmreg(int r) 610{ 611 static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; 612 613 return map[r]; 614} 615 616/* Used for 16-bit store instructions. */ 617static int mmreg2(int r) 618{ 619 static const int map[] = { 0, 17, 2, 3, 4, 5, 6, 7 }; 620 621 return map[r]; 622} 623 624#define uMIPS_RD(op) ((op >> 7) & 0x7) 625#define uMIPS_RS(op) ((op >> 4) & 0x7) 626#define uMIPS_RS2(op) uMIPS_RS(op) 627#define uMIPS_RS1(op) ((op >> 1) & 0x7) 628#define uMIPS_RD5(op) ((op >> 5) & 0x1f) 629#define uMIPS_RS5(op) (op & 0x1f) 630 631/* Signed immediate */ 632#define SIMM(op, start, width) \ 633 ((int32_t)(((op >> start) & ((~0U) >> (32 - width))) \ 634 << (32 - width)) \ 635 >> (32 - width)) 636/* Zero-extended immediate */ 637#define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32 - width))) 638 639static void gen_addiur1sp(DisasContext *ctx) 640{ 641 int rd = mmreg(uMIPS_RD(ctx->opcode)); 642 643 gen_arith_imm(ctx, OPC_ADDIU, rd, 29, ((ctx->opcode >> 1) & 0x3f) << 2); 644} 645 646static void gen_addiur2(DisasContext *ctx) 647{ 648 static const int decoded_imm[] = { 1, 4, 8, 12, 16, 20, 24, -1 }; 649 int rd = mmreg(uMIPS_RD(ctx->opcode)); 650 int rs = mmreg(uMIPS_RS(ctx->opcode)); 651 652 gen_arith_imm(ctx, OPC_ADDIU, rd, rs, decoded_imm[ZIMM(ctx->opcode, 1, 3)]); 653} 654 655static void gen_addiusp(DisasContext *ctx) 656{ 657 int encoded = ZIMM(ctx->opcode, 1, 9); 658 int decoded; 659 660 if (encoded <= 1) { 661 decoded = 256 + encoded; 662 } else if (encoded <= 255) { 663 decoded = encoded; 664 } else if (encoded <= 509) { 665 decoded = encoded - 512; 666 } else { 667 decoded = encoded - 768; 668 } 669 670 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, decoded << 2); 671} 672 673static void gen_addius5(DisasContext *ctx) 674{ 675 int imm = SIMM(ctx->opcode, 1, 4); 676 int rd = (ctx->opcode >> 5) & 0x1f; 677 678 gen_arith_imm(ctx, OPC_ADDIU, rd, rd, imm); 679} 680 681static void gen_andi16(DisasContext *ctx) 682{ 683 static const int decoded_imm[] = { 128, 1, 2, 3, 4, 7, 8, 15, 16, 684 31, 32, 63, 64, 255, 32768, 65535 }; 685 int rd = mmreg(uMIPS_RD(ctx->opcode)); 686 int rs = mmreg(uMIPS_RS(ctx->opcode)); 687 int encoded = ZIMM(ctx->opcode, 0, 4); 688 689 gen_logic_imm(ctx, OPC_ANDI, rd, rs, decoded_imm[encoded]); 690} 691 692static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist, 693 int base, int16_t offset) 694{ 695 TCGv t0, t1; 696 TCGv_i32 t2; 697 698 if (ctx->hflags & MIPS_HFLAG_BMASK) { 699 gen_reserved_instruction(ctx); 700 return; 701 } 702 703 t0 = tcg_temp_new(); 704 705 gen_base_offset_addr(ctx, t0, base, offset); 706 707 t1 = tcg_constant_tl(reglist); 708 t2 = tcg_constant_i32(ctx->mem_idx); 709 710 save_cpu_state(ctx, 1); 711 switch (opc) { 712 case LWM32: 713 gen_helper_lwm(tcg_env, t0, t1, t2); 714 break; 715 case SWM32: 716 gen_helper_swm(tcg_env, t0, t1, t2); 717 break; 718#ifdef TARGET_MIPS64 719 case LDM: 720 gen_helper_ldm(tcg_env, t0, t1, t2); 721 break; 722 case SDM: 723 gen_helper_sdm(tcg_env, t0, t1, t2); 724 break; 725#endif 726 } 727} 728 729 730static void gen_pool16c_insn(DisasContext *ctx) 731{ 732 int rd = mmreg((ctx->opcode >> 3) & 0x7); 733 int rs = mmreg(ctx->opcode & 0x7); 734 735 switch (((ctx->opcode) >> 4) & 0x3f) { 736 case NOT16 + 0: 737 case NOT16 + 1: 738 case NOT16 + 2: 739 case NOT16 + 3: 740 gen_logic(ctx, OPC_NOR, rd, rs, 0); 741 break; 742 case XOR16 + 0: 743 case XOR16 + 1: 744 case XOR16 + 2: 745 case XOR16 + 3: 746 gen_logic(ctx, OPC_XOR, rd, rd, rs); 747 break; 748 case AND16 + 0: 749 case AND16 + 1: 750 case AND16 + 2: 751 case AND16 + 3: 752 gen_logic(ctx, OPC_AND, rd, rd, rs); 753 break; 754 case OR16 + 0: 755 case OR16 + 1: 756 case OR16 + 2: 757 case OR16 + 3: 758 gen_logic(ctx, OPC_OR, rd, rd, rs); 759 break; 760 case LWM16 + 0: 761 case LWM16 + 1: 762 case LWM16 + 2: 763 case LWM16 + 3: 764 { 765 static const int lwm_convert[] = { 0x11, 0x12, 0x13, 0x14 }; 766 int offset = ZIMM(ctx->opcode, 0, 4); 767 768 gen_ldst_multiple(ctx, LWM32, lwm_convert[(ctx->opcode >> 4) & 0x3], 769 29, offset << 2); 770 } 771 break; 772 case SWM16 + 0: 773 case SWM16 + 1: 774 case SWM16 + 2: 775 case SWM16 + 3: 776 { 777 static const int swm_convert[] = { 0x11, 0x12, 0x13, 0x14 }; 778 int offset = ZIMM(ctx->opcode, 0, 4); 779 780 gen_ldst_multiple(ctx, SWM32, swm_convert[(ctx->opcode >> 4) & 0x3], 781 29, offset << 2); 782 } 783 break; 784 case JR16 + 0: 785 case JR16 + 1: 786 { 787 int reg = ctx->opcode & 0x1f; 788 789 gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0, 4); 790 } 791 break; 792 case JRC16 + 0: 793 case JRC16 + 1: 794 { 795 int reg = ctx->opcode & 0x1f; 796 gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0, 0); 797 /* 798 * Let normal delay slot handling in our caller take us 799 * to the branch target. 800 */ 801 } 802 break; 803 case JALR16 + 0: 804 case JALR16 + 1: 805 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 4); 806 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 807 break; 808 case JALR16S + 0: 809 case JALR16S + 1: 810 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 2); 811 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 812 break; 813 case MFHI16 + 0: 814 case MFHI16 + 1: 815 gen_HILO(ctx, OPC_MFHI, 0, uMIPS_RS5(ctx->opcode)); 816 break; 817 case MFLO16 + 0: 818 case MFLO16 + 1: 819 gen_HILO(ctx, OPC_MFLO, 0, uMIPS_RS5(ctx->opcode)); 820 break; 821 case BREAK16: 822 generate_exception_break(ctx, extract32(ctx->opcode, 0, 4)); 823 break; 824 case SDBBP16: 825 if (is_uhi(ctx, extract32(ctx->opcode, 0, 4))) { 826 ctx->base.is_jmp = DISAS_SEMIHOST; 827 } else { 828 /* 829 * XXX: not clear which exception should be raised 830 * when in debug mode... 831 */ 832 check_insn(ctx, ISA_MIPS_R1); 833 generate_exception_end(ctx, EXCP_DBp); 834 } 835 break; 836 case JRADDIUSP + 0: 837 case JRADDIUSP + 1: 838 { 839 int imm = ZIMM(ctx->opcode, 0, 5); 840 gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0); 841 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2); 842 /* 843 * Let normal delay slot handling in our caller take us 844 * to the branch target. 845 */ 846 } 847 break; 848 default: 849 gen_reserved_instruction(ctx); 850 break; 851 } 852} 853 854static inline void gen_movep(DisasContext *ctx, int enc_dest, int enc_rt, 855 int enc_rs) 856{ 857 int rd, re; 858 static const int rd_enc[] = { 5, 5, 6, 4, 4, 4, 4, 4 }; 859 static const int re_enc[] = { 6, 7, 7, 21, 22, 5, 6, 7 }; 860 static const int rs_rt_enc[] = { 0, 17, 2, 3, 16, 18, 19, 20 }; 861 862 rd = rd_enc[enc_dest]; 863 re = re_enc[enc_dest]; 864 gen_load_gpr(cpu_gpr[rd], rs_rt_enc[enc_rs]); 865 gen_load_gpr(cpu_gpr[re], rs_rt_enc[enc_rt]); 866} 867 868static void gen_pool16c_r6_insn(DisasContext *ctx) 869{ 870 int rt = mmreg((ctx->opcode >> 7) & 0x7); 871 int rs = mmreg((ctx->opcode >> 4) & 0x7); 872 873 switch (ctx->opcode & 0xf) { 874 case R6_NOT16: 875 gen_logic(ctx, OPC_NOR, rt, rs, 0); 876 break; 877 case R6_AND16: 878 gen_logic(ctx, OPC_AND, rt, rt, rs); 879 break; 880 case R6_LWM16: 881 { 882 int lwm_converted = 0x11 + extract32(ctx->opcode, 8, 2); 883 int offset = extract32(ctx->opcode, 4, 4); 884 gen_ldst_multiple(ctx, LWM32, lwm_converted, 29, offset << 2); 885 } 886 break; 887 case R6_JRC16: /* JRCADDIUSP */ 888 if ((ctx->opcode >> 4) & 1) { 889 /* JRCADDIUSP */ 890 int imm = extract32(ctx->opcode, 5, 5); 891 gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0); 892 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2); 893 } else { 894 /* JRC16 */ 895 rs = extract32(ctx->opcode, 5, 5); 896 gen_compute_branch(ctx, OPC_JR, 2, rs, 0, 0, 0); 897 } 898 break; 899 case MOVEP: 900 case MOVEP_05: 901 case MOVEP_06: 902 case MOVEP_07: 903 case MOVEP_0C: 904 case MOVEP_0D: 905 case MOVEP_0E: 906 case MOVEP_0F: 907 { 908 int enc_dest = uMIPS_RD(ctx->opcode); 909 int enc_rt = uMIPS_RS2(ctx->opcode); 910 int enc_rs = (ctx->opcode & 3) | ((ctx->opcode >> 1) & 4); 911 gen_movep(ctx, enc_dest, enc_rt, enc_rs); 912 } 913 break; 914 case R6_XOR16: 915 gen_logic(ctx, OPC_XOR, rt, rt, rs); 916 break; 917 case R6_OR16: 918 gen_logic(ctx, OPC_OR, rt, rt, rs); 919 break; 920 case R6_SWM16: 921 { 922 int swm_converted = 0x11 + extract32(ctx->opcode, 8, 2); 923 int offset = extract32(ctx->opcode, 4, 4); 924 gen_ldst_multiple(ctx, SWM32, swm_converted, 29, offset << 2); 925 } 926 break; 927 case JALRC16: /* BREAK16, SDBBP16 */ 928 switch (ctx->opcode & 0x3f) { 929 case JALRC16: 930 case JALRC16 + 0x20: 931 /* JALRC16 */ 932 gen_compute_branch(ctx, OPC_JALR, 2, (ctx->opcode >> 5) & 0x1f, 933 31, 0, 0); 934 break; 935 case R6_BREAK16: 936 /* BREAK16 */ 937 generate_exception_break(ctx, extract32(ctx->opcode, 6, 4)); 938 break; 939 case R6_SDBBP16: 940 /* SDBBP16 */ 941 if (is_uhi(ctx, extract32(ctx->opcode, 6, 4))) { 942 ctx->base.is_jmp = DISAS_SEMIHOST; 943 } else { 944 if (ctx->hflags & MIPS_HFLAG_SBRI) { 945 generate_exception(ctx, EXCP_RI); 946 } else { 947 generate_exception(ctx, EXCP_DBp); 948 } 949 } 950 break; 951 } 952 break; 953 default: 954 generate_exception(ctx, EXCP_RI); 955 break; 956 } 957} 958 959static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, 960 int base, int16_t offset) 961{ 962 TCGv t0, t1; 963 964 if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31) { 965 gen_reserved_instruction(ctx); 966 return; 967 } 968 969 t0 = tcg_temp_new(); 970 t1 = tcg_temp_new(); 971 972 gen_base_offset_addr(ctx, t0, base, offset); 973 974 switch (opc) { 975 case LWP: 976 if (rd == base) { 977 gen_reserved_instruction(ctx); 978 return; 979 } 980 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | 981 ctx->default_tcg_memop_mask); 982 gen_store_gpr(t1, rd); 983 gen_op_addr_addi(ctx, t0, t0, 4); 984 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | 985 ctx->default_tcg_memop_mask); 986 gen_store_gpr(t1, rd + 1); 987 break; 988 case SWP: 989 gen_load_gpr(t1, rd); 990 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | 991 ctx->default_tcg_memop_mask); 992 gen_op_addr_addi(ctx, t0, t0, 4); 993 gen_load_gpr(t1, rd + 1); 994 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | 995 ctx->default_tcg_memop_mask); 996 break; 997#ifdef TARGET_MIPS64 998 case LDP: 999 if (rd == base) { 1000 gen_reserved_instruction(ctx); 1001 return; 1002 } 1003 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 1004 ctx->default_tcg_memop_mask); 1005 gen_store_gpr(t1, rd); 1006 gen_op_addr_addi(ctx, t0, t0, 8); 1007 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 1008 ctx->default_tcg_memop_mask); 1009 gen_store_gpr(t1, rd + 1); 1010 break; 1011 case SDP: 1012 gen_load_gpr(t1, rd); 1013 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 1014 ctx->default_tcg_memop_mask); 1015 gen_op_addr_addi(ctx, t0, t0, 8); 1016 gen_load_gpr(t1, rd + 1); 1017 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 1018 ctx->default_tcg_memop_mask); 1019 break; 1020#endif 1021 } 1022} 1023 1024static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) 1025{ 1026 int extension = (ctx->opcode >> 6) & 0x3f; 1027 int minor = (ctx->opcode >> 12) & 0xf; 1028 uint32_t mips32_op; 1029 1030 switch (extension) { 1031 case TEQ: 1032 mips32_op = OPC_TEQ; 1033 goto do_trap; 1034 case TGE: 1035 mips32_op = OPC_TGE; 1036 goto do_trap; 1037 case TGEU: 1038 mips32_op = OPC_TGEU; 1039 goto do_trap; 1040 case TLT: 1041 mips32_op = OPC_TLT; 1042 goto do_trap; 1043 case TLTU: 1044 mips32_op = OPC_TLTU; 1045 goto do_trap; 1046 case TNE: 1047 mips32_op = OPC_TNE; 1048 do_trap: 1049 gen_trap(ctx, mips32_op, rs, rt, -1, extract32(ctx->opcode, 12, 4)); 1050 break; 1051#ifndef CONFIG_USER_ONLY 1052 case MFC0: 1053 case MFC0 + 32: 1054 check_cp0_enabled(ctx); 1055 if (rt == 0) { 1056 /* Treat as NOP. */ 1057 break; 1058 } 1059 gen_mfc0(ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7); 1060 break; 1061 case MTC0: 1062 case MTC0 + 32: 1063 check_cp0_enabled(ctx); 1064 { 1065 TCGv t0 = tcg_temp_new(); 1066 1067 gen_load_gpr(t0, rt); 1068 gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7); 1069 } 1070 break; 1071#endif 1072 case 0x2a: 1073 switch (minor & 3) { 1074 case MADD_ACC: 1075 gen_muldiv(ctx, OPC_MADD, (ctx->opcode >> 14) & 3, rs, rt); 1076 break; 1077 case MADDU_ACC: 1078 gen_muldiv(ctx, OPC_MADDU, (ctx->opcode >> 14) & 3, rs, rt); 1079 break; 1080 case MSUB_ACC: 1081 gen_muldiv(ctx, OPC_MSUB, (ctx->opcode >> 14) & 3, rs, rt); 1082 break; 1083 case MSUBU_ACC: 1084 gen_muldiv(ctx, OPC_MSUBU, (ctx->opcode >> 14) & 3, rs, rt); 1085 break; 1086 default: 1087 goto pool32axf_invalid; 1088 } 1089 break; 1090 case 0x32: 1091 switch (minor & 3) { 1092 case MULT_ACC: 1093 gen_muldiv(ctx, OPC_MULT, (ctx->opcode >> 14) & 3, rs, rt); 1094 break; 1095 case MULTU_ACC: 1096 gen_muldiv(ctx, OPC_MULTU, (ctx->opcode >> 14) & 3, rs, rt); 1097 break; 1098 default: 1099 goto pool32axf_invalid; 1100 } 1101 break; 1102 case 0x2c: 1103 switch (minor) { 1104 case BITSWAP: 1105 check_insn(ctx, ISA_MIPS_R6); 1106 gen_bitswap(ctx, OPC_BITSWAP, rs, rt); 1107 break; 1108 case SEB: 1109 gen_bshfl(ctx, OPC_SEB, rs, rt); 1110 break; 1111 case SEH: 1112 gen_bshfl(ctx, OPC_SEH, rs, rt); 1113 break; 1114 case CLO: 1115 mips32_op = OPC_CLO; 1116 goto do_cl; 1117 case CLZ: 1118 mips32_op = OPC_CLZ; 1119 do_cl: 1120 check_insn(ctx, ISA_MIPS_R1); 1121 gen_cl(ctx, mips32_op, rt, rs); 1122 break; 1123 case RDHWR: 1124 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1125 gen_rdhwr(ctx, rt, rs, 0); 1126 break; 1127 case WSBH: 1128 gen_bshfl(ctx, OPC_WSBH, rs, rt); 1129 break; 1130 case MULT: 1131 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1132 mips32_op = OPC_MULT; 1133 goto do_mul; 1134 case MULTU: 1135 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1136 mips32_op = OPC_MULTU; 1137 goto do_mul; 1138 case DIV: 1139 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1140 mips32_op = OPC_DIV; 1141 goto do_div; 1142 case DIVU: 1143 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1144 mips32_op = OPC_DIVU; 1145 goto do_div; 1146 do_div: 1147 check_insn(ctx, ISA_MIPS_R1); 1148 gen_muldiv(ctx, mips32_op, 0, rs, rt); 1149 break; 1150 case MADD: 1151 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1152 mips32_op = OPC_MADD; 1153 goto do_mul; 1154 case MADDU: 1155 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1156 mips32_op = OPC_MADDU; 1157 goto do_mul; 1158 case MSUB: 1159 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1160 mips32_op = OPC_MSUB; 1161 goto do_mul; 1162 case MSUBU: 1163 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1164 mips32_op = OPC_MSUBU; 1165 do_mul: 1166 check_insn(ctx, ISA_MIPS_R1); 1167 gen_muldiv(ctx, mips32_op, 0, rs, rt); 1168 break; 1169 default: 1170 goto pool32axf_invalid; 1171 } 1172 break; 1173 case 0x34: 1174 switch (minor) { 1175 case MFC2: 1176 case MTC2: 1177 case MFHC2: 1178 case MTHC2: 1179 case CFC2: 1180 case CTC2: 1181 generate_exception_err(ctx, EXCP_CpU, 2); 1182 break; 1183 default: 1184 goto pool32axf_invalid; 1185 } 1186 break; 1187 case 0x3c: 1188 switch (minor) { 1189 case JALR: /* JALRC */ 1190 case JALR_HB: /* JALRC_HB */ 1191 if (ctx->insn_flags & ISA_MIPS_R6) { 1192 /* JALRC, JALRC_HB */ 1193 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0); 1194 } else { 1195 /* JALR, JALR_HB */ 1196 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 4); 1197 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 1198 } 1199 break; 1200 case JALRS: 1201 case JALRS_HB: 1202 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1203 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2); 1204 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 1205 break; 1206 default: 1207 goto pool32axf_invalid; 1208 } 1209 break; 1210 case 0x05: 1211 switch (minor) { 1212 case RDPGPR: 1213 check_cp0_enabled(ctx); 1214 check_insn(ctx, ISA_MIPS_R2); 1215 gen_load_srsgpr(rs, rt); 1216 break; 1217 case WRPGPR: 1218 check_cp0_enabled(ctx); 1219 check_insn(ctx, ISA_MIPS_R2); 1220 gen_store_srsgpr(rs, rt); 1221 break; 1222 default: 1223 goto pool32axf_invalid; 1224 } 1225 break; 1226#ifndef CONFIG_USER_ONLY 1227 case 0x0d: 1228 switch (minor) { 1229 case TLBP: 1230 mips32_op = OPC_TLBP; 1231 goto do_cp0; 1232 case TLBR: 1233 mips32_op = OPC_TLBR; 1234 goto do_cp0; 1235 case TLBWI: 1236 mips32_op = OPC_TLBWI; 1237 goto do_cp0; 1238 case TLBWR: 1239 mips32_op = OPC_TLBWR; 1240 goto do_cp0; 1241 case TLBINV: 1242 mips32_op = OPC_TLBINV; 1243 goto do_cp0; 1244 case TLBINVF: 1245 mips32_op = OPC_TLBINVF; 1246 goto do_cp0; 1247 case WAIT: 1248 mips32_op = OPC_WAIT; 1249 goto do_cp0; 1250 case DERET: 1251 mips32_op = OPC_DERET; 1252 goto do_cp0; 1253 case ERET: 1254 mips32_op = OPC_ERET; 1255 do_cp0: 1256 gen_cp0(env, ctx, mips32_op, rt, rs); 1257 break; 1258 default: 1259 goto pool32axf_invalid; 1260 } 1261 break; 1262 case 0x1d: 1263 switch (minor) { 1264 case DI: 1265 check_cp0_enabled(ctx); 1266 { 1267 TCGv t0 = tcg_temp_new(); 1268 1269 save_cpu_state(ctx, 1); 1270 gen_helper_di(t0, tcg_env); 1271 gen_store_gpr(t0, rs); 1272 /* 1273 * Stop translation as we may have switched the execution 1274 * mode. 1275 */ 1276 ctx->base.is_jmp = DISAS_STOP; 1277 } 1278 break; 1279 case EI: 1280 check_cp0_enabled(ctx); 1281 { 1282 TCGv t0 = tcg_temp_new(); 1283 1284 save_cpu_state(ctx, 1); 1285 gen_helper_ei(t0, tcg_env); 1286 gen_store_gpr(t0, rs); 1287 /* 1288 * DISAS_STOP isn't sufficient, we need to ensure we break out 1289 * of translated code to check for pending interrupts. 1290 */ 1291 gen_save_pc(ctx->base.pc_next + 4); 1292 ctx->base.is_jmp = DISAS_EXIT; 1293 } 1294 break; 1295 default: 1296 goto pool32axf_invalid; 1297 } 1298 break; 1299#endif 1300 case 0x2d: 1301 switch (minor) { 1302 case SYNC: 1303 gen_sync(extract32(ctx->opcode, 16, 5)); 1304 break; 1305 case SYSCALL: 1306 generate_exception_end(ctx, EXCP_SYSCALL); 1307 break; 1308 case SDBBP: 1309 if (is_uhi(ctx, extract32(ctx->opcode, 16, 10))) { 1310 ctx->base.is_jmp = DISAS_SEMIHOST; 1311 } else { 1312 check_insn(ctx, ISA_MIPS_R1); 1313 if (ctx->hflags & MIPS_HFLAG_SBRI) { 1314 gen_reserved_instruction(ctx); 1315 } else { 1316 generate_exception_end(ctx, EXCP_DBp); 1317 } 1318 } 1319 break; 1320 default: 1321 goto pool32axf_invalid; 1322 } 1323 break; 1324 case 0x01: 1325 switch (minor & 3) { 1326 case MFHI_ACC: 1327 gen_HILO(ctx, OPC_MFHI, minor >> 2, rs); 1328 break; 1329 case MFLO_ACC: 1330 gen_HILO(ctx, OPC_MFLO, minor >> 2, rs); 1331 break; 1332 case MTHI_ACC: 1333 gen_HILO(ctx, OPC_MTHI, minor >> 2, rs); 1334 break; 1335 case MTLO_ACC: 1336 gen_HILO(ctx, OPC_MTLO, minor >> 2, rs); 1337 break; 1338 default: 1339 goto pool32axf_invalid; 1340 } 1341 break; 1342 case 0x35: 1343 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1344 switch (minor) { 1345 case MFHI32: 1346 gen_HILO(ctx, OPC_MFHI, 0, rs); 1347 break; 1348 case MFLO32: 1349 gen_HILO(ctx, OPC_MFLO, 0, rs); 1350 break; 1351 case MTHI32: 1352 gen_HILO(ctx, OPC_MTHI, 0, rs); 1353 break; 1354 case MTLO32: 1355 gen_HILO(ctx, OPC_MTLO, 0, rs); 1356 break; 1357 default: 1358 goto pool32axf_invalid; 1359 } 1360 break; 1361 default: 1362 pool32axf_invalid: 1363 MIPS_INVAL("pool32axf"); 1364 gen_reserved_instruction(ctx); 1365 break; 1366 } 1367} 1368 1369static void gen_pool32fxf(DisasContext *ctx, int rt, int rs) 1370{ 1371 int extension = (ctx->opcode >> 6) & 0x3ff; 1372 uint32_t mips32_op; 1373 1374#define FLOAT_1BIT_FMT(opc, fmt) ((fmt << 8) | opc) 1375#define FLOAT_2BIT_FMT(opc, fmt) ((fmt << 7) | opc) 1376#define COND_FLOAT_MOV(opc, cond) ((cond << 7) | opc) 1377 1378 switch (extension) { 1379 case FLOAT_1BIT_FMT(CFC1, 0): 1380 mips32_op = OPC_CFC1; 1381 goto do_cp1; 1382 case FLOAT_1BIT_FMT(CTC1, 0): 1383 mips32_op = OPC_CTC1; 1384 goto do_cp1; 1385 case FLOAT_1BIT_FMT(MFC1, 0): 1386 mips32_op = OPC_MFC1; 1387 goto do_cp1; 1388 case FLOAT_1BIT_FMT(MTC1, 0): 1389 mips32_op = OPC_MTC1; 1390 goto do_cp1; 1391 case FLOAT_1BIT_FMT(MFHC1, 0): 1392 mips32_op = OPC_MFHC1; 1393 goto do_cp1; 1394 case FLOAT_1BIT_FMT(MTHC1, 0): 1395 mips32_op = OPC_MTHC1; 1396 do_cp1: 1397 gen_cp1(ctx, mips32_op, rt, rs); 1398 break; 1399 1400 /* Reciprocal square root */ 1401 case FLOAT_1BIT_FMT(RSQRT_FMT, FMT_SD_S): 1402 mips32_op = OPC_RSQRT_S; 1403 goto do_unaryfp; 1404 case FLOAT_1BIT_FMT(RSQRT_FMT, FMT_SD_D): 1405 mips32_op = OPC_RSQRT_D; 1406 goto do_unaryfp; 1407 1408 /* Square root */ 1409 case FLOAT_1BIT_FMT(SQRT_FMT, FMT_SD_S): 1410 mips32_op = OPC_SQRT_S; 1411 goto do_unaryfp; 1412 case FLOAT_1BIT_FMT(SQRT_FMT, FMT_SD_D): 1413 mips32_op = OPC_SQRT_D; 1414 goto do_unaryfp; 1415 1416 /* Reciprocal */ 1417 case FLOAT_1BIT_FMT(RECIP_FMT, FMT_SD_S): 1418 mips32_op = OPC_RECIP_S; 1419 goto do_unaryfp; 1420 case FLOAT_1BIT_FMT(RECIP_FMT, FMT_SD_D): 1421 mips32_op = OPC_RECIP_D; 1422 goto do_unaryfp; 1423 1424 /* Floor */ 1425 case FLOAT_1BIT_FMT(FLOOR_L, FMT_SD_S): 1426 mips32_op = OPC_FLOOR_L_S; 1427 goto do_unaryfp; 1428 case FLOAT_1BIT_FMT(FLOOR_L, FMT_SD_D): 1429 mips32_op = OPC_FLOOR_L_D; 1430 goto do_unaryfp; 1431 case FLOAT_1BIT_FMT(FLOOR_W, FMT_SD_S): 1432 mips32_op = OPC_FLOOR_W_S; 1433 goto do_unaryfp; 1434 case FLOAT_1BIT_FMT(FLOOR_W, FMT_SD_D): 1435 mips32_op = OPC_FLOOR_W_D; 1436 goto do_unaryfp; 1437 1438 /* Ceiling */ 1439 case FLOAT_1BIT_FMT(CEIL_L, FMT_SD_S): 1440 mips32_op = OPC_CEIL_L_S; 1441 goto do_unaryfp; 1442 case FLOAT_1BIT_FMT(CEIL_L, FMT_SD_D): 1443 mips32_op = OPC_CEIL_L_D; 1444 goto do_unaryfp; 1445 case FLOAT_1BIT_FMT(CEIL_W, FMT_SD_S): 1446 mips32_op = OPC_CEIL_W_S; 1447 goto do_unaryfp; 1448 case FLOAT_1BIT_FMT(CEIL_W, FMT_SD_D): 1449 mips32_op = OPC_CEIL_W_D; 1450 goto do_unaryfp; 1451 1452 /* Truncation */ 1453 case FLOAT_1BIT_FMT(TRUNC_L, FMT_SD_S): 1454 mips32_op = OPC_TRUNC_L_S; 1455 goto do_unaryfp; 1456 case FLOAT_1BIT_FMT(TRUNC_L, FMT_SD_D): 1457 mips32_op = OPC_TRUNC_L_D; 1458 goto do_unaryfp; 1459 case FLOAT_1BIT_FMT(TRUNC_W, FMT_SD_S): 1460 mips32_op = OPC_TRUNC_W_S; 1461 goto do_unaryfp; 1462 case FLOAT_1BIT_FMT(TRUNC_W, FMT_SD_D): 1463 mips32_op = OPC_TRUNC_W_D; 1464 goto do_unaryfp; 1465 1466 /* Round */ 1467 case FLOAT_1BIT_FMT(ROUND_L, FMT_SD_S): 1468 mips32_op = OPC_ROUND_L_S; 1469 goto do_unaryfp; 1470 case FLOAT_1BIT_FMT(ROUND_L, FMT_SD_D): 1471 mips32_op = OPC_ROUND_L_D; 1472 goto do_unaryfp; 1473 case FLOAT_1BIT_FMT(ROUND_W, FMT_SD_S): 1474 mips32_op = OPC_ROUND_W_S; 1475 goto do_unaryfp; 1476 case FLOAT_1BIT_FMT(ROUND_W, FMT_SD_D): 1477 mips32_op = OPC_ROUND_W_D; 1478 goto do_unaryfp; 1479 1480 /* Integer to floating-point conversion */ 1481 case FLOAT_1BIT_FMT(CVT_L, FMT_SD_S): 1482 mips32_op = OPC_CVT_L_S; 1483 goto do_unaryfp; 1484 case FLOAT_1BIT_FMT(CVT_L, FMT_SD_D): 1485 mips32_op = OPC_CVT_L_D; 1486 goto do_unaryfp; 1487 case FLOAT_1BIT_FMT(CVT_W, FMT_SD_S): 1488 mips32_op = OPC_CVT_W_S; 1489 goto do_unaryfp; 1490 case FLOAT_1BIT_FMT(CVT_W, FMT_SD_D): 1491 mips32_op = OPC_CVT_W_D; 1492 goto do_unaryfp; 1493 1494 /* Paired-foo conversions */ 1495 case FLOAT_1BIT_FMT(CVT_S_PL, 0): 1496 mips32_op = OPC_CVT_S_PL; 1497 goto do_unaryfp; 1498 case FLOAT_1BIT_FMT(CVT_S_PU, 0): 1499 mips32_op = OPC_CVT_S_PU; 1500 goto do_unaryfp; 1501 case FLOAT_1BIT_FMT(CVT_PW_PS, 0): 1502 mips32_op = OPC_CVT_PW_PS; 1503 goto do_unaryfp; 1504 case FLOAT_1BIT_FMT(CVT_PS_PW, 0): 1505 mips32_op = OPC_CVT_PS_PW; 1506 goto do_unaryfp; 1507 1508 /* Floating-point moves */ 1509 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_S): 1510 mips32_op = OPC_MOV_S; 1511 goto do_unaryfp; 1512 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_D): 1513 mips32_op = OPC_MOV_D; 1514 goto do_unaryfp; 1515 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_PS): 1516 mips32_op = OPC_MOV_PS; 1517 goto do_unaryfp; 1518 1519 /* Absolute value */ 1520 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_S): 1521 mips32_op = OPC_ABS_S; 1522 goto do_unaryfp; 1523 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_D): 1524 mips32_op = OPC_ABS_D; 1525 goto do_unaryfp; 1526 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_PS): 1527 mips32_op = OPC_ABS_PS; 1528 goto do_unaryfp; 1529 1530 /* Negation */ 1531 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_S): 1532 mips32_op = OPC_NEG_S; 1533 goto do_unaryfp; 1534 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_D): 1535 mips32_op = OPC_NEG_D; 1536 goto do_unaryfp; 1537 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_PS): 1538 mips32_op = OPC_NEG_PS; 1539 goto do_unaryfp; 1540 1541 /* Reciprocal square root step */ 1542 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_S): 1543 mips32_op = OPC_RSQRT1_S; 1544 goto do_unaryfp; 1545 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_D): 1546 mips32_op = OPC_RSQRT1_D; 1547 goto do_unaryfp; 1548 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_PS): 1549 mips32_op = OPC_RSQRT1_PS; 1550 goto do_unaryfp; 1551 1552 /* Reciprocal step */ 1553 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_S): 1554 mips32_op = OPC_RECIP1_S; 1555 goto do_unaryfp; 1556 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_D): 1557 mips32_op = OPC_RECIP1_S; 1558 goto do_unaryfp; 1559 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_PS): 1560 mips32_op = OPC_RECIP1_PS; 1561 goto do_unaryfp; 1562 1563 /* Conversions from double */ 1564 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_S): 1565 mips32_op = OPC_CVT_D_S; 1566 goto do_unaryfp; 1567 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_W): 1568 mips32_op = OPC_CVT_D_W; 1569 goto do_unaryfp; 1570 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_L): 1571 mips32_op = OPC_CVT_D_L; 1572 goto do_unaryfp; 1573 1574 /* Conversions from single */ 1575 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_D): 1576 mips32_op = OPC_CVT_S_D; 1577 goto do_unaryfp; 1578 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_W): 1579 mips32_op = OPC_CVT_S_W; 1580 goto do_unaryfp; 1581 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_L): 1582 mips32_op = OPC_CVT_S_L; 1583 do_unaryfp: 1584 gen_farith(ctx, mips32_op, -1, rs, rt, 0); 1585 break; 1586 1587 /* Conditional moves on floating-point codes */ 1588 case COND_FLOAT_MOV(MOVT, 0): 1589 case COND_FLOAT_MOV(MOVT, 1): 1590 case COND_FLOAT_MOV(MOVT, 2): 1591 case COND_FLOAT_MOV(MOVT, 3): 1592 case COND_FLOAT_MOV(MOVT, 4): 1593 case COND_FLOAT_MOV(MOVT, 5): 1594 case COND_FLOAT_MOV(MOVT, 6): 1595 case COND_FLOAT_MOV(MOVT, 7): 1596 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1597 gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 1); 1598 break; 1599 case COND_FLOAT_MOV(MOVF, 0): 1600 case COND_FLOAT_MOV(MOVF, 1): 1601 case COND_FLOAT_MOV(MOVF, 2): 1602 case COND_FLOAT_MOV(MOVF, 3): 1603 case COND_FLOAT_MOV(MOVF, 4): 1604 case COND_FLOAT_MOV(MOVF, 5): 1605 case COND_FLOAT_MOV(MOVF, 6): 1606 case COND_FLOAT_MOV(MOVF, 7): 1607 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1608 gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 0); 1609 break; 1610 default: 1611 MIPS_INVAL("pool32fxf"); 1612 gen_reserved_instruction(ctx); 1613 break; 1614 } 1615} 1616 1617static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) 1618{ 1619 int32_t offset; 1620 uint16_t insn; 1621 int rt, rs, rd, rr; 1622 int16_t imm; 1623 uint32_t op, minor, minor2, mips32_op; 1624 uint32_t cond, fmt, cc; 1625 1626 insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2); 1627 ctx->opcode = (ctx->opcode << 16) | insn; 1628 1629 rt = (ctx->opcode >> 21) & 0x1f; 1630 rs = (ctx->opcode >> 16) & 0x1f; 1631 rd = (ctx->opcode >> 11) & 0x1f; 1632 rr = (ctx->opcode >> 6) & 0x1f; 1633 imm = (int16_t) ctx->opcode; 1634 1635 op = (ctx->opcode >> 26) & 0x3f; 1636 switch (op) { 1637 case POOL32A: 1638 minor = ctx->opcode & 0x3f; 1639 switch (minor) { 1640 case 0x00: 1641 minor = (ctx->opcode >> 6) & 0xf; 1642 switch (minor) { 1643 case SLL32: 1644 mips32_op = OPC_SLL; 1645 goto do_shifti; 1646 case SRA: 1647 mips32_op = OPC_SRA; 1648 goto do_shifti; 1649 case SRL32: 1650 mips32_op = OPC_SRL; 1651 goto do_shifti; 1652 case ROTR: 1653 mips32_op = OPC_ROTR; 1654 do_shifti: 1655 gen_shift_imm(ctx, mips32_op, rt, rs, rd); 1656 break; 1657 case SELEQZ: 1658 check_insn(ctx, ISA_MIPS_R6); 1659 gen_cond_move(ctx, OPC_SELEQZ, rd, rs, rt); 1660 break; 1661 case SELNEZ: 1662 check_insn(ctx, ISA_MIPS_R6); 1663 gen_cond_move(ctx, OPC_SELNEZ, rd, rs, rt); 1664 break; 1665 case R6_RDHWR: 1666 check_insn(ctx, ISA_MIPS_R6); 1667 gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3)); 1668 break; 1669 default: 1670 goto pool32a_invalid; 1671 } 1672 break; 1673 case 0x10: 1674 minor = (ctx->opcode >> 6) & 0xf; 1675 switch (minor) { 1676 /* Arithmetic */ 1677 case ADD: 1678 mips32_op = OPC_ADD; 1679 goto do_arith; 1680 case ADDU32: 1681 mips32_op = OPC_ADDU; 1682 goto do_arith; 1683 case SUB: 1684 mips32_op = OPC_SUB; 1685 goto do_arith; 1686 case SUBU32: 1687 mips32_op = OPC_SUBU; 1688 goto do_arith; 1689 case MUL: 1690 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1691 mips32_op = OPC_MUL; 1692 do_arith: 1693 gen_arith(ctx, mips32_op, rd, rs, rt); 1694 break; 1695 /* Shifts */ 1696 case SLLV: 1697 mips32_op = OPC_SLLV; 1698 goto do_shift; 1699 case SRLV: 1700 mips32_op = OPC_SRLV; 1701 goto do_shift; 1702 case SRAV: 1703 mips32_op = OPC_SRAV; 1704 goto do_shift; 1705 case ROTRV: 1706 mips32_op = OPC_ROTRV; 1707 do_shift: 1708 gen_shift(ctx, mips32_op, rd, rs, rt); 1709 break; 1710 /* Logical operations */ 1711 case AND: 1712 mips32_op = OPC_AND; 1713 goto do_logic; 1714 case OR32: 1715 mips32_op = OPC_OR; 1716 goto do_logic; 1717 case NOR: 1718 mips32_op = OPC_NOR; 1719 goto do_logic; 1720 case XOR32: 1721 mips32_op = OPC_XOR; 1722 do_logic: 1723 gen_logic(ctx, mips32_op, rd, rs, rt); 1724 break; 1725 /* Set less than */ 1726 case SLT: 1727 mips32_op = OPC_SLT; 1728 goto do_slt; 1729 case SLTU: 1730 mips32_op = OPC_SLTU; 1731 do_slt: 1732 gen_slt(ctx, mips32_op, rd, rs, rt); 1733 break; 1734 default: 1735 goto pool32a_invalid; 1736 } 1737 break; 1738 case 0x18: 1739 minor = (ctx->opcode >> 6) & 0xf; 1740 switch (minor) { 1741 /* Conditional moves */ 1742 case MOVN: /* MUL */ 1743 if (ctx->insn_flags & ISA_MIPS_R6) { 1744 /* MUL */ 1745 gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt); 1746 } else { 1747 /* MOVN */ 1748 gen_cond_move(ctx, OPC_MOVN, rd, rs, rt); 1749 } 1750 break; 1751 case MOVZ: /* MUH */ 1752 if (ctx->insn_flags & ISA_MIPS_R6) { 1753 /* MUH */ 1754 gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt); 1755 } else { 1756 /* MOVZ */ 1757 gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt); 1758 } 1759 break; 1760 case MULU: 1761 check_insn(ctx, ISA_MIPS_R6); 1762 gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt); 1763 break; 1764 case MUHU: 1765 check_insn(ctx, ISA_MIPS_R6); 1766 gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt); 1767 break; 1768 case LWXS: /* DIV */ 1769 if (ctx->insn_flags & ISA_MIPS_R6) { 1770 /* DIV */ 1771 gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt); 1772 } else { 1773 /* LWXS */ 1774 gen_ldxs(ctx, rs, rt, rd); 1775 } 1776 break; 1777 case MOD: 1778 check_insn(ctx, ISA_MIPS_R6); 1779 gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt); 1780 break; 1781 case R6_DIVU: 1782 check_insn(ctx, ISA_MIPS_R6); 1783 gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt); 1784 break; 1785 case MODU: 1786 check_insn(ctx, ISA_MIPS_R6); 1787 gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt); 1788 break; 1789 default: 1790 goto pool32a_invalid; 1791 } 1792 break; 1793 case INS: 1794 gen_bitops(ctx, OPC_INS, rt, rs, rr, rd); 1795 return; 1796 case LSA: 1797 check_insn(ctx, ISA_MIPS_R6); 1798 gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2)); 1799 break; 1800 case ALIGN: 1801 check_insn(ctx, ISA_MIPS_R6); 1802 gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2)); 1803 break; 1804 case EXT: 1805 gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd); 1806 return; 1807 case POOL32AXF: 1808 gen_pool32axf(env, ctx, rt, rs); 1809 break; 1810 case BREAK32: 1811 generate_exception_break(ctx, extract32(ctx->opcode, 6, 20)); 1812 break; 1813 case SIGRIE: 1814 check_insn(ctx, ISA_MIPS_R6); 1815 gen_reserved_instruction(ctx); 1816 break; 1817 default: 1818 pool32a_invalid: 1819 MIPS_INVAL("pool32a"); 1820 gen_reserved_instruction(ctx); 1821 break; 1822 } 1823 break; 1824 case POOL32B: 1825 minor = (ctx->opcode >> 12) & 0xf; 1826 switch (minor) { 1827 case CACHE: 1828 check_cp0_enabled(ctx); 1829 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 1830 gen_cache_operation(ctx, rt, rs, imm); 1831 } 1832 break; 1833 case LWC2: 1834 case SWC2: 1835 /* COP2: Not implemented. */ 1836 generate_exception_err(ctx, EXCP_CpU, 2); 1837 break; 1838#ifdef TARGET_MIPS64 1839 case LDP: 1840 case SDP: 1841 check_insn(ctx, ISA_MIPS3); 1842 check_mips_64(ctx); 1843#endif 1844 /* fall through */ 1845 case LWP: 1846 case SWP: 1847 gen_ldst_pair(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12)); 1848 break; 1849#ifdef TARGET_MIPS64 1850 case LDM: 1851 case SDM: 1852 check_insn(ctx, ISA_MIPS3); 1853 check_mips_64(ctx); 1854#endif 1855 /* fall through */ 1856 case LWM32: 1857 case SWM32: 1858 gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12)); 1859 break; 1860 default: 1861 MIPS_INVAL("pool32b"); 1862 gen_reserved_instruction(ctx); 1863 break; 1864 } 1865 break; 1866 case POOL32F: 1867 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { 1868 minor = ctx->opcode & 0x3f; 1869 check_cp1_enabled(ctx); 1870 switch (minor) { 1871 case ALNV_PS: 1872 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1873 mips32_op = OPC_ALNV_PS; 1874 goto do_madd; 1875 case MADD_S: 1876 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1877 mips32_op = OPC_MADD_S; 1878 goto do_madd; 1879 case MADD_D: 1880 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1881 mips32_op = OPC_MADD_D; 1882 goto do_madd; 1883 case MADD_PS: 1884 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1885 mips32_op = OPC_MADD_PS; 1886 goto do_madd; 1887 case MSUB_S: 1888 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1889 mips32_op = OPC_MSUB_S; 1890 goto do_madd; 1891 case MSUB_D: 1892 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1893 mips32_op = OPC_MSUB_D; 1894 goto do_madd; 1895 case MSUB_PS: 1896 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1897 mips32_op = OPC_MSUB_PS; 1898 goto do_madd; 1899 case NMADD_S: 1900 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1901 mips32_op = OPC_NMADD_S; 1902 goto do_madd; 1903 case NMADD_D: 1904 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1905 mips32_op = OPC_NMADD_D; 1906 goto do_madd; 1907 case NMADD_PS: 1908 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1909 mips32_op = OPC_NMADD_PS; 1910 goto do_madd; 1911 case NMSUB_S: 1912 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1913 mips32_op = OPC_NMSUB_S; 1914 goto do_madd; 1915 case NMSUB_D: 1916 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1917 mips32_op = OPC_NMSUB_D; 1918 goto do_madd; 1919 case NMSUB_PS: 1920 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1921 mips32_op = OPC_NMSUB_PS; 1922 do_madd: 1923 gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt); 1924 break; 1925 case CABS_COND_FMT: 1926 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1927 cond = (ctx->opcode >> 6) & 0xf; 1928 cc = (ctx->opcode >> 13) & 0x7; 1929 fmt = (ctx->opcode >> 10) & 0x3; 1930 switch (fmt) { 1931 case 0x0: 1932 gen_cmpabs_s(ctx, cond, rt, rs, cc); 1933 break; 1934 case 0x1: 1935 gen_cmpabs_d(ctx, cond, rt, rs, cc); 1936 break; 1937 case 0x2: 1938 gen_cmpabs_ps(ctx, cond, rt, rs, cc); 1939 break; 1940 default: 1941 goto pool32f_invalid; 1942 } 1943 break; 1944 case C_COND_FMT: 1945 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1946 cond = (ctx->opcode >> 6) & 0xf; 1947 cc = (ctx->opcode >> 13) & 0x7; 1948 fmt = (ctx->opcode >> 10) & 0x3; 1949 switch (fmt) { 1950 case 0x0: 1951 gen_cmp_s(ctx, cond, rt, rs, cc); 1952 break; 1953 case 0x1: 1954 gen_cmp_d(ctx, cond, rt, rs, cc); 1955 break; 1956 case 0x2: 1957 gen_cmp_ps(ctx, cond, rt, rs, cc); 1958 break; 1959 default: 1960 goto pool32f_invalid; 1961 } 1962 break; 1963 case CMP_CONDN_S: 1964 check_insn(ctx, ISA_MIPS_R6); 1965 gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); 1966 break; 1967 case CMP_CONDN_D: 1968 check_insn(ctx, ISA_MIPS_R6); 1969 gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); 1970 break; 1971 case POOL32FXF: 1972 gen_pool32fxf(ctx, rt, rs); 1973 break; 1974 case 0x00: 1975 /* PLL foo */ 1976 switch ((ctx->opcode >> 6) & 0x7) { 1977 case PLL_PS: 1978 mips32_op = OPC_PLL_PS; 1979 goto do_ps; 1980 case PLU_PS: 1981 mips32_op = OPC_PLU_PS; 1982 goto do_ps; 1983 case PUL_PS: 1984 mips32_op = OPC_PUL_PS; 1985 goto do_ps; 1986 case PUU_PS: 1987 mips32_op = OPC_PUU_PS; 1988 goto do_ps; 1989 case CVT_PS_S: 1990 check_insn_opc_removed(ctx, ISA_MIPS_R6); 1991 mips32_op = OPC_CVT_PS_S; 1992 do_ps: 1993 gen_farith(ctx, mips32_op, rt, rs, rd, 0); 1994 break; 1995 default: 1996 goto pool32f_invalid; 1997 } 1998 break; 1999 case MIN_FMT: 2000 check_insn(ctx, ISA_MIPS_R6); 2001 switch ((ctx->opcode >> 9) & 0x3) { 2002 case FMT_SDPS_S: 2003 gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0); 2004 break; 2005 case FMT_SDPS_D: 2006 gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0); 2007 break; 2008 default: 2009 goto pool32f_invalid; 2010 } 2011 break; 2012 case 0x08: 2013 /* [LS][WDU]XC1 */ 2014 switch ((ctx->opcode >> 6) & 0x7) { 2015 case LWXC1: 2016 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2017 mips32_op = OPC_LWXC1; 2018 goto do_ldst_cp1; 2019 case SWXC1: 2020 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2021 mips32_op = OPC_SWXC1; 2022 goto do_ldst_cp1; 2023 case LDXC1: 2024 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2025 mips32_op = OPC_LDXC1; 2026 goto do_ldst_cp1; 2027 case SDXC1: 2028 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2029 mips32_op = OPC_SDXC1; 2030 goto do_ldst_cp1; 2031 case LUXC1: 2032 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2033 mips32_op = OPC_LUXC1; 2034 goto do_ldst_cp1; 2035 case SUXC1: 2036 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2037 mips32_op = OPC_SUXC1; 2038 do_ldst_cp1: 2039 gen_flt3_ldst(ctx, mips32_op, rd, rd, rt, rs); 2040 break; 2041 default: 2042 goto pool32f_invalid; 2043 } 2044 break; 2045 case MAX_FMT: 2046 check_insn(ctx, ISA_MIPS_R6); 2047 switch ((ctx->opcode >> 9) & 0x3) { 2048 case FMT_SDPS_S: 2049 gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0); 2050 break; 2051 case FMT_SDPS_D: 2052 gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0); 2053 break; 2054 default: 2055 goto pool32f_invalid; 2056 } 2057 break; 2058 case 0x18: 2059 /* 3D insns */ 2060 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2061 fmt = (ctx->opcode >> 9) & 0x3; 2062 switch ((ctx->opcode >> 6) & 0x7) { 2063 case RSQRT2_FMT: 2064 switch (fmt) { 2065 case FMT_SDPS_S: 2066 mips32_op = OPC_RSQRT2_S; 2067 goto do_3d; 2068 case FMT_SDPS_D: 2069 mips32_op = OPC_RSQRT2_D; 2070 goto do_3d; 2071 case FMT_SDPS_PS: 2072 mips32_op = OPC_RSQRT2_PS; 2073 goto do_3d; 2074 default: 2075 goto pool32f_invalid; 2076 } 2077 break; 2078 case RECIP2_FMT: 2079 switch (fmt) { 2080 case FMT_SDPS_S: 2081 mips32_op = OPC_RECIP2_S; 2082 goto do_3d; 2083 case FMT_SDPS_D: 2084 mips32_op = OPC_RECIP2_D; 2085 goto do_3d; 2086 case FMT_SDPS_PS: 2087 mips32_op = OPC_RECIP2_PS; 2088 goto do_3d; 2089 default: 2090 goto pool32f_invalid; 2091 } 2092 break; 2093 case ADDR_PS: 2094 mips32_op = OPC_ADDR_PS; 2095 goto do_3d; 2096 case MULR_PS: 2097 mips32_op = OPC_MULR_PS; 2098 do_3d: 2099 gen_farith(ctx, mips32_op, rt, rs, rd, 0); 2100 break; 2101 default: 2102 goto pool32f_invalid; 2103 } 2104 break; 2105 case 0x20: 2106 /* MOV[FT].fmt, PREFX, RINT.fmt, CLASS.fmt*/ 2107 cc = (ctx->opcode >> 13) & 0x7; 2108 fmt = (ctx->opcode >> 9) & 0x3; 2109 switch ((ctx->opcode >> 6) & 0x7) { 2110 case MOVF_FMT: /* RINT_FMT */ 2111 if (ctx->insn_flags & ISA_MIPS_R6) { 2112 /* RINT_FMT */ 2113 switch (fmt) { 2114 case FMT_SDPS_S: 2115 gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0); 2116 break; 2117 case FMT_SDPS_D: 2118 gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0); 2119 break; 2120 default: 2121 goto pool32f_invalid; 2122 } 2123 } else { 2124 /* MOVF_FMT */ 2125 switch (fmt) { 2126 case FMT_SDPS_S: 2127 gen_movcf_s(ctx, rs, rt, cc, 0); 2128 break; 2129 case FMT_SDPS_D: 2130 gen_movcf_d(ctx, rs, rt, cc, 0); 2131 break; 2132 case FMT_SDPS_PS: 2133 check_ps(ctx); 2134 gen_movcf_ps(ctx, rs, rt, cc, 0); 2135 break; 2136 default: 2137 goto pool32f_invalid; 2138 } 2139 } 2140 break; 2141 case MOVT_FMT: /* CLASS_FMT */ 2142 if (ctx->insn_flags & ISA_MIPS_R6) { 2143 /* CLASS_FMT */ 2144 switch (fmt) { 2145 case FMT_SDPS_S: 2146 gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0); 2147 break; 2148 case FMT_SDPS_D: 2149 gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0); 2150 break; 2151 default: 2152 goto pool32f_invalid; 2153 } 2154 } else { 2155 /* MOVT_FMT */ 2156 switch (fmt) { 2157 case FMT_SDPS_S: 2158 gen_movcf_s(ctx, rs, rt, cc, 1); 2159 break; 2160 case FMT_SDPS_D: 2161 gen_movcf_d(ctx, rs, rt, cc, 1); 2162 break; 2163 case FMT_SDPS_PS: 2164 check_ps(ctx); 2165 gen_movcf_ps(ctx, rs, rt, cc, 1); 2166 break; 2167 default: 2168 goto pool32f_invalid; 2169 } 2170 } 2171 break; 2172 case PREFX: 2173 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2174 break; 2175 default: 2176 goto pool32f_invalid; 2177 } 2178 break; 2179#define FINSN_3ARG_SDPS(prfx) \ 2180 switch ((ctx->opcode >> 8) & 0x3) { \ 2181 case FMT_SDPS_S: \ 2182 mips32_op = OPC_##prfx##_S; \ 2183 goto do_fpop; \ 2184 case FMT_SDPS_D: \ 2185 mips32_op = OPC_##prfx##_D; \ 2186 goto do_fpop; \ 2187 case FMT_SDPS_PS: \ 2188 check_ps(ctx); \ 2189 mips32_op = OPC_##prfx##_PS; \ 2190 goto do_fpop; \ 2191 default: \ 2192 goto pool32f_invalid; \ 2193 } 2194 case MINA_FMT: 2195 check_insn(ctx, ISA_MIPS_R6); 2196 switch ((ctx->opcode >> 9) & 0x3) { 2197 case FMT_SDPS_S: 2198 gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0); 2199 break; 2200 case FMT_SDPS_D: 2201 gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0); 2202 break; 2203 default: 2204 goto pool32f_invalid; 2205 } 2206 break; 2207 case MAXA_FMT: 2208 check_insn(ctx, ISA_MIPS_R6); 2209 switch ((ctx->opcode >> 9) & 0x3) { 2210 case FMT_SDPS_S: 2211 gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0); 2212 break; 2213 case FMT_SDPS_D: 2214 gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0); 2215 break; 2216 default: 2217 goto pool32f_invalid; 2218 } 2219 break; 2220 case 0x30: 2221 /* regular FP ops */ 2222 switch ((ctx->opcode >> 6) & 0x3) { 2223 case ADD_FMT: 2224 FINSN_3ARG_SDPS(ADD); 2225 break; 2226 case SUB_FMT: 2227 FINSN_3ARG_SDPS(SUB); 2228 break; 2229 case MUL_FMT: 2230 FINSN_3ARG_SDPS(MUL); 2231 break; 2232 case DIV_FMT: 2233 fmt = (ctx->opcode >> 8) & 0x3; 2234 if (fmt == 1) { 2235 mips32_op = OPC_DIV_D; 2236 } else if (fmt == 0) { 2237 mips32_op = OPC_DIV_S; 2238 } else { 2239 goto pool32f_invalid; 2240 } 2241 goto do_fpop; 2242 default: 2243 goto pool32f_invalid; 2244 } 2245 break; 2246 case 0x38: 2247 /* cmovs */ 2248 switch ((ctx->opcode >> 6) & 0x7) { 2249 case MOVN_FMT: /* SELEQZ_FMT */ 2250 if (ctx->insn_flags & ISA_MIPS_R6) { 2251 /* SELEQZ_FMT */ 2252 switch ((ctx->opcode >> 9) & 0x3) { 2253 case FMT_SDPS_S: 2254 gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs); 2255 break; 2256 case FMT_SDPS_D: 2257 gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs); 2258 break; 2259 default: 2260 goto pool32f_invalid; 2261 } 2262 } else { 2263 /* MOVN_FMT */ 2264 FINSN_3ARG_SDPS(MOVN); 2265 } 2266 break; 2267 case MOVN_FMT_04: 2268 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2269 FINSN_3ARG_SDPS(MOVN); 2270 break; 2271 case MOVZ_FMT: /* SELNEZ_FMT */ 2272 if (ctx->insn_flags & ISA_MIPS_R6) { 2273 /* SELNEZ_FMT */ 2274 switch ((ctx->opcode >> 9) & 0x3) { 2275 case FMT_SDPS_S: 2276 gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs); 2277 break; 2278 case FMT_SDPS_D: 2279 gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs); 2280 break; 2281 default: 2282 goto pool32f_invalid; 2283 } 2284 } else { 2285 /* MOVZ_FMT */ 2286 FINSN_3ARG_SDPS(MOVZ); 2287 } 2288 break; 2289 case MOVZ_FMT_05: 2290 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2291 FINSN_3ARG_SDPS(MOVZ); 2292 break; 2293 case SEL_FMT: 2294 check_insn(ctx, ISA_MIPS_R6); 2295 switch ((ctx->opcode >> 9) & 0x3) { 2296 case FMT_SDPS_S: 2297 gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs); 2298 break; 2299 case FMT_SDPS_D: 2300 gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs); 2301 break; 2302 default: 2303 goto pool32f_invalid; 2304 } 2305 break; 2306 case MADDF_FMT: 2307 check_insn(ctx, ISA_MIPS_R6); 2308 switch ((ctx->opcode >> 9) & 0x3) { 2309 case FMT_SDPS_S: 2310 mips32_op = OPC_MADDF_S; 2311 goto do_fpop; 2312 case FMT_SDPS_D: 2313 mips32_op = OPC_MADDF_D; 2314 goto do_fpop; 2315 default: 2316 goto pool32f_invalid; 2317 } 2318 break; 2319 case MSUBF_FMT: 2320 check_insn(ctx, ISA_MIPS_R6); 2321 switch ((ctx->opcode >> 9) & 0x3) { 2322 case FMT_SDPS_S: 2323 mips32_op = OPC_MSUBF_S; 2324 goto do_fpop; 2325 case FMT_SDPS_D: 2326 mips32_op = OPC_MSUBF_D; 2327 goto do_fpop; 2328 default: 2329 goto pool32f_invalid; 2330 } 2331 break; 2332 default: 2333 goto pool32f_invalid; 2334 } 2335 break; 2336 do_fpop: 2337 gen_farith(ctx, mips32_op, rt, rs, rd, 0); 2338 break; 2339 default: 2340 pool32f_invalid: 2341 MIPS_INVAL("pool32f"); 2342 gen_reserved_instruction(ctx); 2343 break; 2344 } 2345 } else { 2346 generate_exception_err(ctx, EXCP_CpU, 1); 2347 } 2348 break; 2349 case POOL32I: 2350 minor = (ctx->opcode >> 21) & 0x1f; 2351 switch (minor) { 2352 case BLTZ: 2353 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2354 gen_compute_branch(ctx, OPC_BLTZ, 4, rs, -1, imm << 1, 4); 2355 break; 2356 case BLTZAL: 2357 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2358 gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 4); 2359 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2360 break; 2361 case BLTZALS: 2362 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2363 gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 2); 2364 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2365 break; 2366 case BGEZ: 2367 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2368 gen_compute_branch(ctx, OPC_BGEZ, 4, rs, -1, imm << 1, 4); 2369 break; 2370 case BGEZAL: 2371 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2372 gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 4); 2373 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2374 break; 2375 case BGEZALS: 2376 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2377 gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 2); 2378 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2379 break; 2380 case BLEZ: 2381 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2382 gen_compute_branch(ctx, OPC_BLEZ, 4, rs, -1, imm << 1, 4); 2383 break; 2384 case BGTZ: 2385 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2386 gen_compute_branch(ctx, OPC_BGTZ, 4, rs, -1, imm << 1, 4); 2387 break; 2388 2389 /* Traps */ 2390 case TLTI: /* BC1EQZC */ 2391 if (ctx->insn_flags & ISA_MIPS_R6) { 2392 /* BC1EQZC */ 2393 check_cp1_enabled(ctx); 2394 gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rs, imm << 1, 0); 2395 } else { 2396 /* TLTI */ 2397 mips32_op = OPC_TLTI; 2398 goto do_trapi; 2399 } 2400 break; 2401 case TGEI: /* BC1NEZC */ 2402 if (ctx->insn_flags & ISA_MIPS_R6) { 2403 /* BC1NEZC */ 2404 check_cp1_enabled(ctx); 2405 gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rs, imm << 1, 0); 2406 } else { 2407 /* TGEI */ 2408 mips32_op = OPC_TGEI; 2409 goto do_trapi; 2410 } 2411 break; 2412 case TLTIU: 2413 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2414 mips32_op = OPC_TLTIU; 2415 goto do_trapi; 2416 case TGEIU: 2417 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2418 mips32_op = OPC_TGEIU; 2419 goto do_trapi; 2420 case TNEI: /* SYNCI */ 2421 if (ctx->insn_flags & ISA_MIPS_R6) { 2422 /* SYNCI */ 2423 /* 2424 * Break the TB to be able to sync copied instructions 2425 * immediately. 2426 */ 2427 ctx->base.is_jmp = DISAS_STOP; 2428 } else { 2429 /* TNEI */ 2430 mips32_op = OPC_TNEI; 2431 goto do_trapi; 2432 } 2433 break; 2434 case TEQI: 2435 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2436 mips32_op = OPC_TEQI; 2437 do_trapi: 2438 gen_trap(ctx, mips32_op, rs, -1, imm, 0); 2439 break; 2440 2441 case BNEZC: 2442 case BEQZC: 2443 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2444 gen_compute_branch(ctx, minor == BNEZC ? OPC_BNE : OPC_BEQ, 2445 4, rs, 0, imm << 1, 0); 2446 /* 2447 * Compact branches don't have a delay slot, so just let 2448 * the normal delay slot handling take us to the branch 2449 * target. 2450 */ 2451 break; 2452 case LUI: 2453 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2454 gen_logic_imm(ctx, OPC_LUI, rs, 0, imm); 2455 break; 2456 case SYNCI: 2457 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2458 /* 2459 * Break the TB to be able to sync copied instructions 2460 * immediately. 2461 */ 2462 ctx->base.is_jmp = DISAS_STOP; 2463 break; 2464 case BC2F: 2465 case BC2T: 2466 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2467 /* COP2: Not implemented. */ 2468 generate_exception_err(ctx, EXCP_CpU, 2); 2469 break; 2470 case BC1F: 2471 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2472 mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1FANY2 : OPC_BC1F; 2473 goto do_cp1branch; 2474 case BC1T: 2475 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2476 mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1TANY2 : OPC_BC1T; 2477 goto do_cp1branch; 2478 case BC1ANY4F: 2479 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2480 mips32_op = OPC_BC1FANY4; 2481 goto do_cp1mips3d; 2482 case BC1ANY4T: 2483 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2484 mips32_op = OPC_BC1TANY4; 2485 do_cp1mips3d: 2486 check_cop1x(ctx); 2487 if (!ase_3d_available(env)) { 2488 gen_reserved_instruction(ctx); 2489 break; 2490 } 2491 /* Fall through */ 2492 do_cp1branch: 2493 if (env->CP0_Config1 & (1 << CP0C1_FP)) { 2494 check_cp1_enabled(ctx); 2495 gen_compute_branch1(ctx, mips32_op, 2496 (ctx->opcode >> 18) & 0x7, imm << 1); 2497 } else { 2498 generate_exception_err(ctx, EXCP_CpU, 1); 2499 } 2500 break; 2501 default: 2502 MIPS_INVAL("pool32i"); 2503 gen_reserved_instruction(ctx); 2504 break; 2505 } 2506 break; 2507 case POOL32C: 2508 minor = (ctx->opcode >> 12) & 0xf; 2509 offset = sextract32(ctx->opcode, 0, 2510 (ctx->insn_flags & ISA_MIPS_R6) ? 9 : 12); 2511 switch (minor) { 2512 case LWL: 2513 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2514 mips32_op = OPC_LWL; 2515 goto do_ld_lr; 2516 case SWL: 2517 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2518 mips32_op = OPC_SWL; 2519 goto do_st_lr; 2520 case LWR: 2521 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2522 mips32_op = OPC_LWR; 2523 goto do_ld_lr; 2524 case SWR: 2525 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2526 mips32_op = OPC_SWR; 2527 goto do_st_lr; 2528#if defined(TARGET_MIPS64) 2529 case LDL: 2530 check_insn(ctx, ISA_MIPS3); 2531 check_mips_64(ctx); 2532 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2533 mips32_op = OPC_LDL; 2534 goto do_ld_lr; 2535 case SDL: 2536 check_insn(ctx, ISA_MIPS3); 2537 check_mips_64(ctx); 2538 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2539 mips32_op = OPC_SDL; 2540 goto do_st_lr; 2541 case LDR: 2542 check_insn(ctx, ISA_MIPS3); 2543 check_mips_64(ctx); 2544 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2545 mips32_op = OPC_LDR; 2546 goto do_ld_lr; 2547 case SDR: 2548 check_insn(ctx, ISA_MIPS3); 2549 check_mips_64(ctx); 2550 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2551 mips32_op = OPC_SDR; 2552 goto do_st_lr; 2553 case LWU: 2554 check_insn(ctx, ISA_MIPS3); 2555 check_mips_64(ctx); 2556 mips32_op = OPC_LWU; 2557 goto do_ld_lr; 2558 case LLD: 2559 check_insn(ctx, ISA_MIPS3); 2560 check_mips_64(ctx); 2561 mips32_op = OPC_LLD; 2562 goto do_ld_lr; 2563#endif 2564 case LL: 2565 mips32_op = OPC_LL; 2566 goto do_ld_lr; 2567 do_ld_lr: 2568 gen_ld(ctx, mips32_op, rt, rs, offset); 2569 break; 2570 do_st_lr: 2571 gen_st(ctx, mips32_op, rt, rs, offset); 2572 break; 2573 case SC: 2574 gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_SL, false); 2575 break; 2576#if defined(TARGET_MIPS64) 2577 case SCD: 2578 check_insn(ctx, ISA_MIPS3); 2579 check_mips_64(ctx); 2580 gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_UQ, false); 2581 break; 2582#endif 2583 case LD_EVA: 2584 if (!ctx->eva) { 2585 MIPS_INVAL("pool32c ld-eva"); 2586 gen_reserved_instruction(ctx); 2587 break; 2588 } 2589 check_cp0_enabled(ctx); 2590 2591 minor2 = (ctx->opcode >> 9) & 0x7; 2592 offset = sextract32(ctx->opcode, 0, 9); 2593 switch (minor2) { 2594 case LBUE: 2595 mips32_op = OPC_LBUE; 2596 goto do_ld_lr; 2597 case LHUE: 2598 mips32_op = OPC_LHUE; 2599 goto do_ld_lr; 2600 case LWLE: 2601 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2602 mips32_op = OPC_LWLE; 2603 goto do_ld_lr; 2604 case LWRE: 2605 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2606 mips32_op = OPC_LWRE; 2607 goto do_ld_lr; 2608 case LBE: 2609 mips32_op = OPC_LBE; 2610 goto do_ld_lr; 2611 case LHE: 2612 mips32_op = OPC_LHE; 2613 goto do_ld_lr; 2614 case LLE: 2615 mips32_op = OPC_LLE; 2616 goto do_ld_lr; 2617 case LWE: 2618 mips32_op = OPC_LWE; 2619 goto do_ld_lr; 2620 }; 2621 break; 2622 case ST_EVA: 2623 if (!ctx->eva) { 2624 MIPS_INVAL("pool32c st-eva"); 2625 gen_reserved_instruction(ctx); 2626 break; 2627 } 2628 check_cp0_enabled(ctx); 2629 2630 minor2 = (ctx->opcode >> 9) & 0x7; 2631 offset = sextract32(ctx->opcode, 0, 9); 2632 switch (minor2) { 2633 case SWLE: 2634 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2635 mips32_op = OPC_SWLE; 2636 goto do_st_lr; 2637 case SWRE: 2638 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2639 mips32_op = OPC_SWRE; 2640 goto do_st_lr; 2641 case PREFE: 2642 /* Treat as no-op */ 2643 if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) { 2644 /* hint codes 24-31 are reserved and signal RI */ 2645 generate_exception(ctx, EXCP_RI); 2646 } 2647 break; 2648 case CACHEE: 2649 /* Treat as no-op */ 2650 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 2651 gen_cache_operation(ctx, rt, rs, offset); 2652 } 2653 break; 2654 case SBE: 2655 mips32_op = OPC_SBE; 2656 goto do_st_lr; 2657 case SHE: 2658 mips32_op = OPC_SHE; 2659 goto do_st_lr; 2660 case SCE: 2661 gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_SL, true); 2662 break; 2663 case SWE: 2664 mips32_op = OPC_SWE; 2665 goto do_st_lr; 2666 }; 2667 break; 2668 case PREF: 2669 /* Treat as no-op */ 2670 if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) { 2671 /* hint codes 24-31 are reserved and signal RI */ 2672 generate_exception(ctx, EXCP_RI); 2673 } 2674 break; 2675 default: 2676 MIPS_INVAL("pool32c"); 2677 gen_reserved_instruction(ctx); 2678 break; 2679 } 2680 break; 2681 case ADDI32: /* AUI, LUI */ 2682 if (ctx->insn_flags & ISA_MIPS_R6) { 2683 /* AUI, LUI */ 2684 gen_logic_imm(ctx, OPC_LUI, rt, rs, imm); 2685 } else { 2686 /* ADDI32 */ 2687 mips32_op = OPC_ADDI; 2688 goto do_addi; 2689 } 2690 break; 2691 case ADDIU32: 2692 mips32_op = OPC_ADDIU; 2693 do_addi: 2694 gen_arith_imm(ctx, mips32_op, rt, rs, imm); 2695 break; 2696 2697 /* Logical operations */ 2698 case ORI32: 2699 mips32_op = OPC_ORI; 2700 goto do_logici; 2701 case XORI32: 2702 mips32_op = OPC_XORI; 2703 goto do_logici; 2704 case ANDI32: 2705 mips32_op = OPC_ANDI; 2706 do_logici: 2707 gen_logic_imm(ctx, mips32_op, rt, rs, imm); 2708 break; 2709 2710 /* Set less than immediate */ 2711 case SLTI32: 2712 mips32_op = OPC_SLTI; 2713 goto do_slti; 2714 case SLTIU32: 2715 mips32_op = OPC_SLTIU; 2716 do_slti: 2717 gen_slt_imm(ctx, mips32_op, rt, rs, imm); 2718 break; 2719 case JALX32: 2720 check_insn_opc_removed(ctx, ISA_MIPS_R6); 2721 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; 2722 gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset, 4); 2723 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2724 break; 2725 case JALS32: /* BOVC, BEQC, BEQZALC */ 2726 if (ctx->insn_flags & ISA_MIPS_R6) { 2727 if (rs >= rt) { 2728 /* BOVC */ 2729 mips32_op = OPC_BOVC; 2730 } else if (rs < rt && rs == 0) { 2731 /* BEQZALC */ 2732 mips32_op = OPC_BEQZALC; 2733 } else { 2734 /* BEQC */ 2735 mips32_op = OPC_BEQC; 2736 } 2737 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2738 } else { 2739 /* JALS32 */ 2740 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 1; 2741 gen_compute_branch(ctx, OPC_JAL, 4, rt, rs, offset, 2); 2742 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2743 } 2744 break; 2745 case BEQ32: /* BC */ 2746 if (ctx->insn_flags & ISA_MIPS_R6) { 2747 /* BC */ 2748 gen_compute_compact_branch(ctx, OPC_BC, 0, 0, 2749 sextract32(ctx->opcode << 1, 0, 27)); 2750 } else { 2751 /* BEQ32 */ 2752 gen_compute_branch(ctx, OPC_BEQ, 4, rt, rs, imm << 1, 4); 2753 } 2754 break; 2755 case BNE32: /* BALC */ 2756 if (ctx->insn_flags & ISA_MIPS_R6) { 2757 /* BALC */ 2758 gen_compute_compact_branch(ctx, OPC_BALC, 0, 0, 2759 sextract32(ctx->opcode << 1, 0, 27)); 2760 } else { 2761 /* BNE32 */ 2762 gen_compute_branch(ctx, OPC_BNE, 4, rt, rs, imm << 1, 4); 2763 } 2764 break; 2765 case J32: /* BGTZC, BLTZC, BLTC */ 2766 if (ctx->insn_flags & ISA_MIPS_R6) { 2767 if (rs == 0 && rt != 0) { 2768 /* BGTZC */ 2769 mips32_op = OPC_BGTZC; 2770 } else if (rs != 0 && rt != 0 && rs == rt) { 2771 /* BLTZC */ 2772 mips32_op = OPC_BLTZC; 2773 } else { 2774 /* BLTC */ 2775 mips32_op = OPC_BLTC; 2776 } 2777 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2778 } else { 2779 /* J32 */ 2780 gen_compute_branch(ctx, OPC_J, 4, rt, rs, 2781 (int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4); 2782 } 2783 break; 2784 case JAL32: /* BLEZC, BGEZC, BGEC */ 2785 if (ctx->insn_flags & ISA_MIPS_R6) { 2786 if (rs == 0 && rt != 0) { 2787 /* BLEZC */ 2788 mips32_op = OPC_BLEZC; 2789 } else if (rs != 0 && rt != 0 && rs == rt) { 2790 /* BGEZC */ 2791 mips32_op = OPC_BGEZC; 2792 } else { 2793 /* BGEC */ 2794 mips32_op = OPC_BGEC; 2795 } 2796 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2797 } else { 2798 /* JAL32 */ 2799 gen_compute_branch(ctx, OPC_JAL, 4, rt, rs, 2800 (int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4); 2801 ctx->hflags |= MIPS_HFLAG_BDS_STRICT; 2802 } 2803 break; 2804 /* Floating point (COP1) */ 2805 case LWC132: 2806 mips32_op = OPC_LWC1; 2807 goto do_cop1; 2808 case LDC132: 2809 mips32_op = OPC_LDC1; 2810 goto do_cop1; 2811 case SWC132: 2812 mips32_op = OPC_SWC1; 2813 goto do_cop1; 2814 case SDC132: 2815 mips32_op = OPC_SDC1; 2816 do_cop1: 2817 gen_cop1_ldst(ctx, mips32_op, rt, rs, imm); 2818 break; 2819 case ADDIUPC: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */ 2820 if (ctx->insn_flags & ISA_MIPS_R6) { 2821 /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */ 2822 switch ((ctx->opcode >> 16) & 0x1f) { 2823 case ADDIUPC_00: 2824 case ADDIUPC_01: 2825 case ADDIUPC_02: 2826 case ADDIUPC_03: 2827 case ADDIUPC_04: 2828 case ADDIUPC_05: 2829 case ADDIUPC_06: 2830 case ADDIUPC_07: 2831 gen_pcrel(ctx, OPC_ADDIUPC, ctx->base.pc_next & ~0x3, rt); 2832 break; 2833 case AUIPC: 2834 gen_pcrel(ctx, OPC_AUIPC, ctx->base.pc_next, rt); 2835 break; 2836 case ALUIPC: 2837 gen_pcrel(ctx, OPC_ALUIPC, ctx->base.pc_next, rt); 2838 break; 2839 case LWPC_08: 2840 case LWPC_09: 2841 case LWPC_0A: 2842 case LWPC_0B: 2843 case LWPC_0C: 2844 case LWPC_0D: 2845 case LWPC_0E: 2846 case LWPC_0F: 2847 gen_pcrel(ctx, R6_OPC_LWPC, ctx->base.pc_next & ~0x3, rt); 2848 break; 2849 default: 2850 generate_exception(ctx, EXCP_RI); 2851 break; 2852 } 2853 } else { 2854 /* ADDIUPC */ 2855 int reg = mmreg(ZIMM(ctx->opcode, 23, 3)); 2856 offset = SIMM(ctx->opcode, 0, 23) << 2; 2857 2858 gen_addiupc(ctx, reg, offset, 0, 0); 2859 } 2860 break; 2861 case BNVC: /* BNEC, BNEZALC */ 2862 check_insn(ctx, ISA_MIPS_R6); 2863 if (rs >= rt) { 2864 /* BNVC */ 2865 mips32_op = OPC_BNVC; 2866 } else if (rs < rt && rs == 0) { 2867 /* BNEZALC */ 2868 mips32_op = OPC_BNEZALC; 2869 } else { 2870 /* BNEC */ 2871 mips32_op = OPC_BNEC; 2872 } 2873 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2874 break; 2875 case R6_BNEZC: /* JIALC */ 2876 check_insn(ctx, ISA_MIPS_R6); 2877 if (rt != 0) { 2878 /* BNEZC */ 2879 gen_compute_compact_branch(ctx, OPC_BNEZC, rt, 0, 2880 sextract32(ctx->opcode << 1, 0, 22)); 2881 } else { 2882 /* JIALC */ 2883 gen_compute_compact_branch(ctx, OPC_JIALC, 0, rs, imm); 2884 } 2885 break; 2886 case R6_BEQZC: /* JIC */ 2887 check_insn(ctx, ISA_MIPS_R6); 2888 if (rt != 0) { 2889 /* BEQZC */ 2890 gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0, 2891 sextract32(ctx->opcode << 1, 0, 22)); 2892 } else { 2893 /* JIC */ 2894 gen_compute_compact_branch(ctx, OPC_JIC, 0, rs, imm); 2895 } 2896 break; 2897 case BLEZALC: /* BGEZALC, BGEUC */ 2898 check_insn(ctx, ISA_MIPS_R6); 2899 if (rs == 0 && rt != 0) { 2900 /* BLEZALC */ 2901 mips32_op = OPC_BLEZALC; 2902 } else if (rs != 0 && rt != 0 && rs == rt) { 2903 /* BGEZALC */ 2904 mips32_op = OPC_BGEZALC; 2905 } else { 2906 /* BGEUC */ 2907 mips32_op = OPC_BGEUC; 2908 } 2909 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2910 break; 2911 case BGTZALC: /* BLTZALC, BLTUC */ 2912 check_insn(ctx, ISA_MIPS_R6); 2913 if (rs == 0 && rt != 0) { 2914 /* BGTZALC */ 2915 mips32_op = OPC_BGTZALC; 2916 } else if (rs != 0 && rt != 0 && rs == rt) { 2917 /* BLTZALC */ 2918 mips32_op = OPC_BLTZALC; 2919 } else { 2920 /* BLTUC */ 2921 mips32_op = OPC_BLTUC; 2922 } 2923 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); 2924 break; 2925 /* Loads and stores */ 2926 case LB32: 2927 mips32_op = OPC_LB; 2928 goto do_ld; 2929 case LBU32: 2930 mips32_op = OPC_LBU; 2931 goto do_ld; 2932 case LH32: 2933 mips32_op = OPC_LH; 2934 goto do_ld; 2935 case LHU32: 2936 mips32_op = OPC_LHU; 2937 goto do_ld; 2938 case LW32: 2939 mips32_op = OPC_LW; 2940 goto do_ld; 2941#ifdef TARGET_MIPS64 2942 case LD32: 2943 check_insn(ctx, ISA_MIPS3); 2944 check_mips_64(ctx); 2945 mips32_op = OPC_LD; 2946 goto do_ld; 2947 case SD32: 2948 check_insn(ctx, ISA_MIPS3); 2949 check_mips_64(ctx); 2950 mips32_op = OPC_SD; 2951 goto do_st; 2952#endif 2953 case SB32: 2954 mips32_op = OPC_SB; 2955 goto do_st; 2956 case SH32: 2957 mips32_op = OPC_SH; 2958 goto do_st; 2959 case SW32: 2960 mips32_op = OPC_SW; 2961 goto do_st; 2962 do_ld: 2963 gen_ld(ctx, mips32_op, rt, rs, imm); 2964 break; 2965 do_st: 2966 gen_st(ctx, mips32_op, rt, rs, imm); 2967 break; 2968 default: 2969 gen_reserved_instruction(ctx); 2970 break; 2971 } 2972} 2973 2974static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) 2975{ 2976 uint32_t op; 2977 2978 /* make sure instructions are on a halfword boundary */ 2979 if (ctx->base.pc_next & 0x1) { 2980 env->CP0_BadVAddr = ctx->base.pc_next; 2981 generate_exception_end(ctx, EXCP_AdEL); 2982 return 2; 2983 } 2984 2985 op = (ctx->opcode >> 10) & 0x3f; 2986 /* Enforce properly-sized instructions in a delay slot */ 2987 if (ctx->hflags & MIPS_HFLAG_BDS_STRICT) { 2988 switch (op & 0x7) { /* MSB-3..MSB-5 */ 2989 case 0: 2990 /* POOL32A, POOL32B, POOL32I, POOL32C */ 2991 case 4: 2992 /* ADDI32, ADDIU32, ORI32, XORI32, SLTI32, SLTIU32, ANDI32, JALX32 */ 2993 case 5: 2994 /* LBU32, LHU32, POOL32F, JALS32, BEQ32, BNE32, J32, JAL32 */ 2995 case 6: 2996 /* SB32, SH32, ADDIUPC, SWC132, SDC132, SW32 */ 2997 case 7: 2998 /* LB32, LH32, LWC132, LDC132, LW32 */ 2999 if (ctx->hflags & MIPS_HFLAG_BDS16) { 3000 gen_reserved_instruction(ctx); 3001 return 2; 3002 } 3003 break; 3004 case 1: 3005 /* POOL16A, POOL16B, POOL16C, LWGP16, POOL16F */ 3006 case 2: 3007 /* LBU16, LHU16, LWSP16, LW16, SB16, SH16, SWSP16, SW16 */ 3008 case 3: 3009 /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */ 3010 if (ctx->hflags & MIPS_HFLAG_BDS32) { 3011 gen_reserved_instruction(ctx); 3012 return 2; 3013 } 3014 break; 3015 } 3016 } 3017 3018 switch (op) { 3019 case POOL16A: 3020 { 3021 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3022 int rs1 = mmreg(uMIPS_RS1(ctx->opcode)); 3023 int rs2 = mmreg(uMIPS_RS2(ctx->opcode)); 3024 uint32_t opc = 0; 3025 3026 switch (ctx->opcode & 0x1) { 3027 case ADDU16: 3028 opc = OPC_ADDU; 3029 break; 3030 case SUBU16: 3031 opc = OPC_SUBU; 3032 break; 3033 } 3034 if (ctx->insn_flags & ISA_MIPS_R6) { 3035 /* 3036 * In the Release 6, the register number location in 3037 * the instruction encoding has changed. 3038 */ 3039 gen_arith(ctx, opc, rs1, rd, rs2); 3040 } else { 3041 gen_arith(ctx, opc, rd, rs1, rs2); 3042 } 3043 } 3044 break; 3045 case POOL16B: 3046 { 3047 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3048 int rs = mmreg(uMIPS_RS(ctx->opcode)); 3049 int amount = (ctx->opcode >> 1) & 0x7; 3050 uint32_t opc = 0; 3051 amount = amount == 0 ? 8 : amount; 3052 3053 switch (ctx->opcode & 0x1) { 3054 case SLL16: 3055 opc = OPC_SLL; 3056 break; 3057 case SRL16: 3058 opc = OPC_SRL; 3059 break; 3060 } 3061 3062 gen_shift_imm(ctx, opc, rd, rs, amount); 3063 } 3064 break; 3065 case POOL16C: 3066 if (ctx->insn_flags & ISA_MIPS_R6) { 3067 gen_pool16c_r6_insn(ctx); 3068 } else { 3069 gen_pool16c_insn(ctx); 3070 } 3071 break; 3072 case LWGP16: 3073 { 3074 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3075 int rb = 28; /* GP */ 3076 int16_t offset = SIMM(ctx->opcode, 0, 7) << 2; 3077 3078 gen_ld(ctx, OPC_LW, rd, rb, offset); 3079 } 3080 break; 3081 case POOL16F: 3082 check_insn_opc_removed(ctx, ISA_MIPS_R6); 3083 if (ctx->opcode & 1) { 3084 gen_reserved_instruction(ctx); 3085 } else { 3086 /* MOVEP */ 3087 int enc_dest = uMIPS_RD(ctx->opcode); 3088 int enc_rt = uMIPS_RS2(ctx->opcode); 3089 int enc_rs = uMIPS_RS1(ctx->opcode); 3090 gen_movep(ctx, enc_dest, enc_rt, enc_rs); 3091 } 3092 break; 3093 case LBU16: 3094 { 3095 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3096 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3097 int16_t offset = ZIMM(ctx->opcode, 0, 4); 3098 offset = (offset == 0xf ? -1 : offset); 3099 3100 gen_ld(ctx, OPC_LBU, rd, rb, offset); 3101 } 3102 break; 3103 case LHU16: 3104 { 3105 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3106 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3107 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1; 3108 3109 gen_ld(ctx, OPC_LHU, rd, rb, offset); 3110 } 3111 break; 3112 case LWSP16: 3113 { 3114 int rd = (ctx->opcode >> 5) & 0x1f; 3115 int rb = 29; /* SP */ 3116 int16_t offset = ZIMM(ctx->opcode, 0, 5) << 2; 3117 3118 gen_ld(ctx, OPC_LW, rd, rb, offset); 3119 } 3120 break; 3121 case LW16: 3122 { 3123 int rd = mmreg(uMIPS_RD(ctx->opcode)); 3124 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3125 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2; 3126 3127 gen_ld(ctx, OPC_LW, rd, rb, offset); 3128 } 3129 break; 3130 case SB16: 3131 { 3132 int rd = mmreg2(uMIPS_RD(ctx->opcode)); 3133 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3134 int16_t offset = ZIMM(ctx->opcode, 0, 4); 3135 3136 gen_st(ctx, OPC_SB, rd, rb, offset); 3137 } 3138 break; 3139 case SH16: 3140 { 3141 int rd = mmreg2(uMIPS_RD(ctx->opcode)); 3142 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3143 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1; 3144 3145 gen_st(ctx, OPC_SH, rd, rb, offset); 3146 } 3147 break; 3148 case SWSP16: 3149 { 3150 int rd = (ctx->opcode >> 5) & 0x1f; 3151 int rb = 29; /* SP */ 3152 int16_t offset = ZIMM(ctx->opcode, 0, 5) << 2; 3153 3154 gen_st(ctx, OPC_SW, rd, rb, offset); 3155 } 3156 break; 3157 case SW16: 3158 { 3159 int rd = mmreg2(uMIPS_RD(ctx->opcode)); 3160 int rb = mmreg(uMIPS_RS(ctx->opcode)); 3161 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2; 3162 3163 gen_st(ctx, OPC_SW, rd, rb, offset); 3164 } 3165 break; 3166 case MOVE16: 3167 { 3168 int rd = uMIPS_RD5(ctx->opcode); 3169 int rs = uMIPS_RS5(ctx->opcode); 3170 3171 gen_arith(ctx, OPC_ADDU, rd, rs, 0); 3172 } 3173 break; 3174 case ANDI16: 3175 gen_andi16(ctx); 3176 break; 3177 case POOL16D: 3178 switch (ctx->opcode & 0x1) { 3179 case ADDIUS5: 3180 gen_addius5(ctx); 3181 break; 3182 case ADDIUSP: 3183 gen_addiusp(ctx); 3184 break; 3185 } 3186 break; 3187 case POOL16E: 3188 switch (ctx->opcode & 0x1) { 3189 case ADDIUR2: 3190 gen_addiur2(ctx); 3191 break; 3192 case ADDIUR1SP: 3193 gen_addiur1sp(ctx); 3194 break; 3195 } 3196 break; 3197 case B16: /* BC16 */ 3198 gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, 3199 sextract32(ctx->opcode, 0, 10) << 1, 3200 (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4); 3201 break; 3202 case BNEZ16: /* BNEZC16 */ 3203 case BEQZ16: /* BEQZC16 */ 3204 gen_compute_branch(ctx, op == BNEZ16 ? OPC_BNE : OPC_BEQ, 2, 3205 mmreg(uMIPS_RD(ctx->opcode)), 3206 0, sextract32(ctx->opcode, 0, 7) << 1, 3207 (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4); 3208 3209 break; 3210 case LI16: 3211 { 3212 int reg = mmreg(uMIPS_RD(ctx->opcode)); 3213 int imm = ZIMM(ctx->opcode, 0, 7); 3214 3215 imm = (imm == 0x7f ? -1 : imm); 3216 tcg_gen_movi_tl(cpu_gpr[reg], imm); 3217 } 3218 break; 3219 case RES_29: 3220 case RES_31: 3221 case RES_39: 3222 gen_reserved_instruction(ctx); 3223 break; 3224 default: 3225 decode_micromips32_opc(env, ctx); 3226 return 4; 3227 } 3228 3229 return 2; 3230} 3231