1 /* 2 * MIPS TLB (Translation lookaside buffer) helpers. 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "exec/exec-all.h" 22 #include "../internal.h" 23 24 static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) 25 { 26 /* 27 * Interpret access control mode and mmu_idx. 28 * AdE? TLB? 29 * AM K S U E K S U E 30 * UK 0 0 1 1 0 0 - - 0 31 * MK 1 0 1 1 0 1 - - !eu 32 * MSK 2 0 0 1 0 1 1 - !eu 33 * MUSK 3 0 0 0 0 1 1 1 !eu 34 * MUSUK 4 0 0 0 0 0 1 1 0 35 * USK 5 0 0 1 0 0 0 - 0 36 * - 6 - - - - - - - - 37 * UUSK 7 0 0 0 0 0 0 0 0 38 */ 39 int32_t adetlb_mask; 40 41 switch (mmu_idx) { 42 case 3: /* ERL */ 43 /* If EU is set, always unmapped */ 44 if (eu) { 45 return 0; 46 } 47 /* fall through */ 48 case MIPS_HFLAG_KM: 49 /* Never AdE, TLB mapped if AM={1,2,3} */ 50 adetlb_mask = 0x70000000; 51 goto check_tlb; 52 53 case MIPS_HFLAG_SM: 54 /* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */ 55 adetlb_mask = 0xc0380000; 56 goto check_ade; 57 58 case MIPS_HFLAG_UM: 59 /* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */ 60 adetlb_mask = 0xe4180000; 61 /* fall through */ 62 check_ade: 63 /* does this AM cause AdE in current execution mode */ 64 if ((adetlb_mask << am) < 0) { 65 return TLBRET_BADADDR; 66 } 67 adetlb_mask <<= 8; 68 /* fall through */ 69 check_tlb: 70 /* is this AM mapped in current execution mode */ 71 return ((adetlb_mask << am) < 0); 72 default: 73 g_assert_not_reached(); 74 }; 75 } 76 77 static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical, 78 int *prot, target_ulong real_address, 79 MMUAccessType access_type, int mmu_idx, 80 unsigned int am, bool eu, 81 target_ulong segmask, 82 hwaddr physical_base) 83 { 84 int mapped = is_seg_am_mapped(am, eu, mmu_idx); 85 86 if (mapped < 0) { 87 /* is_seg_am_mapped can report TLBRET_BADADDR */ 88 return mapped; 89 } else if (mapped) { 90 /* The segment is TLB mapped */ 91 return env->tlb->map_address(env, physical, prot, real_address, 92 access_type); 93 } else { 94 /* The segment is unmapped */ 95 *physical = physical_base | (real_address & segmask); 96 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 97 return TLBRET_MATCH; 98 } 99 } 100 101 static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical, 102 int *prot, target_ulong real_address, 103 MMUAccessType access_type, int mmu_idx, 104 uint16_t segctl, target_ulong segmask) 105 { 106 unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM; 107 bool eu = (segctl >> CP0SC_EU) & 1; 108 hwaddr pa = ((hwaddr)segctl & CP0SC_PA_MASK) << 20; 109 110 return get_seg_physical_address(env, physical, prot, real_address, 111 access_type, mmu_idx, am, eu, segmask, 112 pa & ~(hwaddr)segmask); 113 } 114 115 int get_physical_address(CPUMIPSState *env, hwaddr *physical, 116 int *prot, target_ulong real_address, 117 MMUAccessType access_type, int mmu_idx) 118 { 119 /* User mode can only access useg/xuseg */ 120 #if defined(TARGET_MIPS64) 121 int user_mode = mmu_idx == MIPS_HFLAG_UM; 122 int supervisor_mode = mmu_idx == MIPS_HFLAG_SM; 123 int kernel_mode = !user_mode && !supervisor_mode; 124 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; 125 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; 126 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; 127 #endif 128 int ret = TLBRET_MATCH; 129 /* effective address (modified for KVM T&E kernel segments) */ 130 target_ulong address = real_address; 131 132 if (address <= USEG_LIMIT) { 133 /* useg */ 134 uint16_t segctl; 135 136 if (address >= 0x40000000UL) { 137 segctl = env->CP0_SegCtl2; 138 } else { 139 segctl = env->CP0_SegCtl2 >> 16; 140 } 141 ret = get_segctl_physical_address(env, physical, prot, 142 real_address, access_type, 143 mmu_idx, segctl, 0x3FFFFFFF); 144 #if defined(TARGET_MIPS64) 145 } else if (address < 0x4000000000000000ULL) { 146 /* xuseg */ 147 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { 148 ret = env->tlb->map_address(env, physical, prot, 149 real_address, access_type); 150 } else { 151 ret = TLBRET_BADADDR; 152 } 153 } else if (address < 0x8000000000000000ULL) { 154 /* xsseg */ 155 if ((supervisor_mode || kernel_mode) && 156 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { 157 ret = env->tlb->map_address(env, physical, prot, 158 real_address, access_type); 159 } else { 160 ret = TLBRET_BADADDR; 161 } 162 } else if (address < 0xC000000000000000ULL) { 163 /* xkphys */ 164 if ((address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) { 165 /* KX/SX/UX bit to check for each xkphys EVA access mode */ 166 static const uint8_t am_ksux[8] = { 167 [CP0SC_AM_UK] = (1u << CP0St_KX), 168 [CP0SC_AM_MK] = (1u << CP0St_KX), 169 [CP0SC_AM_MSK] = (1u << CP0St_SX), 170 [CP0SC_AM_MUSK] = (1u << CP0St_UX), 171 [CP0SC_AM_MUSUK] = (1u << CP0St_UX), 172 [CP0SC_AM_USK] = (1u << CP0St_SX), 173 [6] = (1u << CP0St_KX), 174 [CP0SC_AM_UUSK] = (1u << CP0St_UX), 175 }; 176 unsigned int am = CP0SC_AM_UK; 177 unsigned int xr = (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0SC2_XR; 178 179 if (xr & (1 << ((address >> 59) & 0x7))) { 180 am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM; 181 } 182 /* Does CP0_Status.KX/SX/UX permit the access mode (am) */ 183 if (env->CP0_Status & am_ksux[am]) { 184 ret = get_seg_physical_address(env, physical, prot, 185 real_address, access_type, 186 mmu_idx, am, false, env->PAMask, 187 0); 188 } else { 189 ret = TLBRET_BADADDR; 190 } 191 } else { 192 ret = TLBRET_BADADDR; 193 } 194 } else if (address < 0xFFFFFFFF80000000ULL) { 195 /* xkseg */ 196 if (kernel_mode && KX && 197 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { 198 ret = env->tlb->map_address(env, physical, prot, 199 real_address, access_type); 200 } else { 201 ret = TLBRET_BADADDR; 202 } 203 #endif 204 } else if (address < KSEG1_BASE) { 205 /* kseg0 */ 206 ret = get_segctl_physical_address(env, physical, prot, real_address, 207 access_type, mmu_idx, 208 env->CP0_SegCtl1 >> 16, 0x1FFFFFFF); 209 } else if (address < KSEG2_BASE) { 210 /* kseg1 */ 211 ret = get_segctl_physical_address(env, physical, prot, real_address, 212 access_type, mmu_idx, 213 env->CP0_SegCtl1, 0x1FFFFFFF); 214 } else if (address < KSEG3_BASE) { 215 /* sseg (kseg2) */ 216 ret = get_segctl_physical_address(env, physical, prot, real_address, 217 access_type, mmu_idx, 218 env->CP0_SegCtl0 >> 16, 0x1FFFFFFF); 219 } else { 220 /* 221 * kseg3 222 * XXX: debug segment is not emulated 223 */ 224 ret = get_segctl_physical_address(env, physical, prot, real_address, 225 access_type, mmu_idx, 226 env->CP0_SegCtl0, 0x1FFFFFFF); 227 } 228 return ret; 229 } 230 231 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 232 { 233 MIPSCPU *cpu = MIPS_CPU(cs); 234 CPUMIPSState *env = &cpu->env; 235 hwaddr phys_addr; 236 int prot; 237 238 if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, 239 cpu_mmu_index(env, false)) != 0) { 240 return -1; 241 } 242 return phys_addr; 243 } 244