1 /* 2 * QEMU MIPS timer support 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "hw/irq.h" 25 #include "hw/mips/cpudevs.h" 26 #include "qemu/timer.h" 27 #include "sysemu/kvm.h" 28 #include "internal.h" 29 30 /* MIPS R4K timer */ 31 static uint32_t cpu_mips_get_count_val(CPUMIPSState *env) 32 { 33 int64_t now_ns; 34 now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 35 return env->CP0_Count + 36 (uint32_t)clock_ns_to_ticks(env->count_clock, now_ns); 37 } 38 39 static void cpu_mips_timer_update(CPUMIPSState *env) 40 { 41 uint64_t now_ns, next_ns; 42 uint32_t wait; 43 44 now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 45 wait = env->CP0_Compare - cpu_mips_get_count_val(env); 46 /* Clamp interval to overflow if virtual time had not progressed */ 47 if (!wait) { 48 wait = UINT32_MAX; 49 } 50 next_ns = now_ns + clock_ticks_to_ns(env->count_clock, wait); 51 timer_mod(env->timer, next_ns); 52 } 53 54 /* Expire the timer. */ 55 static void cpu_mips_timer_expire(CPUMIPSState *env) 56 { 57 cpu_mips_timer_update(env); 58 if (env->insn_flags & ISA_MIPS_R2) { 59 env->CP0_Cause |= 1 << CP0Ca_TI; 60 } 61 qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); 62 } 63 64 uint32_t cpu_mips_get_count(CPUMIPSState *env) 65 { 66 if (env->CP0_Cause & (1 << CP0Ca_DC)) { 67 return env->CP0_Count; 68 } else { 69 uint64_t now_ns; 70 71 now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 72 if (timer_pending(env->timer) 73 && timer_expired(env->timer, now_ns)) { 74 /* The timer has already expired. */ 75 cpu_mips_timer_expire(env); 76 } 77 78 return cpu_mips_get_count_val(env); 79 } 80 } 81 82 void cpu_mips_store_count(CPUMIPSState *env, uint32_t count) 83 { 84 /* 85 * This gets called from cpu_state_reset(), potentially before timer init. 86 * So env->timer may be NULL, which is also the case with KVM enabled so 87 * treat timer as disabled in that case. 88 */ 89 if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer) { 90 env->CP0_Count = count; 91 } else { 92 /* Store new count register */ 93 env->CP0_Count = count - (uint32_t)clock_ns_to_ticks(env->count_clock, 94 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 95 /* Update timer timer */ 96 cpu_mips_timer_update(env); 97 } 98 } 99 100 void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value) 101 { 102 env->CP0_Compare = value; 103 if (!(env->CP0_Cause & (1 << CP0Ca_DC))) { 104 cpu_mips_timer_update(env); 105 } 106 if (env->insn_flags & ISA_MIPS_R2) { 107 env->CP0_Cause &= ~(1 << CP0Ca_TI); 108 } 109 qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); 110 } 111 112 void cpu_mips_start_count(CPUMIPSState *env) 113 { 114 cpu_mips_store_count(env, env->CP0_Count); 115 } 116 117 void cpu_mips_stop_count(CPUMIPSState *env) 118 { 119 /* Store the current value */ 120 env->CP0_Count += (uint32_t)clock_ns_to_ticks(env->count_clock, 121 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 122 } 123 124 static void mips_timer_cb(void *opaque) 125 { 126 CPUMIPSState *env; 127 128 env = opaque; 129 130 if (env->CP0_Cause & (1 << CP0Ca_DC)) { 131 return; 132 } 133 134 cpu_mips_timer_expire(env); 135 } 136 137 void cpu_mips_clock_init(MIPSCPU *cpu) 138 { 139 CPUMIPSState *env = &cpu->env; 140 141 /* 142 * If we're in KVM mode, don't create the periodic timer, that is handled in 143 * kernel. 144 */ 145 if (!kvm_enabled()) { 146 env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env); 147 } 148 } 149