1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * This file is subject to the terms and conditions of the GNU General Public 3fcf5ef2aSThomas Huth * License. See the file "COPYING" in the main directory of this archive 4fcf5ef2aSThomas Huth * for more details. 5fcf5ef2aSThomas Huth * 6fcf5ef2aSThomas Huth * KVM/MIPS: MIPS specific KVM APIs 7fcf5ef2aSThomas Huth * 8fcf5ef2aSThomas Huth * Copyright (C) 2012-2014 Imagination Technologies Ltd. 9fcf5ef2aSThomas Huth * Authors: Sanjay Lal <sanjayl@kymasys.com> 10fcf5ef2aSThomas Huth */ 11fcf5ef2aSThomas Huth 12fcf5ef2aSThomas Huth #include "qemu/osdep.h" 13fcf5ef2aSThomas Huth #include <sys/ioctl.h> 14fcf5ef2aSThomas Huth 15fcf5ef2aSThomas Huth #include <linux/kvm.h> 16fcf5ef2aSThomas Huth 17fcf5ef2aSThomas Huth #include "qemu-common.h" 18fcf5ef2aSThomas Huth #include "cpu.h" 1926aa3d9aSPhilippe Mathieu-Daudé #include "internal.h" 20fcf5ef2aSThomas Huth #include "qemu/error-report.h" 21fcf5ef2aSThomas Huth #include "qemu/timer.h" 22fcf5ef2aSThomas Huth #include "sysemu/sysemu.h" 23fcf5ef2aSThomas Huth #include "sysemu/kvm.h" 24fcf5ef2aSThomas Huth #include "sysemu/cpus.h" 25fcf5ef2aSThomas Huth #include "kvm_mips.h" 26fcf5ef2aSThomas Huth #include "exec/memattrs.h" 27fcf5ef2aSThomas Huth 28fcf5ef2aSThomas Huth #define DEBUG_KVM 0 29fcf5ef2aSThomas Huth 30fcf5ef2aSThomas Huth #define DPRINTF(fmt, ...) \ 31fcf5ef2aSThomas Huth do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0) 32fcf5ef2aSThomas Huth 33fcf5ef2aSThomas Huth static int kvm_mips_fpu_cap; 34fcf5ef2aSThomas Huth static int kvm_mips_msa_cap; 35fcf5ef2aSThomas Huth 36fcf5ef2aSThomas Huth const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 37fcf5ef2aSThomas Huth KVM_CAP_LAST_INFO 38fcf5ef2aSThomas Huth }; 39fcf5ef2aSThomas Huth 40fcf5ef2aSThomas Huth static void kvm_mips_update_state(void *opaque, int running, RunState state); 41fcf5ef2aSThomas Huth 42fcf5ef2aSThomas Huth unsigned long kvm_arch_vcpu_id(CPUState *cs) 43fcf5ef2aSThomas Huth { 44fcf5ef2aSThomas Huth return cs->cpu_index; 45fcf5ef2aSThomas Huth } 46fcf5ef2aSThomas Huth 47fcf5ef2aSThomas Huth int kvm_arch_init(MachineState *ms, KVMState *s) 48fcf5ef2aSThomas Huth { 49fcf5ef2aSThomas Huth /* MIPS has 128 signals */ 50fcf5ef2aSThomas Huth kvm_set_sigmask_len(s, 16); 51fcf5ef2aSThomas Huth 52fcf5ef2aSThomas Huth kvm_mips_fpu_cap = kvm_check_extension(s, KVM_CAP_MIPS_FPU); 53fcf5ef2aSThomas Huth kvm_mips_msa_cap = kvm_check_extension(s, KVM_CAP_MIPS_MSA); 54fcf5ef2aSThomas Huth 55fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 56fcf5ef2aSThomas Huth return 0; 57fcf5ef2aSThomas Huth } 58fcf5ef2aSThomas Huth 59d525ffabSPaolo Bonzini int kvm_arch_irqchip_create(MachineState *ms, KVMState *s) 60d525ffabSPaolo Bonzini { 61d525ffabSPaolo Bonzini return 0; 62d525ffabSPaolo Bonzini } 63d525ffabSPaolo Bonzini 64fcf5ef2aSThomas Huth int kvm_arch_init_vcpu(CPUState *cs) 65fcf5ef2aSThomas Huth { 66fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 67fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 68fcf5ef2aSThomas Huth int ret = 0; 69fcf5ef2aSThomas Huth 70fcf5ef2aSThomas Huth qemu_add_vm_change_state_handler(kvm_mips_update_state, cs); 71fcf5ef2aSThomas Huth 72fcf5ef2aSThomas Huth if (kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) { 73fcf5ef2aSThomas Huth ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_FPU, 0, 0); 74fcf5ef2aSThomas Huth if (ret < 0) { 75fcf5ef2aSThomas Huth /* mark unsupported so it gets disabled on reset */ 76fcf5ef2aSThomas Huth kvm_mips_fpu_cap = 0; 77fcf5ef2aSThomas Huth ret = 0; 78fcf5ef2aSThomas Huth } 79fcf5ef2aSThomas Huth } 80fcf5ef2aSThomas Huth 81fcf5ef2aSThomas Huth if (kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) { 82fcf5ef2aSThomas Huth ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0); 83fcf5ef2aSThomas Huth if (ret < 0) { 84fcf5ef2aSThomas Huth /* mark unsupported so it gets disabled on reset */ 85fcf5ef2aSThomas Huth kvm_mips_msa_cap = 0; 86fcf5ef2aSThomas Huth ret = 0; 87fcf5ef2aSThomas Huth } 88fcf5ef2aSThomas Huth } 89fcf5ef2aSThomas Huth 90fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 91fcf5ef2aSThomas Huth return ret; 92fcf5ef2aSThomas Huth } 93fcf5ef2aSThomas Huth 94*b1115c99SLiran Alon int kvm_arch_destroy_vcpu(CPUState *cs) 95*b1115c99SLiran Alon { 96*b1115c99SLiran Alon return 0; 97*b1115c99SLiran Alon } 98*b1115c99SLiran Alon 99fcf5ef2aSThomas Huth void kvm_mips_reset_vcpu(MIPSCPU *cpu) 100fcf5ef2aSThomas Huth { 101fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 102fcf5ef2aSThomas Huth 103fcf5ef2aSThomas Huth if (!kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) { 1042ab4b135SAlistair Francis warn_report("KVM does not support FPU, disabling"); 105fcf5ef2aSThomas Huth env->CP0_Config1 &= ~(1 << CP0C1_FP); 106fcf5ef2aSThomas Huth } 107fcf5ef2aSThomas Huth if (!kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) { 1082ab4b135SAlistair Francis warn_report("KVM does not support MSA, disabling"); 109fcf5ef2aSThomas Huth env->CP0_Config3 &= ~(1 << CP0C3_MSAP); 110fcf5ef2aSThomas Huth } 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 113fcf5ef2aSThomas Huth } 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 116fcf5ef2aSThomas Huth { 117fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 118fcf5ef2aSThomas Huth return 0; 119fcf5ef2aSThomas Huth } 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 122fcf5ef2aSThomas Huth { 123fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 124fcf5ef2aSThomas Huth return 0; 125fcf5ef2aSThomas Huth } 126fcf5ef2aSThomas Huth 127fcf5ef2aSThomas Huth static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu) 128fcf5ef2aSThomas Huth { 129fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 130fcf5ef2aSThomas Huth 131fcf5ef2aSThomas Huth return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP)); 132fcf5ef2aSThomas Huth } 133fcf5ef2aSThomas Huth 134fcf5ef2aSThomas Huth 135fcf5ef2aSThomas Huth void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 136fcf5ef2aSThomas Huth { 137fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 138fcf5ef2aSThomas Huth int r; 139fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 140fcf5ef2aSThomas Huth 141fcf5ef2aSThomas Huth qemu_mutex_lock_iothread(); 142fcf5ef2aSThomas Huth 143fcf5ef2aSThomas Huth if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 144fcf5ef2aSThomas Huth cpu_mips_io_interrupts_pending(cpu)) { 145fcf5ef2aSThomas Huth intr.cpu = -1; 146fcf5ef2aSThomas Huth intr.irq = 2; 147fcf5ef2aSThomas Huth r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 148fcf5ef2aSThomas Huth if (r < 0) { 149fcf5ef2aSThomas Huth error_report("%s: cpu %d: failed to inject IRQ %x", 150fcf5ef2aSThomas Huth __func__, cs->cpu_index, intr.irq); 151fcf5ef2aSThomas Huth } 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth qemu_mutex_unlock_iothread(); 155fcf5ef2aSThomas Huth } 156fcf5ef2aSThomas Huth 157fcf5ef2aSThomas Huth MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 158fcf5ef2aSThomas Huth { 159fcf5ef2aSThomas Huth return MEMTXATTRS_UNSPECIFIED; 160fcf5ef2aSThomas Huth } 161fcf5ef2aSThomas Huth 162fcf5ef2aSThomas Huth int kvm_arch_process_async_events(CPUState *cs) 163fcf5ef2aSThomas Huth { 164fcf5ef2aSThomas Huth return cs->halted; 165fcf5ef2aSThomas Huth } 166fcf5ef2aSThomas Huth 167fcf5ef2aSThomas Huth int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 168fcf5ef2aSThomas Huth { 169fcf5ef2aSThomas Huth int ret; 170fcf5ef2aSThomas Huth 171fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 172fcf5ef2aSThomas Huth switch (run->exit_reason) { 173fcf5ef2aSThomas Huth default: 174fcf5ef2aSThomas Huth error_report("%s: unknown exit reason %d", 175fcf5ef2aSThomas Huth __func__, run->exit_reason); 176fcf5ef2aSThomas Huth ret = -1; 177fcf5ef2aSThomas Huth break; 178fcf5ef2aSThomas Huth } 179fcf5ef2aSThomas Huth 180fcf5ef2aSThomas Huth return ret; 181fcf5ef2aSThomas Huth } 182fcf5ef2aSThomas Huth 183fcf5ef2aSThomas Huth bool kvm_arch_stop_on_emulation_error(CPUState *cs) 184fcf5ef2aSThomas Huth { 185fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 186fcf5ef2aSThomas Huth return true; 187fcf5ef2aSThomas Huth } 188fcf5ef2aSThomas Huth 189fcf5ef2aSThomas Huth void kvm_arch_init_irq_routing(KVMState *s) 190fcf5ef2aSThomas Huth { 191fcf5ef2aSThomas Huth } 192fcf5ef2aSThomas Huth 193fcf5ef2aSThomas Huth int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level) 194fcf5ef2aSThomas Huth { 195fcf5ef2aSThomas Huth CPUState *cs = CPU(cpu); 196fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 197fcf5ef2aSThomas Huth 198fcf5ef2aSThomas Huth if (!kvm_enabled()) { 199fcf5ef2aSThomas Huth return 0; 200fcf5ef2aSThomas Huth } 201fcf5ef2aSThomas Huth 202fcf5ef2aSThomas Huth intr.cpu = -1; 203fcf5ef2aSThomas Huth 204fcf5ef2aSThomas Huth if (level) { 205fcf5ef2aSThomas Huth intr.irq = irq; 206fcf5ef2aSThomas Huth } else { 207fcf5ef2aSThomas Huth intr.irq = -irq; 208fcf5ef2aSThomas Huth } 209fcf5ef2aSThomas Huth 210fcf5ef2aSThomas Huth kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 211fcf5ef2aSThomas Huth 212fcf5ef2aSThomas Huth return 0; 213fcf5ef2aSThomas Huth } 214fcf5ef2aSThomas Huth 215fcf5ef2aSThomas Huth int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) 216fcf5ef2aSThomas Huth { 217fcf5ef2aSThomas Huth CPUState *cs = current_cpu; 218fcf5ef2aSThomas Huth CPUState *dest_cs = CPU(cpu); 219fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 220fcf5ef2aSThomas Huth 221fcf5ef2aSThomas Huth if (!kvm_enabled()) { 222fcf5ef2aSThomas Huth return 0; 223fcf5ef2aSThomas Huth } 224fcf5ef2aSThomas Huth 225fcf5ef2aSThomas Huth intr.cpu = dest_cs->cpu_index; 226fcf5ef2aSThomas Huth 227fcf5ef2aSThomas Huth if (level) { 228fcf5ef2aSThomas Huth intr.irq = irq; 229fcf5ef2aSThomas Huth } else { 230fcf5ef2aSThomas Huth intr.irq = -irq; 231fcf5ef2aSThomas Huth } 232fcf5ef2aSThomas Huth 233fcf5ef2aSThomas Huth DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq); 234fcf5ef2aSThomas Huth 235fcf5ef2aSThomas Huth kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 236fcf5ef2aSThomas Huth 237fcf5ef2aSThomas Huth return 0; 238fcf5ef2aSThomas Huth } 239fcf5ef2aSThomas Huth 240fcf5ef2aSThomas Huth #define MIPS_CP0_32(_R, _S) \ 241fcf5ef2aSThomas Huth (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S))) 242fcf5ef2aSThomas Huth 243fcf5ef2aSThomas Huth #define MIPS_CP0_64(_R, _S) \ 244fcf5ef2aSThomas Huth (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) 245fcf5ef2aSThomas Huth 246fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) 247fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) 248fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) 249fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) 250fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) 251fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) 252fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) 253fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) 254fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) 255fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) 256fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) 257fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) 258fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) 259fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) 260fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) 261fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) 262fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) 263fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) 264fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) 265fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) 266fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) 267fcf5ef2aSThomas Huth 268fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, 269fcf5ef2aSThomas Huth int32_t *addr) 270fcf5ef2aSThomas Huth { 271fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 272fcf5ef2aSThomas Huth .id = reg_id, 273fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 274fcf5ef2aSThomas Huth }; 275fcf5ef2aSThomas Huth 276fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 277fcf5ef2aSThomas Huth } 278fcf5ef2aSThomas Huth 279fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ureg(CPUState *cs, uint64_t reg_id, 280fcf5ef2aSThomas Huth uint32_t *addr) 281fcf5ef2aSThomas Huth { 282fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 283fcf5ef2aSThomas Huth .id = reg_id, 284fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 285fcf5ef2aSThomas Huth }; 286fcf5ef2aSThomas Huth 287fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 288fcf5ef2aSThomas Huth } 289fcf5ef2aSThomas Huth 290fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id, 291fcf5ef2aSThomas Huth target_ulong *addr) 292fcf5ef2aSThomas Huth { 293fcf5ef2aSThomas Huth uint64_t val64 = *addr; 294fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 295fcf5ef2aSThomas Huth .id = reg_id, 296fcf5ef2aSThomas Huth .addr = (uintptr_t)&val64 297fcf5ef2aSThomas Huth }; 298fcf5ef2aSThomas Huth 299fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 300fcf5ef2aSThomas Huth } 301fcf5ef2aSThomas Huth 302fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id, 303fcf5ef2aSThomas Huth int64_t *addr) 304fcf5ef2aSThomas Huth { 305fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 306fcf5ef2aSThomas Huth .id = reg_id, 307fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 308fcf5ef2aSThomas Huth }; 309fcf5ef2aSThomas Huth 310fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 311fcf5ef2aSThomas Huth } 312fcf5ef2aSThomas Huth 313fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ureg64(CPUState *cs, uint64_t reg_id, 314fcf5ef2aSThomas Huth uint64_t *addr) 315fcf5ef2aSThomas Huth { 316fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 317fcf5ef2aSThomas Huth .id = reg_id, 318fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 319fcf5ef2aSThomas Huth }; 320fcf5ef2aSThomas Huth 321fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 322fcf5ef2aSThomas Huth } 323fcf5ef2aSThomas Huth 324fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id, 325fcf5ef2aSThomas Huth int32_t *addr) 326fcf5ef2aSThomas Huth { 327fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 328fcf5ef2aSThomas Huth .id = reg_id, 329fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 330fcf5ef2aSThomas Huth }; 331fcf5ef2aSThomas Huth 332fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 333fcf5ef2aSThomas Huth } 334fcf5ef2aSThomas Huth 335fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ureg(CPUState *cs, uint64_t reg_id, 336fcf5ef2aSThomas Huth uint32_t *addr) 337fcf5ef2aSThomas Huth { 338fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 339fcf5ef2aSThomas Huth .id = reg_id, 340fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 341fcf5ef2aSThomas Huth }; 342fcf5ef2aSThomas Huth 343fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 344fcf5ef2aSThomas Huth } 345fcf5ef2aSThomas Huth 346fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64_t reg_id, 347fcf5ef2aSThomas Huth target_ulong *addr) 348fcf5ef2aSThomas Huth { 349fcf5ef2aSThomas Huth int ret; 350fcf5ef2aSThomas Huth uint64_t val64 = 0; 351fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 352fcf5ef2aSThomas Huth .id = reg_id, 353fcf5ef2aSThomas Huth .addr = (uintptr_t)&val64 354fcf5ef2aSThomas Huth }; 355fcf5ef2aSThomas Huth 356fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 357fcf5ef2aSThomas Huth if (ret >= 0) { 358fcf5ef2aSThomas Huth *addr = val64; 359fcf5ef2aSThomas Huth } 360fcf5ef2aSThomas Huth return ret; 361fcf5ef2aSThomas Huth } 362fcf5ef2aSThomas Huth 363fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64_t reg_id, 364fcf5ef2aSThomas Huth int64_t *addr) 365fcf5ef2aSThomas Huth { 366fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 367fcf5ef2aSThomas Huth .id = reg_id, 368fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 369fcf5ef2aSThomas Huth }; 370fcf5ef2aSThomas Huth 371fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 372fcf5ef2aSThomas Huth } 373fcf5ef2aSThomas Huth 374fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ureg64(CPUState *cs, uint64_t reg_id, 375fcf5ef2aSThomas Huth uint64_t *addr) 376fcf5ef2aSThomas Huth { 377fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 378fcf5ef2aSThomas Huth .id = reg_id, 379fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 380fcf5ef2aSThomas Huth }; 381fcf5ef2aSThomas Huth 382fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 383fcf5ef2aSThomas Huth } 384fcf5ef2aSThomas Huth 385fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M) 386fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG1_MASK ((1U << CP0C1_M) | \ 387fcf5ef2aSThomas Huth (1U << CP0C1_FP)) 388fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG2_MASK (1U << CP0C2_M) 389fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG3_MASK ((1U << CP0C3_M) | \ 390fcf5ef2aSThomas Huth (1U << CP0C3_MSAP)) 391fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG4_MASK (1U << CP0C4_M) 392fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG5_MASK ((1U << CP0C5_MSAEn) | \ 393fcf5ef2aSThomas Huth (1U << CP0C5_UFE) | \ 394fcf5ef2aSThomas Huth (1U << CP0C5_FRE) | \ 395fcf5ef2aSThomas Huth (1U << CP0C5_UFR)) 396fcf5ef2aSThomas Huth 397fcf5ef2aSThomas Huth static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id, 398fcf5ef2aSThomas Huth int32_t *addr, int32_t mask) 399fcf5ef2aSThomas Huth { 400fcf5ef2aSThomas Huth int err; 401fcf5ef2aSThomas Huth int32_t tmp, change; 402fcf5ef2aSThomas Huth 403fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, reg_id, &tmp); 404fcf5ef2aSThomas Huth if (err < 0) { 405fcf5ef2aSThomas Huth return err; 406fcf5ef2aSThomas Huth } 407fcf5ef2aSThomas Huth 408fcf5ef2aSThomas Huth /* only change bits in mask */ 409fcf5ef2aSThomas Huth change = (*addr ^ tmp) & mask; 410fcf5ef2aSThomas Huth if (!change) { 411fcf5ef2aSThomas Huth return 0; 412fcf5ef2aSThomas Huth } 413fcf5ef2aSThomas Huth 414fcf5ef2aSThomas Huth tmp = tmp ^ change; 415fcf5ef2aSThomas Huth return kvm_mips_put_one_reg(cs, reg_id, &tmp); 416fcf5ef2aSThomas Huth } 417fcf5ef2aSThomas Huth 418fcf5ef2aSThomas Huth /* 419fcf5ef2aSThomas Huth * We freeze the KVM timer when either the VM clock is stopped or the state is 420fcf5ef2aSThomas Huth * saved (the state is dirty). 421fcf5ef2aSThomas Huth */ 422fcf5ef2aSThomas Huth 423fcf5ef2aSThomas Huth /* 424fcf5ef2aSThomas Huth * Save the state of the KVM timer when VM clock is stopped or state is synced 425fcf5ef2aSThomas Huth * to QEMU. 426fcf5ef2aSThomas Huth */ 427fcf5ef2aSThomas Huth static int kvm_mips_save_count(CPUState *cs) 428fcf5ef2aSThomas Huth { 429fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 430fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 431fcf5ef2aSThomas Huth uint64_t count_ctl; 432fcf5ef2aSThomas Huth int err, ret = 0; 433fcf5ef2aSThomas Huth 434fcf5ef2aSThomas Huth /* freeze KVM timer */ 435fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 436fcf5ef2aSThomas Huth if (err < 0) { 437fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err); 438fcf5ef2aSThomas Huth ret = err; 439fcf5ef2aSThomas Huth } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) { 440fcf5ef2aSThomas Huth count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC; 441fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 442fcf5ef2aSThomas Huth if (err < 0) { 443fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err); 444fcf5ef2aSThomas Huth ret = err; 445fcf5ef2aSThomas Huth } 446fcf5ef2aSThomas Huth } 447fcf5ef2aSThomas Huth 448fcf5ef2aSThomas Huth /* read CP0_Cause */ 449fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause); 450fcf5ef2aSThomas Huth if (err < 0) { 451fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err); 452fcf5ef2aSThomas Huth ret = err; 453fcf5ef2aSThomas Huth } 454fcf5ef2aSThomas Huth 455fcf5ef2aSThomas Huth /* read CP0_Count */ 456fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count); 457fcf5ef2aSThomas Huth if (err < 0) { 458fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err); 459fcf5ef2aSThomas Huth ret = err; 460fcf5ef2aSThomas Huth } 461fcf5ef2aSThomas Huth 462fcf5ef2aSThomas Huth return ret; 463fcf5ef2aSThomas Huth } 464fcf5ef2aSThomas Huth 465fcf5ef2aSThomas Huth /* 466fcf5ef2aSThomas Huth * Restore the state of the KVM timer when VM clock is restarted or state is 467fcf5ef2aSThomas Huth * synced to KVM. 468fcf5ef2aSThomas Huth */ 469fcf5ef2aSThomas Huth static int kvm_mips_restore_count(CPUState *cs) 470fcf5ef2aSThomas Huth { 471fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 472fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 473fcf5ef2aSThomas Huth uint64_t count_ctl; 474fcf5ef2aSThomas Huth int err_dc, err, ret = 0; 475fcf5ef2aSThomas Huth 476fcf5ef2aSThomas Huth /* check the timer is frozen */ 477fcf5ef2aSThomas Huth err_dc = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 478fcf5ef2aSThomas Huth if (err_dc < 0) { 479fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc); 480fcf5ef2aSThomas Huth ret = err_dc; 481fcf5ef2aSThomas Huth } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) { 482fcf5ef2aSThomas Huth /* freeze timer (sets COUNT_RESUME for us) */ 483fcf5ef2aSThomas Huth count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC; 484fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 485fcf5ef2aSThomas Huth if (err < 0) { 486fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err); 487fcf5ef2aSThomas Huth ret = err; 488fcf5ef2aSThomas Huth } 489fcf5ef2aSThomas Huth } 490fcf5ef2aSThomas Huth 491fcf5ef2aSThomas Huth /* load CP0_Cause */ 492fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause); 493fcf5ef2aSThomas Huth if (err < 0) { 494fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err); 495fcf5ef2aSThomas Huth ret = err; 496fcf5ef2aSThomas Huth } 497fcf5ef2aSThomas Huth 498fcf5ef2aSThomas Huth /* load CP0_Count */ 499fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count); 500fcf5ef2aSThomas Huth if (err < 0) { 501fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err); 502fcf5ef2aSThomas Huth ret = err; 503fcf5ef2aSThomas Huth } 504fcf5ef2aSThomas Huth 505fcf5ef2aSThomas Huth /* resume KVM timer */ 506fcf5ef2aSThomas Huth if (err_dc >= 0) { 507fcf5ef2aSThomas Huth count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC; 508fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 509fcf5ef2aSThomas Huth if (err < 0) { 510fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err); 511fcf5ef2aSThomas Huth ret = err; 512fcf5ef2aSThomas Huth } 513fcf5ef2aSThomas Huth } 514fcf5ef2aSThomas Huth 515fcf5ef2aSThomas Huth return ret; 516fcf5ef2aSThomas Huth } 517fcf5ef2aSThomas Huth 518fcf5ef2aSThomas Huth /* 519fcf5ef2aSThomas Huth * Handle the VM clock being started or stopped 520fcf5ef2aSThomas Huth */ 521fcf5ef2aSThomas Huth static void kvm_mips_update_state(void *opaque, int running, RunState state) 522fcf5ef2aSThomas Huth { 523fcf5ef2aSThomas Huth CPUState *cs = opaque; 524fcf5ef2aSThomas Huth int ret; 525fcf5ef2aSThomas Huth uint64_t count_resume; 526fcf5ef2aSThomas Huth 527fcf5ef2aSThomas Huth /* 528fcf5ef2aSThomas Huth * If state is already dirty (synced to QEMU) then the KVM timer state is 529fcf5ef2aSThomas Huth * already saved and can be restored when it is synced back to KVM. 530fcf5ef2aSThomas Huth */ 531fcf5ef2aSThomas Huth if (!running) { 53299f31832SSergio Andres Gomez Del Real if (!cs->vcpu_dirty) { 533fcf5ef2aSThomas Huth ret = kvm_mips_save_count(cs); 534fcf5ef2aSThomas Huth if (ret < 0) { 535288cb949SAlistair Francis warn_report("Failed saving count"); 536fcf5ef2aSThomas Huth } 537fcf5ef2aSThomas Huth } 538fcf5ef2aSThomas Huth } else { 539fcf5ef2aSThomas Huth /* Set clock restore time to now */ 540fcf5ef2aSThomas Huth count_resume = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 541fcf5ef2aSThomas Huth ret = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_RESUME, 542fcf5ef2aSThomas Huth &count_resume); 543fcf5ef2aSThomas Huth if (ret < 0) { 544288cb949SAlistair Francis warn_report("Failed setting COUNT_RESUME"); 545fcf5ef2aSThomas Huth return; 546fcf5ef2aSThomas Huth } 547fcf5ef2aSThomas Huth 54899f31832SSergio Andres Gomez Del Real if (!cs->vcpu_dirty) { 549fcf5ef2aSThomas Huth ret = kvm_mips_restore_count(cs); 550fcf5ef2aSThomas Huth if (ret < 0) { 551288cb949SAlistair Francis warn_report("Failed restoring count"); 552fcf5ef2aSThomas Huth } 553fcf5ef2aSThomas Huth } 554fcf5ef2aSThomas Huth } 555fcf5ef2aSThomas Huth } 556fcf5ef2aSThomas Huth 557fcf5ef2aSThomas Huth static int kvm_mips_put_fpu_registers(CPUState *cs, int level) 558fcf5ef2aSThomas Huth { 559fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 560fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 561fcf5ef2aSThomas Huth int err, ret = 0; 562fcf5ef2aSThomas Huth unsigned int i; 563fcf5ef2aSThomas Huth 564fcf5ef2aSThomas Huth /* Only put FPU state if we're emulating a CPU with an FPU */ 565fcf5ef2aSThomas Huth if (env->CP0_Config1 & (1 << CP0C1_FP)) { 566fcf5ef2aSThomas Huth /* FPU Control Registers */ 567fcf5ef2aSThomas Huth if (level == KVM_PUT_FULL_STATE) { 568fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg(cs, KVM_REG_MIPS_FCR_IR, 569fcf5ef2aSThomas Huth &env->active_fpu.fcr0); 570fcf5ef2aSThomas Huth if (err < 0) { 571fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FCR_IR (%d)\n", __func__, err); 572fcf5ef2aSThomas Huth ret = err; 573fcf5ef2aSThomas Huth } 574fcf5ef2aSThomas Huth } 575fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg(cs, KVM_REG_MIPS_FCR_CSR, 576fcf5ef2aSThomas Huth &env->active_fpu.fcr31); 577fcf5ef2aSThomas Huth if (err < 0) { 578fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FCR_CSR (%d)\n", __func__, err); 579fcf5ef2aSThomas Huth ret = err; 580fcf5ef2aSThomas Huth } 581fcf5ef2aSThomas Huth 582fcf5ef2aSThomas Huth /* 583fcf5ef2aSThomas Huth * FPU register state is a subset of MSA vector state, so don't put FPU 584fcf5ef2aSThomas Huth * registers if we're emulating a CPU with MSA. 585fcf5ef2aSThomas Huth */ 586fcf5ef2aSThomas Huth if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { 587fcf5ef2aSThomas Huth /* Floating point registers */ 588fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 589fcf5ef2aSThomas Huth if (env->CP0_Status & (1 << CP0St_FR)) { 590fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i), 591fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].d); 592fcf5ef2aSThomas Huth } else { 593fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i), 594fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); 595fcf5ef2aSThomas Huth } 596fcf5ef2aSThomas Huth if (err < 0) { 597fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FPR%u (%d)\n", __func__, i, err); 598fcf5ef2aSThomas Huth ret = err; 599fcf5ef2aSThomas Huth } 600fcf5ef2aSThomas Huth } 601fcf5ef2aSThomas Huth } 602fcf5ef2aSThomas Huth } 603fcf5ef2aSThomas Huth 604fcf5ef2aSThomas Huth /* Only put MSA state if we're emulating a CPU with MSA */ 605fcf5ef2aSThomas Huth if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { 606fcf5ef2aSThomas Huth /* MSA Control Registers */ 607fcf5ef2aSThomas Huth if (level == KVM_PUT_FULL_STATE) { 608fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_IR, 609fcf5ef2aSThomas Huth &env->msair); 610fcf5ef2aSThomas Huth if (err < 0) { 611fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put MSA_IR (%d)\n", __func__, err); 612fcf5ef2aSThomas Huth ret = err; 613fcf5ef2aSThomas Huth } 614fcf5ef2aSThomas Huth } 615fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_CSR, 616fcf5ef2aSThomas Huth &env->active_tc.msacsr); 617fcf5ef2aSThomas Huth if (err < 0) { 618fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put MSA_CSR (%d)\n", __func__, err); 619fcf5ef2aSThomas Huth ret = err; 620fcf5ef2aSThomas Huth } 621fcf5ef2aSThomas Huth 622fcf5ef2aSThomas Huth /* Vector registers (includes FP registers) */ 623fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 624fcf5ef2aSThomas Huth /* Big endian MSA not supported by QEMU yet anyway */ 625fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_VEC_128(i), 626fcf5ef2aSThomas Huth env->active_fpu.fpr[i].wr.d); 627fcf5ef2aSThomas Huth if (err < 0) { 628fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put VEC%u (%d)\n", __func__, i, err); 629fcf5ef2aSThomas Huth ret = err; 630fcf5ef2aSThomas Huth } 631fcf5ef2aSThomas Huth } 632fcf5ef2aSThomas Huth } 633fcf5ef2aSThomas Huth 634fcf5ef2aSThomas Huth return ret; 635fcf5ef2aSThomas Huth } 636fcf5ef2aSThomas Huth 637fcf5ef2aSThomas Huth static int kvm_mips_get_fpu_registers(CPUState *cs) 638fcf5ef2aSThomas Huth { 639fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 640fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 641fcf5ef2aSThomas Huth int err, ret = 0; 642fcf5ef2aSThomas Huth unsigned int i; 643fcf5ef2aSThomas Huth 644fcf5ef2aSThomas Huth /* Only get FPU state if we're emulating a CPU with an FPU */ 645fcf5ef2aSThomas Huth if (env->CP0_Config1 & (1 << CP0C1_FP)) { 646fcf5ef2aSThomas Huth /* FPU Control Registers */ 647fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_IR, 648fcf5ef2aSThomas Huth &env->active_fpu.fcr0); 649fcf5ef2aSThomas Huth if (err < 0) { 650fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FCR_IR (%d)\n", __func__, err); 651fcf5ef2aSThomas Huth ret = err; 652fcf5ef2aSThomas Huth } 653fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_CSR, 654fcf5ef2aSThomas Huth &env->active_fpu.fcr31); 655fcf5ef2aSThomas Huth if (err < 0) { 656fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FCR_CSR (%d)\n", __func__, err); 657fcf5ef2aSThomas Huth ret = err; 658fcf5ef2aSThomas Huth } else { 659fcf5ef2aSThomas Huth restore_fp_status(env); 660fcf5ef2aSThomas Huth } 661fcf5ef2aSThomas Huth 662fcf5ef2aSThomas Huth /* 663fcf5ef2aSThomas Huth * FPU register state is a subset of MSA vector state, so don't save FPU 664fcf5ef2aSThomas Huth * registers if we're emulating a CPU with MSA. 665fcf5ef2aSThomas Huth */ 666fcf5ef2aSThomas Huth if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { 667fcf5ef2aSThomas Huth /* Floating point registers */ 668fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 669fcf5ef2aSThomas Huth if (env->CP0_Status & (1 << CP0St_FR)) { 670fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i), 671fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].d); 672fcf5ef2aSThomas Huth } else { 673fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i), 674fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); 675fcf5ef2aSThomas Huth } 676fcf5ef2aSThomas Huth if (err < 0) { 677fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__, i, err); 678fcf5ef2aSThomas Huth ret = err; 679fcf5ef2aSThomas Huth } 680fcf5ef2aSThomas Huth } 681fcf5ef2aSThomas Huth } 682fcf5ef2aSThomas Huth } 683fcf5ef2aSThomas Huth 684fcf5ef2aSThomas Huth /* Only get MSA state if we're emulating a CPU with MSA */ 685fcf5ef2aSThomas Huth if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { 686fcf5ef2aSThomas Huth /* MSA Control Registers */ 687fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR, 688fcf5ef2aSThomas Huth &env->msair); 689fcf5ef2aSThomas Huth if (err < 0) { 690fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get MSA_IR (%d)\n", __func__, err); 691fcf5ef2aSThomas Huth ret = err; 692fcf5ef2aSThomas Huth } 693fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_CSR, 694fcf5ef2aSThomas Huth &env->active_tc.msacsr); 695fcf5ef2aSThomas Huth if (err < 0) { 696fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get MSA_CSR (%d)\n", __func__, err); 697fcf5ef2aSThomas Huth ret = err; 698fcf5ef2aSThomas Huth } else { 699fcf5ef2aSThomas Huth restore_msa_fp_status(env); 700fcf5ef2aSThomas Huth } 701fcf5ef2aSThomas Huth 702fcf5ef2aSThomas Huth /* Vector registers (includes FP registers) */ 703fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 704fcf5ef2aSThomas Huth /* Big endian MSA not supported by QEMU yet anyway */ 705fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_VEC_128(i), 706fcf5ef2aSThomas Huth env->active_fpu.fpr[i].wr.d); 707fcf5ef2aSThomas Huth if (err < 0) { 708fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get VEC%u (%d)\n", __func__, i, err); 709fcf5ef2aSThomas Huth ret = err; 710fcf5ef2aSThomas Huth } 711fcf5ef2aSThomas Huth } 712fcf5ef2aSThomas Huth } 713fcf5ef2aSThomas Huth 714fcf5ef2aSThomas Huth return ret; 715fcf5ef2aSThomas Huth } 716fcf5ef2aSThomas Huth 717fcf5ef2aSThomas Huth 718fcf5ef2aSThomas Huth static int kvm_mips_put_cp0_registers(CPUState *cs, int level) 719fcf5ef2aSThomas Huth { 720fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 721fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 722fcf5ef2aSThomas Huth int err, ret = 0; 723fcf5ef2aSThomas Huth 724fcf5ef2aSThomas Huth (void)level; 725fcf5ef2aSThomas Huth 726fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); 727fcf5ef2aSThomas Huth if (err < 0) { 728fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err); 729fcf5ef2aSThomas Huth ret = err; 730fcf5ef2aSThomas Huth } 731fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, 732fcf5ef2aSThomas Huth &env->CP0_Context); 733fcf5ef2aSThomas Huth if (err < 0) { 734fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err); 735fcf5ef2aSThomas Huth ret = err; 736fcf5ef2aSThomas Huth } 737fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL, 738fcf5ef2aSThomas Huth &env->active_tc.CP0_UserLocal); 739fcf5ef2aSThomas Huth if (err < 0) { 740fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err); 741fcf5ef2aSThomas Huth ret = err; 742fcf5ef2aSThomas Huth } 743fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK, 744fcf5ef2aSThomas Huth &env->CP0_PageMask); 745fcf5ef2aSThomas Huth if (err < 0) { 746fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err); 747fcf5ef2aSThomas Huth ret = err; 748fcf5ef2aSThomas Huth } 749fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); 750fcf5ef2aSThomas Huth if (err < 0) { 751fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err); 752fcf5ef2aSThomas Huth ret = err; 753fcf5ef2aSThomas Huth } 754fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); 755fcf5ef2aSThomas Huth if (err < 0) { 756fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err); 757fcf5ef2aSThomas Huth ret = err; 758fcf5ef2aSThomas Huth } 759fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR, 760fcf5ef2aSThomas Huth &env->CP0_BadVAddr); 761fcf5ef2aSThomas Huth if (err < 0) { 762fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err); 763fcf5ef2aSThomas Huth ret = err; 764fcf5ef2aSThomas Huth } 765fcf5ef2aSThomas Huth 766fcf5ef2aSThomas Huth /* If VM clock stopped then state will be restored when it is restarted */ 767fcf5ef2aSThomas Huth if (runstate_is_running()) { 768fcf5ef2aSThomas Huth err = kvm_mips_restore_count(cs); 769fcf5ef2aSThomas Huth if (err < 0) { 770fcf5ef2aSThomas Huth ret = err; 771fcf5ef2aSThomas Huth } 772fcf5ef2aSThomas Huth } 773fcf5ef2aSThomas Huth 774fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI, 775fcf5ef2aSThomas Huth &env->CP0_EntryHi); 776fcf5ef2aSThomas Huth if (err < 0) { 777fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err); 778fcf5ef2aSThomas Huth ret = err; 779fcf5ef2aSThomas Huth } 780fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE, 781fcf5ef2aSThomas Huth &env->CP0_Compare); 782fcf5ef2aSThomas Huth if (err < 0) { 783fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err); 784fcf5ef2aSThomas Huth ret = err; 785fcf5ef2aSThomas Huth } 786fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status); 787fcf5ef2aSThomas Huth if (err < 0) { 788fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err); 789fcf5ef2aSThomas Huth ret = err; 790fcf5ef2aSThomas Huth } 791fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC); 792fcf5ef2aSThomas Huth if (err < 0) { 793fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err); 794fcf5ef2aSThomas Huth ret = err; 795fcf5ef2aSThomas Huth } 796fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); 797fcf5ef2aSThomas Huth if (err < 0) { 798fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err); 799fcf5ef2aSThomas Huth ret = err; 800fcf5ef2aSThomas Huth } 801fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, 802fcf5ef2aSThomas Huth &env->CP0_Config0, 803fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG_MASK); 804fcf5ef2aSThomas Huth if (err < 0) { 805fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG (%d)\n", __func__, err); 806fcf5ef2aSThomas Huth ret = err; 807fcf5ef2aSThomas Huth } 808fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, 809fcf5ef2aSThomas Huth &env->CP0_Config1, 810fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG1_MASK); 811fcf5ef2aSThomas Huth if (err < 0) { 812fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG1 (%d)\n", __func__, err); 813fcf5ef2aSThomas Huth ret = err; 814fcf5ef2aSThomas Huth } 815fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2, 816fcf5ef2aSThomas Huth &env->CP0_Config2, 817fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG2_MASK); 818fcf5ef2aSThomas Huth if (err < 0) { 819fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG2 (%d)\n", __func__, err); 820fcf5ef2aSThomas Huth ret = err; 821fcf5ef2aSThomas Huth } 822fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3, 823fcf5ef2aSThomas Huth &env->CP0_Config3, 824fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG3_MASK); 825fcf5ef2aSThomas Huth if (err < 0) { 826fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG3 (%d)\n", __func__, err); 827fcf5ef2aSThomas Huth ret = err; 828fcf5ef2aSThomas Huth } 829fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4, 830fcf5ef2aSThomas Huth &env->CP0_Config4, 831fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG4_MASK); 832fcf5ef2aSThomas Huth if (err < 0) { 833fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG4 (%d)\n", __func__, err); 834fcf5ef2aSThomas Huth ret = err; 835fcf5ef2aSThomas Huth } 836fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, 837fcf5ef2aSThomas Huth &env->CP0_Config5, 838fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG5_MASK); 839fcf5ef2aSThomas Huth if (err < 0) { 840fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG5 (%d)\n", __func__, err); 841fcf5ef2aSThomas Huth ret = err; 842fcf5ef2aSThomas Huth } 843fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, 844fcf5ef2aSThomas Huth &env->CP0_ErrorEPC); 845fcf5ef2aSThomas Huth if (err < 0) { 846fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err); 847fcf5ef2aSThomas Huth ret = err; 848fcf5ef2aSThomas Huth } 849fcf5ef2aSThomas Huth 850fcf5ef2aSThomas Huth return ret; 851fcf5ef2aSThomas Huth } 852fcf5ef2aSThomas Huth 853fcf5ef2aSThomas Huth static int kvm_mips_get_cp0_registers(CPUState *cs) 854fcf5ef2aSThomas Huth { 855fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 856fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 857fcf5ef2aSThomas Huth int err, ret = 0; 858fcf5ef2aSThomas Huth 859fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); 860fcf5ef2aSThomas Huth if (err < 0) { 861fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err); 862fcf5ef2aSThomas Huth ret = err; 863fcf5ef2aSThomas Huth } 864fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, 865fcf5ef2aSThomas Huth &env->CP0_Context); 866fcf5ef2aSThomas Huth if (err < 0) { 867fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err); 868fcf5ef2aSThomas Huth ret = err; 869fcf5ef2aSThomas Huth } 870fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL, 871fcf5ef2aSThomas Huth &env->active_tc.CP0_UserLocal); 872fcf5ef2aSThomas Huth if (err < 0) { 873fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err); 874fcf5ef2aSThomas Huth ret = err; 875fcf5ef2aSThomas Huth } 876fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK, 877fcf5ef2aSThomas Huth &env->CP0_PageMask); 878fcf5ef2aSThomas Huth if (err < 0) { 879fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err); 880fcf5ef2aSThomas Huth ret = err; 881fcf5ef2aSThomas Huth } 882fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); 883fcf5ef2aSThomas Huth if (err < 0) { 884fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err); 885fcf5ef2aSThomas Huth ret = err; 886fcf5ef2aSThomas Huth } 887fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); 888fcf5ef2aSThomas Huth if (err < 0) { 889fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err); 890fcf5ef2aSThomas Huth ret = err; 891fcf5ef2aSThomas Huth } 892fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR, 893fcf5ef2aSThomas Huth &env->CP0_BadVAddr); 894fcf5ef2aSThomas Huth if (err < 0) { 895fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err); 896fcf5ef2aSThomas Huth ret = err; 897fcf5ef2aSThomas Huth } 898fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI, 899fcf5ef2aSThomas Huth &env->CP0_EntryHi); 900fcf5ef2aSThomas Huth if (err < 0) { 901fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err); 902fcf5ef2aSThomas Huth ret = err; 903fcf5ef2aSThomas Huth } 904fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE, 905fcf5ef2aSThomas Huth &env->CP0_Compare); 906fcf5ef2aSThomas Huth if (err < 0) { 907fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err); 908fcf5ef2aSThomas Huth ret = err; 909fcf5ef2aSThomas Huth } 910fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status); 911fcf5ef2aSThomas Huth if (err < 0) { 912fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err); 913fcf5ef2aSThomas Huth ret = err; 914fcf5ef2aSThomas Huth } 915fcf5ef2aSThomas Huth 916fcf5ef2aSThomas Huth /* If VM clock stopped then state was already saved when it was stopped */ 917fcf5ef2aSThomas Huth if (runstate_is_running()) { 918fcf5ef2aSThomas Huth err = kvm_mips_save_count(cs); 919fcf5ef2aSThomas Huth if (err < 0) { 920fcf5ef2aSThomas Huth ret = err; 921fcf5ef2aSThomas Huth } 922fcf5ef2aSThomas Huth } 923fcf5ef2aSThomas Huth 924fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC); 925fcf5ef2aSThomas Huth if (err < 0) { 926fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err); 927fcf5ef2aSThomas Huth ret = err; 928fcf5ef2aSThomas Huth } 929fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); 930fcf5ef2aSThomas Huth if (err < 0) { 931fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err); 932fcf5ef2aSThomas Huth ret = err; 933fcf5ef2aSThomas Huth } 934fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, &env->CP0_Config0); 935fcf5ef2aSThomas Huth if (err < 0) { 936fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG (%d)\n", __func__, err); 937fcf5ef2aSThomas Huth ret = err; 938fcf5ef2aSThomas Huth } 939fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, &env->CP0_Config1); 940fcf5ef2aSThomas Huth if (err < 0) { 941fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG1 (%d)\n", __func__, err); 942fcf5ef2aSThomas Huth ret = err; 943fcf5ef2aSThomas Huth } 944fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2, &env->CP0_Config2); 945fcf5ef2aSThomas Huth if (err < 0) { 946fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG2 (%d)\n", __func__, err); 947fcf5ef2aSThomas Huth ret = err; 948fcf5ef2aSThomas Huth } 949fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3, &env->CP0_Config3); 950fcf5ef2aSThomas Huth if (err < 0) { 951fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG3 (%d)\n", __func__, err); 952fcf5ef2aSThomas Huth ret = err; 953fcf5ef2aSThomas Huth } 954fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4, &env->CP0_Config4); 955fcf5ef2aSThomas Huth if (err < 0) { 956fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG4 (%d)\n", __func__, err); 957fcf5ef2aSThomas Huth ret = err; 958fcf5ef2aSThomas Huth } 959fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, &env->CP0_Config5); 960fcf5ef2aSThomas Huth if (err < 0) { 961fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG5 (%d)\n", __func__, err); 962fcf5ef2aSThomas Huth ret = err; 963fcf5ef2aSThomas Huth } 964fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, 965fcf5ef2aSThomas Huth &env->CP0_ErrorEPC); 966fcf5ef2aSThomas Huth if (err < 0) { 967fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err); 968fcf5ef2aSThomas Huth ret = err; 969fcf5ef2aSThomas Huth } 970fcf5ef2aSThomas Huth 971fcf5ef2aSThomas Huth return ret; 972fcf5ef2aSThomas Huth } 973fcf5ef2aSThomas Huth 974fcf5ef2aSThomas Huth int kvm_arch_put_registers(CPUState *cs, int level) 975fcf5ef2aSThomas Huth { 976fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 977fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 978fcf5ef2aSThomas Huth struct kvm_regs regs; 979fcf5ef2aSThomas Huth int ret; 980fcf5ef2aSThomas Huth int i; 981fcf5ef2aSThomas Huth 982fcf5ef2aSThomas Huth /* Set the registers based on QEMU's view of things */ 983fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 984fcf5ef2aSThomas Huth regs.gpr[i] = (int64_t)(target_long)env->active_tc.gpr[i]; 985fcf5ef2aSThomas Huth } 986fcf5ef2aSThomas Huth 987fcf5ef2aSThomas Huth regs.hi = (int64_t)(target_long)env->active_tc.HI[0]; 988fcf5ef2aSThomas Huth regs.lo = (int64_t)(target_long)env->active_tc.LO[0]; 989fcf5ef2aSThomas Huth regs.pc = (int64_t)(target_long)env->active_tc.PC; 990fcf5ef2aSThomas Huth 991fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); 992fcf5ef2aSThomas Huth 993fcf5ef2aSThomas Huth if (ret < 0) { 994fcf5ef2aSThomas Huth return ret; 995fcf5ef2aSThomas Huth } 996fcf5ef2aSThomas Huth 997fcf5ef2aSThomas Huth ret = kvm_mips_put_cp0_registers(cs, level); 998fcf5ef2aSThomas Huth if (ret < 0) { 999fcf5ef2aSThomas Huth return ret; 1000fcf5ef2aSThomas Huth } 1001fcf5ef2aSThomas Huth 1002fcf5ef2aSThomas Huth ret = kvm_mips_put_fpu_registers(cs, level); 1003fcf5ef2aSThomas Huth if (ret < 0) { 1004fcf5ef2aSThomas Huth return ret; 1005fcf5ef2aSThomas Huth } 1006fcf5ef2aSThomas Huth 1007fcf5ef2aSThomas Huth return ret; 1008fcf5ef2aSThomas Huth } 1009fcf5ef2aSThomas Huth 1010fcf5ef2aSThomas Huth int kvm_arch_get_registers(CPUState *cs) 1011fcf5ef2aSThomas Huth { 1012fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 1013fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 1014fcf5ef2aSThomas Huth int ret = 0; 1015fcf5ef2aSThomas Huth struct kvm_regs regs; 1016fcf5ef2aSThomas Huth int i; 1017fcf5ef2aSThomas Huth 1018fcf5ef2aSThomas Huth /* Get the current register set as KVM seems it */ 1019fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 1020fcf5ef2aSThomas Huth 1021fcf5ef2aSThomas Huth if (ret < 0) { 1022fcf5ef2aSThomas Huth return ret; 1023fcf5ef2aSThomas Huth } 1024fcf5ef2aSThomas Huth 1025fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 1026fcf5ef2aSThomas Huth env->active_tc.gpr[i] = regs.gpr[i]; 1027fcf5ef2aSThomas Huth } 1028fcf5ef2aSThomas Huth 1029fcf5ef2aSThomas Huth env->active_tc.HI[0] = regs.hi; 1030fcf5ef2aSThomas Huth env->active_tc.LO[0] = regs.lo; 1031fcf5ef2aSThomas Huth env->active_tc.PC = regs.pc; 1032fcf5ef2aSThomas Huth 1033fcf5ef2aSThomas Huth kvm_mips_get_cp0_registers(cs); 1034fcf5ef2aSThomas Huth kvm_mips_get_fpu_registers(cs); 1035fcf5ef2aSThomas Huth 1036fcf5ef2aSThomas Huth return ret; 1037fcf5ef2aSThomas Huth } 1038fcf5ef2aSThomas Huth 1039fcf5ef2aSThomas Huth int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1040fcf5ef2aSThomas Huth uint64_t address, uint32_t data, PCIDevice *dev) 1041fcf5ef2aSThomas Huth { 1042fcf5ef2aSThomas Huth return 0; 1043fcf5ef2aSThomas Huth } 1044fcf5ef2aSThomas Huth 1045fcf5ef2aSThomas Huth int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1046fcf5ef2aSThomas Huth int vector, PCIDevice *dev) 1047fcf5ef2aSThomas Huth { 1048fcf5ef2aSThomas Huth return 0; 1049fcf5ef2aSThomas Huth } 1050fcf5ef2aSThomas Huth 1051fcf5ef2aSThomas Huth int kvm_arch_release_virq_post(int virq) 1052fcf5ef2aSThomas Huth { 1053fcf5ef2aSThomas Huth return 0; 1054fcf5ef2aSThomas Huth } 1055fcf5ef2aSThomas Huth 1056fcf5ef2aSThomas Huth int kvm_arch_msi_data_to_gsi(uint32_t data) 1057fcf5ef2aSThomas Huth { 1058fcf5ef2aSThomas Huth abort(); 1059fcf5ef2aSThomas Huth } 1060