1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * This file is subject to the terms and conditions of the GNU General Public 3fcf5ef2aSThomas Huth * License. See the file "COPYING" in the main directory of this archive 4fcf5ef2aSThomas Huth * for more details. 5fcf5ef2aSThomas Huth * 6fcf5ef2aSThomas Huth * KVM/MIPS: MIPS specific KVM APIs 7fcf5ef2aSThomas Huth * 8fcf5ef2aSThomas Huth * Copyright (C) 2012-2014 Imagination Technologies Ltd. 9fcf5ef2aSThomas Huth * Authors: Sanjay Lal <sanjayl@kymasys.com> 10fcf5ef2aSThomas Huth */ 11fcf5ef2aSThomas Huth 12fcf5ef2aSThomas Huth #include "qemu/osdep.h" 13fcf5ef2aSThomas Huth #include <sys/ioctl.h> 14fcf5ef2aSThomas Huth 15fcf5ef2aSThomas Huth #include <linux/kvm.h> 16fcf5ef2aSThomas Huth 17fcf5ef2aSThomas Huth #include "cpu.h" 1826aa3d9aSPhilippe Mathieu-Daudé #include "internal.h" 19fcf5ef2aSThomas Huth #include "qemu/error-report.h" 20db725815SMarkus Armbruster #include "qemu/main-loop.h" 21fcf5ef2aSThomas Huth #include "sysemu/kvm.h" 22719d109bSHuacai Chen #include "sysemu/kvm_int.h" 2354d31236SMarkus Armbruster #include "sysemu/runstate.h" 24fcf5ef2aSThomas Huth #include "kvm_mips.h" 25719d109bSHuacai Chen #include "hw/boards.h" 2681ddae7cSPhilippe Mathieu-Daudé #include "fpu_helper.h" 27fcf5ef2aSThomas Huth 28fcf5ef2aSThomas Huth #define DEBUG_KVM 0 29fcf5ef2aSThomas Huth 30fcf5ef2aSThomas Huth #define DPRINTF(fmt, ...) \ 31fcf5ef2aSThomas Huth do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0) 32fcf5ef2aSThomas Huth 33fcf5ef2aSThomas Huth static int kvm_mips_fpu_cap; 34fcf5ef2aSThomas Huth static int kvm_mips_msa_cap; 35fcf5ef2aSThomas Huth 36fcf5ef2aSThomas Huth const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 37fcf5ef2aSThomas Huth KVM_CAP_LAST_INFO 38fcf5ef2aSThomas Huth }; 39fcf5ef2aSThomas Huth 40538f0497SPhilippe Mathieu-Daudé static void kvm_mips_update_state(void *opaque, bool running, RunState state); 41fcf5ef2aSThomas Huth 42fcf5ef2aSThomas Huth unsigned long kvm_arch_vcpu_id(CPUState *cs) 43fcf5ef2aSThomas Huth { 44fcf5ef2aSThomas Huth return cs->cpu_index; 45fcf5ef2aSThomas Huth } 46fcf5ef2aSThomas Huth 47fcf5ef2aSThomas Huth int kvm_arch_init(MachineState *ms, KVMState *s) 48fcf5ef2aSThomas Huth { 49fcf5ef2aSThomas Huth /* MIPS has 128 signals */ 50fcf5ef2aSThomas Huth kvm_set_sigmask_len(s, 16); 51fcf5ef2aSThomas Huth 52fcf5ef2aSThomas Huth kvm_mips_fpu_cap = kvm_check_extension(s, KVM_CAP_MIPS_FPU); 53fcf5ef2aSThomas Huth kvm_mips_msa_cap = kvm_check_extension(s, KVM_CAP_MIPS_MSA); 54fcf5ef2aSThomas Huth 55fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 56fcf5ef2aSThomas Huth return 0; 57fcf5ef2aSThomas Huth } 58fcf5ef2aSThomas Huth 594376c40dSPaolo Bonzini int kvm_arch_irqchip_create(KVMState *s) 60d525ffabSPaolo Bonzini { 61d525ffabSPaolo Bonzini return 0; 62d525ffabSPaolo Bonzini } 63d525ffabSPaolo Bonzini 64fcf5ef2aSThomas Huth int kvm_arch_init_vcpu(CPUState *cs) 65fcf5ef2aSThomas Huth { 66fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 67fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 68fcf5ef2aSThomas Huth int ret = 0; 69fcf5ef2aSThomas Huth 70fcf5ef2aSThomas Huth qemu_add_vm_change_state_handler(kvm_mips_update_state, cs); 71fcf5ef2aSThomas Huth 72fcf5ef2aSThomas Huth if (kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) { 73fcf5ef2aSThomas Huth ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_FPU, 0, 0); 74fcf5ef2aSThomas Huth if (ret < 0) { 75fcf5ef2aSThomas Huth /* mark unsupported so it gets disabled on reset */ 76fcf5ef2aSThomas Huth kvm_mips_fpu_cap = 0; 77fcf5ef2aSThomas Huth ret = 0; 78fcf5ef2aSThomas Huth } 79fcf5ef2aSThomas Huth } 80fcf5ef2aSThomas Huth 8125a13628SPhilippe Mathieu-Daudé if (kvm_mips_msa_cap && ase_msa_available(env)) { 82fcf5ef2aSThomas Huth ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0); 83fcf5ef2aSThomas Huth if (ret < 0) { 84fcf5ef2aSThomas Huth /* mark unsupported so it gets disabled on reset */ 85fcf5ef2aSThomas Huth kvm_mips_msa_cap = 0; 86fcf5ef2aSThomas Huth ret = 0; 87fcf5ef2aSThomas Huth } 88fcf5ef2aSThomas Huth } 89fcf5ef2aSThomas Huth 90fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 91fcf5ef2aSThomas Huth return ret; 92fcf5ef2aSThomas Huth } 93fcf5ef2aSThomas Huth 94b1115c99SLiran Alon int kvm_arch_destroy_vcpu(CPUState *cs) 95b1115c99SLiran Alon { 96b1115c99SLiran Alon return 0; 97b1115c99SLiran Alon } 98b1115c99SLiran Alon 99fcf5ef2aSThomas Huth void kvm_mips_reset_vcpu(MIPSCPU *cpu) 100fcf5ef2aSThomas Huth { 101fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 102fcf5ef2aSThomas Huth 103fcf5ef2aSThomas Huth if (!kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) { 1042ab4b135SAlistair Francis warn_report("KVM does not support FPU, disabling"); 105fcf5ef2aSThomas Huth env->CP0_Config1 &= ~(1 << CP0C1_FP); 106fcf5ef2aSThomas Huth } 10725a13628SPhilippe Mathieu-Daudé if (!kvm_mips_msa_cap && ase_msa_available(env)) { 1082ab4b135SAlistair Francis warn_report("KVM does not support MSA, disabling"); 109fcf5ef2aSThomas Huth env->CP0_Config3 &= ~(1 << CP0C3_MSAP); 110fcf5ef2aSThomas Huth } 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 113fcf5ef2aSThomas Huth } 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 116fcf5ef2aSThomas Huth { 117fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 118fcf5ef2aSThomas Huth return 0; 119fcf5ef2aSThomas Huth } 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 122fcf5ef2aSThomas Huth { 123fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 124fcf5ef2aSThomas Huth return 0; 125fcf5ef2aSThomas Huth } 126fcf5ef2aSThomas Huth 127fcf5ef2aSThomas Huth static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu) 128fcf5ef2aSThomas Huth { 129fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 130fcf5ef2aSThomas Huth 131fcf5ef2aSThomas Huth return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP)); 132fcf5ef2aSThomas Huth } 133fcf5ef2aSThomas Huth 134fcf5ef2aSThomas Huth 135fcf5ef2aSThomas Huth void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 136fcf5ef2aSThomas Huth { 137fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 138fcf5ef2aSThomas Huth int r; 139fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 140fcf5ef2aSThomas Huth 141fcf5ef2aSThomas Huth qemu_mutex_lock_iothread(); 142fcf5ef2aSThomas Huth 143fcf5ef2aSThomas Huth if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 144fcf5ef2aSThomas Huth cpu_mips_io_interrupts_pending(cpu)) { 145fcf5ef2aSThomas Huth intr.cpu = -1; 146fcf5ef2aSThomas Huth intr.irq = 2; 147fcf5ef2aSThomas Huth r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 148fcf5ef2aSThomas Huth if (r < 0) { 149fcf5ef2aSThomas Huth error_report("%s: cpu %d: failed to inject IRQ %x", 150fcf5ef2aSThomas Huth __func__, cs->cpu_index, intr.irq); 151fcf5ef2aSThomas Huth } 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth qemu_mutex_unlock_iothread(); 155fcf5ef2aSThomas Huth } 156fcf5ef2aSThomas Huth 157fcf5ef2aSThomas Huth MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 158fcf5ef2aSThomas Huth { 159fcf5ef2aSThomas Huth return MEMTXATTRS_UNSPECIFIED; 160fcf5ef2aSThomas Huth } 161fcf5ef2aSThomas Huth 162fcf5ef2aSThomas Huth int kvm_arch_process_async_events(CPUState *cs) 163fcf5ef2aSThomas Huth { 164fcf5ef2aSThomas Huth return cs->halted; 165fcf5ef2aSThomas Huth } 166fcf5ef2aSThomas Huth 167fcf5ef2aSThomas Huth int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 168fcf5ef2aSThomas Huth { 169fcf5ef2aSThomas Huth int ret; 170fcf5ef2aSThomas Huth 171fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 172fcf5ef2aSThomas Huth switch (run->exit_reason) { 173fcf5ef2aSThomas Huth default: 174fcf5ef2aSThomas Huth error_report("%s: unknown exit reason %d", 175fcf5ef2aSThomas Huth __func__, run->exit_reason); 176fcf5ef2aSThomas Huth ret = -1; 177fcf5ef2aSThomas Huth break; 178fcf5ef2aSThomas Huth } 179fcf5ef2aSThomas Huth 180fcf5ef2aSThomas Huth return ret; 181fcf5ef2aSThomas Huth } 182fcf5ef2aSThomas Huth 183fcf5ef2aSThomas Huth bool kvm_arch_stop_on_emulation_error(CPUState *cs) 184fcf5ef2aSThomas Huth { 185fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 186fcf5ef2aSThomas Huth return true; 187fcf5ef2aSThomas Huth } 188fcf5ef2aSThomas Huth 189fcf5ef2aSThomas Huth void kvm_arch_init_irq_routing(KVMState *s) 190fcf5ef2aSThomas Huth { 191fcf5ef2aSThomas Huth } 192fcf5ef2aSThomas Huth 193fcf5ef2aSThomas Huth int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level) 194fcf5ef2aSThomas Huth { 195fcf5ef2aSThomas Huth CPUState *cs = CPU(cpu); 196fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 197fcf5ef2aSThomas Huth 19811cb076bSPhilippe Mathieu-Daudé assert(kvm_enabled()); 199fcf5ef2aSThomas Huth 200fcf5ef2aSThomas Huth intr.cpu = -1; 201fcf5ef2aSThomas Huth 202fcf5ef2aSThomas Huth if (level) { 203fcf5ef2aSThomas Huth intr.irq = irq; 204fcf5ef2aSThomas Huth } else { 205fcf5ef2aSThomas Huth intr.irq = -irq; 206fcf5ef2aSThomas Huth } 207fcf5ef2aSThomas Huth 208fcf5ef2aSThomas Huth kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 209fcf5ef2aSThomas Huth 210fcf5ef2aSThomas Huth return 0; 211fcf5ef2aSThomas Huth } 212fcf5ef2aSThomas Huth 213fcf5ef2aSThomas Huth int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) 214fcf5ef2aSThomas Huth { 215fcf5ef2aSThomas Huth CPUState *cs = current_cpu; 216fcf5ef2aSThomas Huth CPUState *dest_cs = CPU(cpu); 217fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 218fcf5ef2aSThomas Huth 21911cb076bSPhilippe Mathieu-Daudé assert(kvm_enabled()); 220fcf5ef2aSThomas Huth 221fcf5ef2aSThomas Huth intr.cpu = dest_cs->cpu_index; 222fcf5ef2aSThomas Huth 223fcf5ef2aSThomas Huth if (level) { 224fcf5ef2aSThomas Huth intr.irq = irq; 225fcf5ef2aSThomas Huth } else { 226fcf5ef2aSThomas Huth intr.irq = -irq; 227fcf5ef2aSThomas Huth } 228fcf5ef2aSThomas Huth 229fcf5ef2aSThomas Huth DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq); 230fcf5ef2aSThomas Huth 231fcf5ef2aSThomas Huth kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 232fcf5ef2aSThomas Huth 233fcf5ef2aSThomas Huth return 0; 234fcf5ef2aSThomas Huth } 235fcf5ef2aSThomas Huth 236fcf5ef2aSThomas Huth #define MIPS_CP0_32(_R, _S) \ 237fcf5ef2aSThomas Huth (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S))) 238fcf5ef2aSThomas Huth 239fcf5ef2aSThomas Huth #define MIPS_CP0_64(_R, _S) \ 240fcf5ef2aSThomas Huth (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) 241fcf5ef2aSThomas Huth 242fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) 2437e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_RANDOM MIPS_CP0_32(1, 0) 244fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) 245fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) 246fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) 2477e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) 2487e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5) 2497e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6) 2507e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7) 251fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) 2527e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6) 253fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) 254fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) 255fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) 256fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) 257fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) 258fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) 259fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) 260fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) 261fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) 2627e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) 263fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) 264fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) 265fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) 266fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) 267fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) 268fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) 2697e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_CONFIG6 MIPS_CP0_32(16, 6) 2707e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) 271fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) 2727e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2) 2737e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3) 2747e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4) 2757e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5) 2767e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6) 2777e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7) 278fcf5ef2aSThomas Huth 279fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, 280fcf5ef2aSThomas Huth int32_t *addr) 281fcf5ef2aSThomas Huth { 282fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 283fcf5ef2aSThomas Huth .id = reg_id, 284fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 285fcf5ef2aSThomas Huth }; 286fcf5ef2aSThomas Huth 287fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 288fcf5ef2aSThomas Huth } 289fcf5ef2aSThomas Huth 290fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ureg(CPUState *cs, uint64_t reg_id, 291fcf5ef2aSThomas Huth uint32_t *addr) 292fcf5ef2aSThomas Huth { 293fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 294fcf5ef2aSThomas Huth .id = reg_id, 295fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 296fcf5ef2aSThomas Huth }; 297fcf5ef2aSThomas Huth 298fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 299fcf5ef2aSThomas Huth } 300fcf5ef2aSThomas Huth 301fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id, 302fcf5ef2aSThomas Huth target_ulong *addr) 303fcf5ef2aSThomas Huth { 304fcf5ef2aSThomas Huth uint64_t val64 = *addr; 305fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 306fcf5ef2aSThomas Huth .id = reg_id, 307fcf5ef2aSThomas Huth .addr = (uintptr_t)&val64 308fcf5ef2aSThomas Huth }; 309fcf5ef2aSThomas Huth 310fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 311fcf5ef2aSThomas Huth } 312fcf5ef2aSThomas Huth 313fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id, 314fcf5ef2aSThomas Huth int64_t *addr) 315fcf5ef2aSThomas Huth { 316fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 317fcf5ef2aSThomas Huth .id = reg_id, 318fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 319fcf5ef2aSThomas Huth }; 320fcf5ef2aSThomas Huth 321fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 322fcf5ef2aSThomas Huth } 323fcf5ef2aSThomas Huth 324fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ureg64(CPUState *cs, uint64_t reg_id, 325fcf5ef2aSThomas Huth uint64_t *addr) 326fcf5ef2aSThomas Huth { 327fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 328fcf5ef2aSThomas Huth .id = reg_id, 329fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 330fcf5ef2aSThomas Huth }; 331fcf5ef2aSThomas Huth 332fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 333fcf5ef2aSThomas Huth } 334fcf5ef2aSThomas Huth 335fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id, 336fcf5ef2aSThomas Huth int32_t *addr) 337fcf5ef2aSThomas Huth { 338fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 339fcf5ef2aSThomas Huth .id = reg_id, 340fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 341fcf5ef2aSThomas Huth }; 342fcf5ef2aSThomas Huth 343fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 344fcf5ef2aSThomas Huth } 345fcf5ef2aSThomas Huth 346fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ureg(CPUState *cs, uint64_t reg_id, 347fcf5ef2aSThomas Huth uint32_t *addr) 348fcf5ef2aSThomas Huth { 349fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 350fcf5ef2aSThomas Huth .id = reg_id, 351fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 352fcf5ef2aSThomas Huth }; 353fcf5ef2aSThomas Huth 354fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 355fcf5ef2aSThomas Huth } 356fcf5ef2aSThomas Huth 357fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64_t reg_id, 358fcf5ef2aSThomas Huth target_ulong *addr) 359fcf5ef2aSThomas Huth { 360fcf5ef2aSThomas Huth int ret; 361fcf5ef2aSThomas Huth uint64_t val64 = 0; 362fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 363fcf5ef2aSThomas Huth .id = reg_id, 364fcf5ef2aSThomas Huth .addr = (uintptr_t)&val64 365fcf5ef2aSThomas Huth }; 366fcf5ef2aSThomas Huth 367fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 368fcf5ef2aSThomas Huth if (ret >= 0) { 369fcf5ef2aSThomas Huth *addr = val64; 370fcf5ef2aSThomas Huth } 371fcf5ef2aSThomas Huth return ret; 372fcf5ef2aSThomas Huth } 373fcf5ef2aSThomas Huth 374fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64_t reg_id, 375fcf5ef2aSThomas Huth int64_t *addr) 376fcf5ef2aSThomas Huth { 377fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 378fcf5ef2aSThomas Huth .id = reg_id, 379fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 380fcf5ef2aSThomas Huth }; 381fcf5ef2aSThomas Huth 382fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 383fcf5ef2aSThomas Huth } 384fcf5ef2aSThomas Huth 385fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ureg64(CPUState *cs, uint64_t reg_id, 386fcf5ef2aSThomas Huth uint64_t *addr) 387fcf5ef2aSThomas Huth { 388fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 389fcf5ef2aSThomas Huth .id = reg_id, 390fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 391fcf5ef2aSThomas Huth }; 392fcf5ef2aSThomas Huth 393fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 394fcf5ef2aSThomas Huth } 395fcf5ef2aSThomas Huth 396fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M) 397fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG1_MASK ((1U << CP0C1_M) | \ 398fcf5ef2aSThomas Huth (1U << CP0C1_FP)) 399fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG2_MASK (1U << CP0C2_M) 400fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG3_MASK ((1U << CP0C3_M) | \ 401fcf5ef2aSThomas Huth (1U << CP0C3_MSAP)) 402fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG4_MASK (1U << CP0C4_M) 403fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG5_MASK ((1U << CP0C5_MSAEn) | \ 404fcf5ef2aSThomas Huth (1U << CP0C5_UFE) | \ 405fcf5ef2aSThomas Huth (1U << CP0C5_FRE) | \ 406fcf5ef2aSThomas Huth (1U << CP0C5_UFR)) 4077e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ 4087e0896b0SHuacai Chen (0x3fU << CP0C6_KPOS) | \ 4097e0896b0SHuacai Chen (1U << CP0C6_KE) | \ 4107e0896b0SHuacai Chen (1U << CP0C6_VTLBONLY) | \ 4117e0896b0SHuacai Chen (1U << CP0C6_LASX) | \ 4127e0896b0SHuacai Chen (1U << CP0C6_SSEN) | \ 4137e0896b0SHuacai Chen (1U << CP0C6_DISDRTIME) | \ 4147e0896b0SHuacai Chen (1U << CP0C6_PIXNUEN) | \ 4157e0896b0SHuacai Chen (1U << CP0C6_SCRAND) | \ 4167e0896b0SHuacai Chen (1U << CP0C6_LLEXCEN) | \ 4177e0896b0SHuacai Chen (1U << CP0C6_DISVC) | \ 4187e0896b0SHuacai Chen (1U << CP0C6_VCLRU) | \ 4197e0896b0SHuacai Chen (1U << CP0C6_DCLRU) | \ 4207e0896b0SHuacai Chen (1U << CP0C6_PIXUEN) | \ 4217e0896b0SHuacai Chen (1U << CP0C6_DISBLKLYEN) | \ 4227e0896b0SHuacai Chen (1U << CP0C6_UMEMUALEN) | \ 4237e0896b0SHuacai Chen (1U << CP0C6_SFBEN) | \ 4247e0896b0SHuacai Chen (1U << CP0C6_FLTINT) | \ 4257e0896b0SHuacai Chen (1U << CP0C6_VLTINT) | \ 4267e0896b0SHuacai Chen (1U << CP0C6_DISBTB) | \ 4277e0896b0SHuacai Chen (3U << CP0C6_STPREFCTL) | \ 4287e0896b0SHuacai Chen (1U << CP0C6_INSTPREF) | \ 4297e0896b0SHuacai Chen (1U << CP0C6_DATAPREF)) 430fcf5ef2aSThomas Huth 431fcf5ef2aSThomas Huth static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id, 432fcf5ef2aSThomas Huth int32_t *addr, int32_t mask) 433fcf5ef2aSThomas Huth { 434fcf5ef2aSThomas Huth int err; 435fcf5ef2aSThomas Huth int32_t tmp, change; 436fcf5ef2aSThomas Huth 437fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, reg_id, &tmp); 438fcf5ef2aSThomas Huth if (err < 0) { 439fcf5ef2aSThomas Huth return err; 440fcf5ef2aSThomas Huth } 441fcf5ef2aSThomas Huth 442fcf5ef2aSThomas Huth /* only change bits in mask */ 443fcf5ef2aSThomas Huth change = (*addr ^ tmp) & mask; 444fcf5ef2aSThomas Huth if (!change) { 445fcf5ef2aSThomas Huth return 0; 446fcf5ef2aSThomas Huth } 447fcf5ef2aSThomas Huth 448fcf5ef2aSThomas Huth tmp = tmp ^ change; 449fcf5ef2aSThomas Huth return kvm_mips_put_one_reg(cs, reg_id, &tmp); 450fcf5ef2aSThomas Huth } 451fcf5ef2aSThomas Huth 452fcf5ef2aSThomas Huth /* 453fcf5ef2aSThomas Huth * We freeze the KVM timer when either the VM clock is stopped or the state is 454fcf5ef2aSThomas Huth * saved (the state is dirty). 455fcf5ef2aSThomas Huth */ 456fcf5ef2aSThomas Huth 457fcf5ef2aSThomas Huth /* 458fcf5ef2aSThomas Huth * Save the state of the KVM timer when VM clock is stopped or state is synced 459fcf5ef2aSThomas Huth * to QEMU. 460fcf5ef2aSThomas Huth */ 461fcf5ef2aSThomas Huth static int kvm_mips_save_count(CPUState *cs) 462fcf5ef2aSThomas Huth { 463fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 464fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 465fcf5ef2aSThomas Huth uint64_t count_ctl; 466fcf5ef2aSThomas Huth int err, ret = 0; 467fcf5ef2aSThomas Huth 468fcf5ef2aSThomas Huth /* freeze KVM timer */ 469fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 470fcf5ef2aSThomas Huth if (err < 0) { 471fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err); 472fcf5ef2aSThomas Huth ret = err; 473fcf5ef2aSThomas Huth } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) { 474fcf5ef2aSThomas Huth count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC; 475fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 476fcf5ef2aSThomas Huth if (err < 0) { 477fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err); 478fcf5ef2aSThomas Huth ret = err; 479fcf5ef2aSThomas Huth } 480fcf5ef2aSThomas Huth } 481fcf5ef2aSThomas Huth 482fcf5ef2aSThomas Huth /* read CP0_Cause */ 483fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause); 484fcf5ef2aSThomas Huth if (err < 0) { 485fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err); 486fcf5ef2aSThomas Huth ret = err; 487fcf5ef2aSThomas Huth } 488fcf5ef2aSThomas Huth 489fcf5ef2aSThomas Huth /* read CP0_Count */ 490fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count); 491fcf5ef2aSThomas Huth if (err < 0) { 492fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err); 493fcf5ef2aSThomas Huth ret = err; 494fcf5ef2aSThomas Huth } 495fcf5ef2aSThomas Huth 496fcf5ef2aSThomas Huth return ret; 497fcf5ef2aSThomas Huth } 498fcf5ef2aSThomas Huth 499fcf5ef2aSThomas Huth /* 500fcf5ef2aSThomas Huth * Restore the state of the KVM timer when VM clock is restarted or state is 501fcf5ef2aSThomas Huth * synced to KVM. 502fcf5ef2aSThomas Huth */ 503fcf5ef2aSThomas Huth static int kvm_mips_restore_count(CPUState *cs) 504fcf5ef2aSThomas Huth { 505fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 506fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 507fcf5ef2aSThomas Huth uint64_t count_ctl; 508fcf5ef2aSThomas Huth int err_dc, err, ret = 0; 509fcf5ef2aSThomas Huth 510fcf5ef2aSThomas Huth /* check the timer is frozen */ 511fcf5ef2aSThomas Huth err_dc = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 512fcf5ef2aSThomas Huth if (err_dc < 0) { 513fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc); 514fcf5ef2aSThomas Huth ret = err_dc; 515fcf5ef2aSThomas Huth } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) { 516fcf5ef2aSThomas Huth /* freeze timer (sets COUNT_RESUME for us) */ 517fcf5ef2aSThomas Huth count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC; 518fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 519fcf5ef2aSThomas Huth if (err < 0) { 520fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err); 521fcf5ef2aSThomas Huth ret = err; 522fcf5ef2aSThomas Huth } 523fcf5ef2aSThomas Huth } 524fcf5ef2aSThomas Huth 525fcf5ef2aSThomas Huth /* load CP0_Cause */ 526fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause); 527fcf5ef2aSThomas Huth if (err < 0) { 528fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err); 529fcf5ef2aSThomas Huth ret = err; 530fcf5ef2aSThomas Huth } 531fcf5ef2aSThomas Huth 532fcf5ef2aSThomas Huth /* load CP0_Count */ 533fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count); 534fcf5ef2aSThomas Huth if (err < 0) { 535fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err); 536fcf5ef2aSThomas Huth ret = err; 537fcf5ef2aSThomas Huth } 538fcf5ef2aSThomas Huth 539fcf5ef2aSThomas Huth /* resume KVM timer */ 540fcf5ef2aSThomas Huth if (err_dc >= 0) { 541fcf5ef2aSThomas Huth count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC; 542fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 543fcf5ef2aSThomas Huth if (err < 0) { 544fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err); 545fcf5ef2aSThomas Huth ret = err; 546fcf5ef2aSThomas Huth } 547fcf5ef2aSThomas Huth } 548fcf5ef2aSThomas Huth 549fcf5ef2aSThomas Huth return ret; 550fcf5ef2aSThomas Huth } 551fcf5ef2aSThomas Huth 552fcf5ef2aSThomas Huth /* 553fcf5ef2aSThomas Huth * Handle the VM clock being started or stopped 554fcf5ef2aSThomas Huth */ 555538f0497SPhilippe Mathieu-Daudé static void kvm_mips_update_state(void *opaque, bool running, RunState state) 556fcf5ef2aSThomas Huth { 557fcf5ef2aSThomas Huth CPUState *cs = opaque; 558fcf5ef2aSThomas Huth int ret; 559fcf5ef2aSThomas Huth uint64_t count_resume; 560fcf5ef2aSThomas Huth 561fcf5ef2aSThomas Huth /* 562fcf5ef2aSThomas Huth * If state is already dirty (synced to QEMU) then the KVM timer state is 563fcf5ef2aSThomas Huth * already saved and can be restored when it is synced back to KVM. 564fcf5ef2aSThomas Huth */ 565fcf5ef2aSThomas Huth if (!running) { 56699f31832SSergio Andres Gomez Del Real if (!cs->vcpu_dirty) { 567fcf5ef2aSThomas Huth ret = kvm_mips_save_count(cs); 568fcf5ef2aSThomas Huth if (ret < 0) { 569288cb949SAlistair Francis warn_report("Failed saving count"); 570fcf5ef2aSThomas Huth } 571fcf5ef2aSThomas Huth } 572fcf5ef2aSThomas Huth } else { 573fcf5ef2aSThomas Huth /* Set clock restore time to now */ 574fcf5ef2aSThomas Huth count_resume = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 575fcf5ef2aSThomas Huth ret = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_RESUME, 576fcf5ef2aSThomas Huth &count_resume); 577fcf5ef2aSThomas Huth if (ret < 0) { 578288cb949SAlistair Francis warn_report("Failed setting COUNT_RESUME"); 579fcf5ef2aSThomas Huth return; 580fcf5ef2aSThomas Huth } 581fcf5ef2aSThomas Huth 58299f31832SSergio Andres Gomez Del Real if (!cs->vcpu_dirty) { 583fcf5ef2aSThomas Huth ret = kvm_mips_restore_count(cs); 584fcf5ef2aSThomas Huth if (ret < 0) { 585288cb949SAlistair Francis warn_report("Failed restoring count"); 586fcf5ef2aSThomas Huth } 587fcf5ef2aSThomas Huth } 588fcf5ef2aSThomas Huth } 589fcf5ef2aSThomas Huth } 590fcf5ef2aSThomas Huth 591fcf5ef2aSThomas Huth static int kvm_mips_put_fpu_registers(CPUState *cs, int level) 592fcf5ef2aSThomas Huth { 593fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 594fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 595fcf5ef2aSThomas Huth int err, ret = 0; 596fcf5ef2aSThomas Huth unsigned int i; 597fcf5ef2aSThomas Huth 598fcf5ef2aSThomas Huth /* Only put FPU state if we're emulating a CPU with an FPU */ 599fcf5ef2aSThomas Huth if (env->CP0_Config1 & (1 << CP0C1_FP)) { 600fcf5ef2aSThomas Huth /* FPU Control Registers */ 601fcf5ef2aSThomas Huth if (level == KVM_PUT_FULL_STATE) { 602fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg(cs, KVM_REG_MIPS_FCR_IR, 603fcf5ef2aSThomas Huth &env->active_fpu.fcr0); 604fcf5ef2aSThomas Huth if (err < 0) { 605fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FCR_IR (%d)\n", __func__, err); 606fcf5ef2aSThomas Huth ret = err; 607fcf5ef2aSThomas Huth } 608fcf5ef2aSThomas Huth } 609fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg(cs, KVM_REG_MIPS_FCR_CSR, 610fcf5ef2aSThomas Huth &env->active_fpu.fcr31); 611fcf5ef2aSThomas Huth if (err < 0) { 612fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FCR_CSR (%d)\n", __func__, err); 613fcf5ef2aSThomas Huth ret = err; 614fcf5ef2aSThomas Huth } 615fcf5ef2aSThomas Huth 616fcf5ef2aSThomas Huth /* 617fcf5ef2aSThomas Huth * FPU register state is a subset of MSA vector state, so don't put FPU 618fcf5ef2aSThomas Huth * registers if we're emulating a CPU with MSA. 619fcf5ef2aSThomas Huth */ 62025a13628SPhilippe Mathieu-Daudé if (!ase_msa_available(env)) { 621fcf5ef2aSThomas Huth /* Floating point registers */ 622fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 623fcf5ef2aSThomas Huth if (env->CP0_Status & (1 << CP0St_FR)) { 624fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i), 625fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].d); 626fcf5ef2aSThomas Huth } else { 627fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i), 628fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); 629fcf5ef2aSThomas Huth } 630fcf5ef2aSThomas Huth if (err < 0) { 631fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FPR%u (%d)\n", __func__, i, err); 632fcf5ef2aSThomas Huth ret = err; 633fcf5ef2aSThomas Huth } 634fcf5ef2aSThomas Huth } 635fcf5ef2aSThomas Huth } 636fcf5ef2aSThomas Huth } 637fcf5ef2aSThomas Huth 638fcf5ef2aSThomas Huth /* Only put MSA state if we're emulating a CPU with MSA */ 63925a13628SPhilippe Mathieu-Daudé if (ase_msa_available(env)) { 640fcf5ef2aSThomas Huth /* MSA Control Registers */ 641fcf5ef2aSThomas Huth if (level == KVM_PUT_FULL_STATE) { 642fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_IR, 643fcf5ef2aSThomas Huth &env->msair); 644fcf5ef2aSThomas Huth if (err < 0) { 645fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put MSA_IR (%d)\n", __func__, err); 646fcf5ef2aSThomas Huth ret = err; 647fcf5ef2aSThomas Huth } 648fcf5ef2aSThomas Huth } 649fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_CSR, 650fcf5ef2aSThomas Huth &env->active_tc.msacsr); 651fcf5ef2aSThomas Huth if (err < 0) { 652fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put MSA_CSR (%d)\n", __func__, err); 653fcf5ef2aSThomas Huth ret = err; 654fcf5ef2aSThomas Huth } 655fcf5ef2aSThomas Huth 656fcf5ef2aSThomas Huth /* Vector registers (includes FP registers) */ 657fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 658fcf5ef2aSThomas Huth /* Big endian MSA not supported by QEMU yet anyway */ 659fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_VEC_128(i), 660fcf5ef2aSThomas Huth env->active_fpu.fpr[i].wr.d); 661fcf5ef2aSThomas Huth if (err < 0) { 662fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put VEC%u (%d)\n", __func__, i, err); 663fcf5ef2aSThomas Huth ret = err; 664fcf5ef2aSThomas Huth } 665fcf5ef2aSThomas Huth } 666fcf5ef2aSThomas Huth } 667fcf5ef2aSThomas Huth 668fcf5ef2aSThomas Huth return ret; 669fcf5ef2aSThomas Huth } 670fcf5ef2aSThomas Huth 671fcf5ef2aSThomas Huth static int kvm_mips_get_fpu_registers(CPUState *cs) 672fcf5ef2aSThomas Huth { 673fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 674fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 675fcf5ef2aSThomas Huth int err, ret = 0; 676fcf5ef2aSThomas Huth unsigned int i; 677fcf5ef2aSThomas Huth 678fcf5ef2aSThomas Huth /* Only get FPU state if we're emulating a CPU with an FPU */ 679fcf5ef2aSThomas Huth if (env->CP0_Config1 & (1 << CP0C1_FP)) { 680fcf5ef2aSThomas Huth /* FPU Control Registers */ 681fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_IR, 682fcf5ef2aSThomas Huth &env->active_fpu.fcr0); 683fcf5ef2aSThomas Huth if (err < 0) { 684fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FCR_IR (%d)\n", __func__, err); 685fcf5ef2aSThomas Huth ret = err; 686fcf5ef2aSThomas Huth } 687fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_CSR, 688fcf5ef2aSThomas Huth &env->active_fpu.fcr31); 689fcf5ef2aSThomas Huth if (err < 0) { 690fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FCR_CSR (%d)\n", __func__, err); 691fcf5ef2aSThomas Huth ret = err; 692fcf5ef2aSThomas Huth } else { 693fcf5ef2aSThomas Huth restore_fp_status(env); 694fcf5ef2aSThomas Huth } 695fcf5ef2aSThomas Huth 696fcf5ef2aSThomas Huth /* 697fcf5ef2aSThomas Huth * FPU register state is a subset of MSA vector state, so don't save FPU 698fcf5ef2aSThomas Huth * registers if we're emulating a CPU with MSA. 699fcf5ef2aSThomas Huth */ 70025a13628SPhilippe Mathieu-Daudé if (!ase_msa_available(env)) { 701fcf5ef2aSThomas Huth /* Floating point registers */ 702fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 703fcf5ef2aSThomas Huth if (env->CP0_Status & (1 << CP0St_FR)) { 704fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i), 705fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].d); 706fcf5ef2aSThomas Huth } else { 707fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i), 708fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); 709fcf5ef2aSThomas Huth } 710fcf5ef2aSThomas Huth if (err < 0) { 711fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__, i, err); 712fcf5ef2aSThomas Huth ret = err; 713fcf5ef2aSThomas Huth } 714fcf5ef2aSThomas Huth } 715fcf5ef2aSThomas Huth } 716fcf5ef2aSThomas Huth } 717fcf5ef2aSThomas Huth 718fcf5ef2aSThomas Huth /* Only get MSA state if we're emulating a CPU with MSA */ 71925a13628SPhilippe Mathieu-Daudé if (ase_msa_available(env)) { 720fcf5ef2aSThomas Huth /* MSA Control Registers */ 721fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR, 722fcf5ef2aSThomas Huth &env->msair); 723fcf5ef2aSThomas Huth if (err < 0) { 724fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get MSA_IR (%d)\n", __func__, err); 725fcf5ef2aSThomas Huth ret = err; 726fcf5ef2aSThomas Huth } 727fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_CSR, 728fcf5ef2aSThomas Huth &env->active_tc.msacsr); 729fcf5ef2aSThomas Huth if (err < 0) { 730fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get MSA_CSR (%d)\n", __func__, err); 731fcf5ef2aSThomas Huth ret = err; 732fcf5ef2aSThomas Huth } else { 733fcf5ef2aSThomas Huth restore_msa_fp_status(env); 734fcf5ef2aSThomas Huth } 735fcf5ef2aSThomas Huth 736fcf5ef2aSThomas Huth /* Vector registers (includes FP registers) */ 737fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 738fcf5ef2aSThomas Huth /* Big endian MSA not supported by QEMU yet anyway */ 739fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_VEC_128(i), 740fcf5ef2aSThomas Huth env->active_fpu.fpr[i].wr.d); 741fcf5ef2aSThomas Huth if (err < 0) { 742fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get VEC%u (%d)\n", __func__, i, err); 743fcf5ef2aSThomas Huth ret = err; 744fcf5ef2aSThomas Huth } 745fcf5ef2aSThomas Huth } 746fcf5ef2aSThomas Huth } 747fcf5ef2aSThomas Huth 748fcf5ef2aSThomas Huth return ret; 749fcf5ef2aSThomas Huth } 750fcf5ef2aSThomas Huth 751fcf5ef2aSThomas Huth 752fcf5ef2aSThomas Huth static int kvm_mips_put_cp0_registers(CPUState *cs, int level) 753fcf5ef2aSThomas Huth { 754fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 755fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 756fcf5ef2aSThomas Huth int err, ret = 0; 757fcf5ef2aSThomas Huth 758fcf5ef2aSThomas Huth (void)level; 759fcf5ef2aSThomas Huth 760fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); 761fcf5ef2aSThomas Huth if (err < 0) { 762fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err); 763fcf5ef2aSThomas Huth ret = err; 764fcf5ef2aSThomas Huth } 7657e0896b0SHuacai Chen err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_RANDOM, &env->CP0_Random); 7667e0896b0SHuacai Chen if (err < 0) { 7677e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_RANDOM (%d)\n", __func__, err); 7687e0896b0SHuacai Chen ret = err; 7697e0896b0SHuacai Chen } 770fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, 771fcf5ef2aSThomas Huth &env->CP0_Context); 772fcf5ef2aSThomas Huth if (err < 0) { 773fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err); 774fcf5ef2aSThomas Huth ret = err; 775fcf5ef2aSThomas Huth } 776fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL, 777fcf5ef2aSThomas Huth &env->active_tc.CP0_UserLocal); 778fcf5ef2aSThomas Huth if (err < 0) { 779fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err); 780fcf5ef2aSThomas Huth ret = err; 781fcf5ef2aSThomas Huth } 782fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK, 783fcf5ef2aSThomas Huth &env->CP0_PageMask); 784fcf5ef2aSThomas Huth if (err < 0) { 785fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err); 786fcf5ef2aSThomas Huth ret = err; 787fcf5ef2aSThomas Huth } 7887e0896b0SHuacai Chen err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEGRAIN, 7897e0896b0SHuacai Chen &env->CP0_PageGrain); 7907e0896b0SHuacai Chen if (err < 0) { 7917e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_PAGEGRAIN (%d)\n", __func__, err); 7927e0896b0SHuacai Chen ret = err; 7937e0896b0SHuacai Chen } 7947e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWBASE, 7957e0896b0SHuacai Chen &env->CP0_PWBase); 7967e0896b0SHuacai Chen if (err < 0) { 7977e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_PWBASE (%d)\n", __func__, err); 7987e0896b0SHuacai Chen ret = err; 7997e0896b0SHuacai Chen } 8007e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWFIELD, 8017e0896b0SHuacai Chen &env->CP0_PWField); 8027e0896b0SHuacai Chen if (err < 0) { 8037e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_PWField (%d)\n", __func__, err); 8047e0896b0SHuacai Chen ret = err; 8057e0896b0SHuacai Chen } 8067e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWSIZE, 8077e0896b0SHuacai Chen &env->CP0_PWSize); 8087e0896b0SHuacai Chen if (err < 0) { 8097e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_PWSIZE (%d)\n", __func__, err); 8107e0896b0SHuacai Chen ret = err; 8117e0896b0SHuacai Chen } 812fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); 813fcf5ef2aSThomas Huth if (err < 0) { 814fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err); 815fcf5ef2aSThomas Huth ret = err; 816fcf5ef2aSThomas Huth } 8177e0896b0SHuacai Chen err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PWCTL, &env->CP0_PWCtl); 8187e0896b0SHuacai Chen if (err < 0) { 8197e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_PWCTL (%d)\n", __func__, err); 8207e0896b0SHuacai Chen ret = err; 8217e0896b0SHuacai Chen } 822fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); 823fcf5ef2aSThomas Huth if (err < 0) { 824fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err); 825fcf5ef2aSThomas Huth ret = err; 826fcf5ef2aSThomas Huth } 827fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR, 828fcf5ef2aSThomas Huth &env->CP0_BadVAddr); 829fcf5ef2aSThomas Huth if (err < 0) { 830fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err); 831fcf5ef2aSThomas Huth ret = err; 832fcf5ef2aSThomas Huth } 833fcf5ef2aSThomas Huth 834fcf5ef2aSThomas Huth /* If VM clock stopped then state will be restored when it is restarted */ 835fcf5ef2aSThomas Huth if (runstate_is_running()) { 836fcf5ef2aSThomas Huth err = kvm_mips_restore_count(cs); 837fcf5ef2aSThomas Huth if (err < 0) { 838fcf5ef2aSThomas Huth ret = err; 839fcf5ef2aSThomas Huth } 840fcf5ef2aSThomas Huth } 841fcf5ef2aSThomas Huth 842fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI, 843fcf5ef2aSThomas Huth &env->CP0_EntryHi); 844fcf5ef2aSThomas Huth if (err < 0) { 845fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err); 846fcf5ef2aSThomas Huth ret = err; 847fcf5ef2aSThomas Huth } 848fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE, 849fcf5ef2aSThomas Huth &env->CP0_Compare); 850fcf5ef2aSThomas Huth if (err < 0) { 851fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err); 852fcf5ef2aSThomas Huth ret = err; 853fcf5ef2aSThomas Huth } 854fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status); 855fcf5ef2aSThomas Huth if (err < 0) { 856fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err); 857fcf5ef2aSThomas Huth ret = err; 858fcf5ef2aSThomas Huth } 859fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC); 860fcf5ef2aSThomas Huth if (err < 0) { 861fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err); 862fcf5ef2aSThomas Huth ret = err; 863fcf5ef2aSThomas Huth } 864fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); 865fcf5ef2aSThomas Huth if (err < 0) { 866fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err); 867fcf5ef2aSThomas Huth ret = err; 868fcf5ef2aSThomas Huth } 8697e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EBASE, &env->CP0_EBase); 8707e0896b0SHuacai Chen if (err < 0) { 8717e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_EBASE (%d)\n", __func__, err); 8727e0896b0SHuacai Chen ret = err; 8737e0896b0SHuacai Chen } 874fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, 875fcf5ef2aSThomas Huth &env->CP0_Config0, 876fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG_MASK); 877fcf5ef2aSThomas Huth if (err < 0) { 878fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG (%d)\n", __func__, err); 879fcf5ef2aSThomas Huth ret = err; 880fcf5ef2aSThomas Huth } 881fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, 882fcf5ef2aSThomas Huth &env->CP0_Config1, 883fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG1_MASK); 884fcf5ef2aSThomas Huth if (err < 0) { 885fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG1 (%d)\n", __func__, err); 886fcf5ef2aSThomas Huth ret = err; 887fcf5ef2aSThomas Huth } 888fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2, 889fcf5ef2aSThomas Huth &env->CP0_Config2, 890fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG2_MASK); 891fcf5ef2aSThomas Huth if (err < 0) { 892fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG2 (%d)\n", __func__, err); 893fcf5ef2aSThomas Huth ret = err; 894fcf5ef2aSThomas Huth } 895fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3, 896fcf5ef2aSThomas Huth &env->CP0_Config3, 897fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG3_MASK); 898fcf5ef2aSThomas Huth if (err < 0) { 899fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG3 (%d)\n", __func__, err); 900fcf5ef2aSThomas Huth ret = err; 901fcf5ef2aSThomas Huth } 902fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4, 903fcf5ef2aSThomas Huth &env->CP0_Config4, 904fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG4_MASK); 905fcf5ef2aSThomas Huth if (err < 0) { 906fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG4 (%d)\n", __func__, err); 907fcf5ef2aSThomas Huth ret = err; 908fcf5ef2aSThomas Huth } 909fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, 910fcf5ef2aSThomas Huth &env->CP0_Config5, 911fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG5_MASK); 912fcf5ef2aSThomas Huth if (err < 0) { 913fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG5 (%d)\n", __func__, err); 914fcf5ef2aSThomas Huth ret = err; 915fcf5ef2aSThomas Huth } 9167e0896b0SHuacai Chen err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG6, 9177e0896b0SHuacai Chen &env->CP0_Config6, 9187e0896b0SHuacai Chen KVM_REG_MIPS_CP0_CONFIG6_MASK); 9197e0896b0SHuacai Chen if (err < 0) { 9207e0896b0SHuacai Chen DPRINTF("%s: Failed to change CP0_CONFIG6 (%d)\n", __func__, err); 9217e0896b0SHuacai Chen ret = err; 9227e0896b0SHuacai Chen } 9237e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_XCONTEXT, 9247e0896b0SHuacai Chen &env->CP0_XContext); 9257e0896b0SHuacai Chen if (err < 0) { 9267e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_XCONTEXT (%d)\n", __func__, err); 9277e0896b0SHuacai Chen ret = err; 9287e0896b0SHuacai Chen } 929fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, 930fcf5ef2aSThomas Huth &env->CP0_ErrorEPC); 931fcf5ef2aSThomas Huth if (err < 0) { 932fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err); 933fcf5ef2aSThomas Huth ret = err; 934fcf5ef2aSThomas Huth } 9357e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH1, 9367e0896b0SHuacai Chen &env->CP0_KScratch[0]); 9377e0896b0SHuacai Chen if (err < 0) { 9387e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH1 (%d)\n", __func__, err); 9397e0896b0SHuacai Chen ret = err; 9407e0896b0SHuacai Chen } 9417e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH2, 9427e0896b0SHuacai Chen &env->CP0_KScratch[1]); 9437e0896b0SHuacai Chen if (err < 0) { 9447e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH2 (%d)\n", __func__, err); 9457e0896b0SHuacai Chen ret = err; 9467e0896b0SHuacai Chen } 9477e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH3, 9487e0896b0SHuacai Chen &env->CP0_KScratch[2]); 9497e0896b0SHuacai Chen if (err < 0) { 9507e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH3 (%d)\n", __func__, err); 9517e0896b0SHuacai Chen ret = err; 9527e0896b0SHuacai Chen } 9537e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH4, 9547e0896b0SHuacai Chen &env->CP0_KScratch[3]); 9557e0896b0SHuacai Chen if (err < 0) { 9567e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH4 (%d)\n", __func__, err); 9577e0896b0SHuacai Chen ret = err; 9587e0896b0SHuacai Chen } 9597e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH5, 9607e0896b0SHuacai Chen &env->CP0_KScratch[4]); 9617e0896b0SHuacai Chen if (err < 0) { 9627e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH5 (%d)\n", __func__, err); 9637e0896b0SHuacai Chen ret = err; 9647e0896b0SHuacai Chen } 9657e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH6, 9667e0896b0SHuacai Chen &env->CP0_KScratch[5]); 9677e0896b0SHuacai Chen if (err < 0) { 9687e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH6 (%d)\n", __func__, err); 9697e0896b0SHuacai Chen ret = err; 9707e0896b0SHuacai Chen } 971fcf5ef2aSThomas Huth 972fcf5ef2aSThomas Huth return ret; 973fcf5ef2aSThomas Huth } 974fcf5ef2aSThomas Huth 975fcf5ef2aSThomas Huth static int kvm_mips_get_cp0_registers(CPUState *cs) 976fcf5ef2aSThomas Huth { 977fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 978fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 979fcf5ef2aSThomas Huth int err, ret = 0; 980fcf5ef2aSThomas Huth 981fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); 982fcf5ef2aSThomas Huth if (err < 0) { 983fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err); 984fcf5ef2aSThomas Huth ret = err; 985fcf5ef2aSThomas Huth } 9867e0896b0SHuacai Chen err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_RANDOM, &env->CP0_Random); 9877e0896b0SHuacai Chen if (err < 0) { 9887e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_RANDOM (%d)\n", __func__, err); 9897e0896b0SHuacai Chen ret = err; 9907e0896b0SHuacai Chen } 991fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, 992fcf5ef2aSThomas Huth &env->CP0_Context); 993fcf5ef2aSThomas Huth if (err < 0) { 994fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err); 995fcf5ef2aSThomas Huth ret = err; 996fcf5ef2aSThomas Huth } 997fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL, 998fcf5ef2aSThomas Huth &env->active_tc.CP0_UserLocal); 999fcf5ef2aSThomas Huth if (err < 0) { 1000fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err); 1001fcf5ef2aSThomas Huth ret = err; 1002fcf5ef2aSThomas Huth } 1003fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK, 1004fcf5ef2aSThomas Huth &env->CP0_PageMask); 1005fcf5ef2aSThomas Huth if (err < 0) { 1006fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err); 1007fcf5ef2aSThomas Huth ret = err; 1008fcf5ef2aSThomas Huth } 10097e0896b0SHuacai Chen err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEGRAIN, 10107e0896b0SHuacai Chen &env->CP0_PageGrain); 10117e0896b0SHuacai Chen if (err < 0) { 10127e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_PAGEGRAIN (%d)\n", __func__, err); 10137e0896b0SHuacai Chen ret = err; 10147e0896b0SHuacai Chen } 10157e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWBASE, 10167e0896b0SHuacai Chen &env->CP0_PWBase); 10177e0896b0SHuacai Chen if (err < 0) { 10187e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_PWBASE (%d)\n", __func__, err); 10197e0896b0SHuacai Chen ret = err; 10207e0896b0SHuacai Chen } 10217e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWFIELD, 10227e0896b0SHuacai Chen &env->CP0_PWField); 10237e0896b0SHuacai Chen if (err < 0) { 10247e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_PWFIELD (%d)\n", __func__, err); 10257e0896b0SHuacai Chen ret = err; 10267e0896b0SHuacai Chen } 10277e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWSIZE, 10287e0896b0SHuacai Chen &env->CP0_PWSize); 10297e0896b0SHuacai Chen if (err < 0) { 10307e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_PWSIZE (%d)\n", __func__, err); 10317e0896b0SHuacai Chen ret = err; 10327e0896b0SHuacai Chen } 1033fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); 1034fcf5ef2aSThomas Huth if (err < 0) { 1035fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err); 1036fcf5ef2aSThomas Huth ret = err; 1037fcf5ef2aSThomas Huth } 10387e0896b0SHuacai Chen err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PWCTL, &env->CP0_PWCtl); 10397e0896b0SHuacai Chen if (err < 0) { 10407e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_PWCtl (%d)\n", __func__, err); 10417e0896b0SHuacai Chen ret = err; 10427e0896b0SHuacai Chen } 1043fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); 1044fcf5ef2aSThomas Huth if (err < 0) { 1045fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err); 1046fcf5ef2aSThomas Huth ret = err; 1047fcf5ef2aSThomas Huth } 1048fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR, 1049fcf5ef2aSThomas Huth &env->CP0_BadVAddr); 1050fcf5ef2aSThomas Huth if (err < 0) { 1051fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err); 1052fcf5ef2aSThomas Huth ret = err; 1053fcf5ef2aSThomas Huth } 1054fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI, 1055fcf5ef2aSThomas Huth &env->CP0_EntryHi); 1056fcf5ef2aSThomas Huth if (err < 0) { 1057fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err); 1058fcf5ef2aSThomas Huth ret = err; 1059fcf5ef2aSThomas Huth } 1060fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE, 1061fcf5ef2aSThomas Huth &env->CP0_Compare); 1062fcf5ef2aSThomas Huth if (err < 0) { 1063fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err); 1064fcf5ef2aSThomas Huth ret = err; 1065fcf5ef2aSThomas Huth } 1066fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status); 1067fcf5ef2aSThomas Huth if (err < 0) { 1068fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err); 1069fcf5ef2aSThomas Huth ret = err; 1070fcf5ef2aSThomas Huth } 1071fcf5ef2aSThomas Huth 1072fcf5ef2aSThomas Huth /* If VM clock stopped then state was already saved when it was stopped */ 1073fcf5ef2aSThomas Huth if (runstate_is_running()) { 1074fcf5ef2aSThomas Huth err = kvm_mips_save_count(cs); 1075fcf5ef2aSThomas Huth if (err < 0) { 1076fcf5ef2aSThomas Huth ret = err; 1077fcf5ef2aSThomas Huth } 1078fcf5ef2aSThomas Huth } 1079fcf5ef2aSThomas Huth 1080fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC); 1081fcf5ef2aSThomas Huth if (err < 0) { 1082fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err); 1083fcf5ef2aSThomas Huth ret = err; 1084fcf5ef2aSThomas Huth } 1085fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); 1086fcf5ef2aSThomas Huth if (err < 0) { 1087fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err); 1088fcf5ef2aSThomas Huth ret = err; 1089fcf5ef2aSThomas Huth } 10907e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EBASE, &env->CP0_EBase); 10917e0896b0SHuacai Chen if (err < 0) { 10927e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_EBASE (%d)\n", __func__, err); 10937e0896b0SHuacai Chen ret = err; 10947e0896b0SHuacai Chen } 1095fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, &env->CP0_Config0); 1096fcf5ef2aSThomas Huth if (err < 0) { 1097fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG (%d)\n", __func__, err); 1098fcf5ef2aSThomas Huth ret = err; 1099fcf5ef2aSThomas Huth } 1100fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, &env->CP0_Config1); 1101fcf5ef2aSThomas Huth if (err < 0) { 1102fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG1 (%d)\n", __func__, err); 1103fcf5ef2aSThomas Huth ret = err; 1104fcf5ef2aSThomas Huth } 1105fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2, &env->CP0_Config2); 1106fcf5ef2aSThomas Huth if (err < 0) { 1107fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG2 (%d)\n", __func__, err); 1108fcf5ef2aSThomas Huth ret = err; 1109fcf5ef2aSThomas Huth } 1110fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3, &env->CP0_Config3); 1111fcf5ef2aSThomas Huth if (err < 0) { 1112fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG3 (%d)\n", __func__, err); 1113fcf5ef2aSThomas Huth ret = err; 1114fcf5ef2aSThomas Huth } 1115fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4, &env->CP0_Config4); 1116fcf5ef2aSThomas Huth if (err < 0) { 1117fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG4 (%d)\n", __func__, err); 1118fcf5ef2aSThomas Huth ret = err; 1119fcf5ef2aSThomas Huth } 1120fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, &env->CP0_Config5); 1121fcf5ef2aSThomas Huth if (err < 0) { 1122fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG5 (%d)\n", __func__, err); 1123fcf5ef2aSThomas Huth ret = err; 1124fcf5ef2aSThomas Huth } 11257e0896b0SHuacai Chen err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG6, &env->CP0_Config6); 11267e0896b0SHuacai Chen if (err < 0) { 11277e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_CONFIG6 (%d)\n", __func__, err); 11287e0896b0SHuacai Chen ret = err; 11297e0896b0SHuacai Chen } 11307e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_XCONTEXT, 11317e0896b0SHuacai Chen &env->CP0_XContext); 11327e0896b0SHuacai Chen if (err < 0) { 11337e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_XCONTEXT (%d)\n", __func__, err); 11347e0896b0SHuacai Chen ret = err; 11357e0896b0SHuacai Chen } 1136fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, 1137fcf5ef2aSThomas Huth &env->CP0_ErrorEPC); 1138fcf5ef2aSThomas Huth if (err < 0) { 1139fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err); 1140fcf5ef2aSThomas Huth ret = err; 1141fcf5ef2aSThomas Huth } 11427e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH1, 11437e0896b0SHuacai Chen &env->CP0_KScratch[0]); 11447e0896b0SHuacai Chen if (err < 0) { 11457e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH1 (%d)\n", __func__, err); 11467e0896b0SHuacai Chen ret = err; 11477e0896b0SHuacai Chen } 11487e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH2, 11497e0896b0SHuacai Chen &env->CP0_KScratch[1]); 11507e0896b0SHuacai Chen if (err < 0) { 11517e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH2 (%d)\n", __func__, err); 11527e0896b0SHuacai Chen ret = err; 11537e0896b0SHuacai Chen } 11547e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH3, 11557e0896b0SHuacai Chen &env->CP0_KScratch[2]); 11567e0896b0SHuacai Chen if (err < 0) { 11577e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH3 (%d)\n", __func__, err); 11587e0896b0SHuacai Chen ret = err; 11597e0896b0SHuacai Chen } 11607e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH4, 11617e0896b0SHuacai Chen &env->CP0_KScratch[3]); 11627e0896b0SHuacai Chen if (err < 0) { 11637e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH4 (%d)\n", __func__, err); 11647e0896b0SHuacai Chen ret = err; 11657e0896b0SHuacai Chen } 11667e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH5, 11677e0896b0SHuacai Chen &env->CP0_KScratch[4]); 11687e0896b0SHuacai Chen if (err < 0) { 11697e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH5 (%d)\n", __func__, err); 11707e0896b0SHuacai Chen ret = err; 11717e0896b0SHuacai Chen } 11727e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH6, 11737e0896b0SHuacai Chen &env->CP0_KScratch[5]); 11747e0896b0SHuacai Chen if (err < 0) { 11757e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH6 (%d)\n", __func__, err); 11767e0896b0SHuacai Chen ret = err; 11777e0896b0SHuacai Chen } 1178fcf5ef2aSThomas Huth 1179fcf5ef2aSThomas Huth return ret; 1180fcf5ef2aSThomas Huth } 1181fcf5ef2aSThomas Huth 1182fcf5ef2aSThomas Huth int kvm_arch_put_registers(CPUState *cs, int level) 1183fcf5ef2aSThomas Huth { 1184fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 1185fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 1186fcf5ef2aSThomas Huth struct kvm_regs regs; 1187fcf5ef2aSThomas Huth int ret; 1188fcf5ef2aSThomas Huth int i; 1189fcf5ef2aSThomas Huth 1190fcf5ef2aSThomas Huth /* Set the registers based on QEMU's view of things */ 1191fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 1192fcf5ef2aSThomas Huth regs.gpr[i] = (int64_t)(target_long)env->active_tc.gpr[i]; 1193fcf5ef2aSThomas Huth } 1194fcf5ef2aSThomas Huth 1195fcf5ef2aSThomas Huth regs.hi = (int64_t)(target_long)env->active_tc.HI[0]; 1196fcf5ef2aSThomas Huth regs.lo = (int64_t)(target_long)env->active_tc.LO[0]; 1197fcf5ef2aSThomas Huth regs.pc = (int64_t)(target_long)env->active_tc.PC; 1198fcf5ef2aSThomas Huth 1199fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); 1200fcf5ef2aSThomas Huth 1201fcf5ef2aSThomas Huth if (ret < 0) { 1202fcf5ef2aSThomas Huth return ret; 1203fcf5ef2aSThomas Huth } 1204fcf5ef2aSThomas Huth 1205fcf5ef2aSThomas Huth ret = kvm_mips_put_cp0_registers(cs, level); 1206fcf5ef2aSThomas Huth if (ret < 0) { 1207fcf5ef2aSThomas Huth return ret; 1208fcf5ef2aSThomas Huth } 1209fcf5ef2aSThomas Huth 1210fcf5ef2aSThomas Huth ret = kvm_mips_put_fpu_registers(cs, level); 1211fcf5ef2aSThomas Huth if (ret < 0) { 1212fcf5ef2aSThomas Huth return ret; 1213fcf5ef2aSThomas Huth } 1214fcf5ef2aSThomas Huth 1215fcf5ef2aSThomas Huth return ret; 1216fcf5ef2aSThomas Huth } 1217fcf5ef2aSThomas Huth 1218fcf5ef2aSThomas Huth int kvm_arch_get_registers(CPUState *cs) 1219fcf5ef2aSThomas Huth { 1220fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 1221fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 1222fcf5ef2aSThomas Huth int ret = 0; 1223fcf5ef2aSThomas Huth struct kvm_regs regs; 1224fcf5ef2aSThomas Huth int i; 1225fcf5ef2aSThomas Huth 1226fcf5ef2aSThomas Huth /* Get the current register set as KVM seems it */ 1227fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 1228fcf5ef2aSThomas Huth 1229fcf5ef2aSThomas Huth if (ret < 0) { 1230fcf5ef2aSThomas Huth return ret; 1231fcf5ef2aSThomas Huth } 1232fcf5ef2aSThomas Huth 1233fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 1234fcf5ef2aSThomas Huth env->active_tc.gpr[i] = regs.gpr[i]; 1235fcf5ef2aSThomas Huth } 1236fcf5ef2aSThomas Huth 1237fcf5ef2aSThomas Huth env->active_tc.HI[0] = regs.hi; 1238fcf5ef2aSThomas Huth env->active_tc.LO[0] = regs.lo; 1239fcf5ef2aSThomas Huth env->active_tc.PC = regs.pc; 1240fcf5ef2aSThomas Huth 1241fcf5ef2aSThomas Huth kvm_mips_get_cp0_registers(cs); 1242fcf5ef2aSThomas Huth kvm_mips_get_fpu_registers(cs); 1243fcf5ef2aSThomas Huth 1244fcf5ef2aSThomas Huth return ret; 1245fcf5ef2aSThomas Huth } 1246fcf5ef2aSThomas Huth 1247fcf5ef2aSThomas Huth int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1248fcf5ef2aSThomas Huth uint64_t address, uint32_t data, PCIDevice *dev) 1249fcf5ef2aSThomas Huth { 1250fcf5ef2aSThomas Huth return 0; 1251fcf5ef2aSThomas Huth } 1252fcf5ef2aSThomas Huth 1253fcf5ef2aSThomas Huth int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1254fcf5ef2aSThomas Huth int vector, PCIDevice *dev) 1255fcf5ef2aSThomas Huth { 1256fcf5ef2aSThomas Huth return 0; 1257fcf5ef2aSThomas Huth } 1258fcf5ef2aSThomas Huth 1259fcf5ef2aSThomas Huth int kvm_arch_release_virq_post(int virq) 1260fcf5ef2aSThomas Huth { 1261fcf5ef2aSThomas Huth return 0; 1262fcf5ef2aSThomas Huth } 1263fcf5ef2aSThomas Huth 1264fcf5ef2aSThomas Huth int kvm_arch_msi_data_to_gsi(uint32_t data) 1265fcf5ef2aSThomas Huth { 1266fcf5ef2aSThomas Huth abort(); 1267fcf5ef2aSThomas Huth } 1268719d109bSHuacai Chen 1269719d109bSHuacai Chen int mips_kvm_type(MachineState *machine, const char *vm_type) 1270719d109bSHuacai Chen { 1271*a8448735SPaolo Bonzini #if defined(KVM_CAP_MIPS_VZ) 1272719d109bSHuacai Chen int r; 1273719d109bSHuacai Chen KVMState *s = KVM_STATE(machine->accelerator); 1274719d109bSHuacai Chen 1275719d109bSHuacai Chen r = kvm_check_extension(s, KVM_CAP_MIPS_VZ); 1276719d109bSHuacai Chen if (r > 0) { 1277719d109bSHuacai Chen return KVM_VM_MIPS_VZ; 1278719d109bSHuacai Chen } 1279719d109bSHuacai Chen #endif 1280719d109bSHuacai Chen 1281719d109bSHuacai Chen return -1; 1282719d109bSHuacai Chen } 128392a5199bSTom Lendacky 128492a5199bSTom Lendacky bool kvm_arch_cpu_check_are_resettable(void) 128592a5199bSTom Lendacky { 128692a5199bSTom Lendacky return true; 128792a5199bSTom Lendacky } 12883dba0a33SPaolo Bonzini 12893dba0a33SPaolo Bonzini void kvm_arch_accel_class_init(ObjectClass *oc) 12903dba0a33SPaolo Bonzini { 12913dba0a33SPaolo Bonzini } 1292