1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * This file is subject to the terms and conditions of the GNU General Public 3fcf5ef2aSThomas Huth * License. See the file "COPYING" in the main directory of this archive 4fcf5ef2aSThomas Huth * for more details. 5fcf5ef2aSThomas Huth * 6fcf5ef2aSThomas Huth * KVM/MIPS: MIPS specific KVM APIs 7fcf5ef2aSThomas Huth * 8fcf5ef2aSThomas Huth * Copyright (C) 2012-2014 Imagination Technologies Ltd. 9fcf5ef2aSThomas Huth * Authors: Sanjay Lal <sanjayl@kymasys.com> 10fcf5ef2aSThomas Huth */ 11fcf5ef2aSThomas Huth 12fcf5ef2aSThomas Huth #include "qemu/osdep.h" 13fcf5ef2aSThomas Huth #include <sys/ioctl.h> 14fcf5ef2aSThomas Huth 15fcf5ef2aSThomas Huth #include <linux/kvm.h> 16fcf5ef2aSThomas Huth 17fcf5ef2aSThomas Huth #include "qemu-common.h" 18fcf5ef2aSThomas Huth #include "cpu.h" 1926aa3d9aSPhilippe Mathieu-Daudé #include "internal.h" 20fcf5ef2aSThomas Huth #include "qemu/error-report.h" 21db725815SMarkus Armbruster #include "qemu/main-loop.h" 22fcf5ef2aSThomas Huth #include "qemu/timer.h" 23fcf5ef2aSThomas Huth #include "sysemu/kvm.h" 2454d31236SMarkus Armbruster #include "sysemu/runstate.h" 25fcf5ef2aSThomas Huth #include "sysemu/cpus.h" 26fcf5ef2aSThomas Huth #include "kvm_mips.h" 27fcf5ef2aSThomas Huth #include "exec/memattrs.h" 28fcf5ef2aSThomas Huth 29fcf5ef2aSThomas Huth #define DEBUG_KVM 0 30fcf5ef2aSThomas Huth 31fcf5ef2aSThomas Huth #define DPRINTF(fmt, ...) \ 32fcf5ef2aSThomas Huth do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0) 33fcf5ef2aSThomas Huth 34fcf5ef2aSThomas Huth static int kvm_mips_fpu_cap; 35fcf5ef2aSThomas Huth static int kvm_mips_msa_cap; 36fcf5ef2aSThomas Huth 37fcf5ef2aSThomas Huth const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 38fcf5ef2aSThomas Huth KVM_CAP_LAST_INFO 39fcf5ef2aSThomas Huth }; 40fcf5ef2aSThomas Huth 41fcf5ef2aSThomas Huth static void kvm_mips_update_state(void *opaque, int running, RunState state); 42fcf5ef2aSThomas Huth 43fcf5ef2aSThomas Huth unsigned long kvm_arch_vcpu_id(CPUState *cs) 44fcf5ef2aSThomas Huth { 45fcf5ef2aSThomas Huth return cs->cpu_index; 46fcf5ef2aSThomas Huth } 47fcf5ef2aSThomas Huth 48fcf5ef2aSThomas Huth int kvm_arch_init(MachineState *ms, KVMState *s) 49fcf5ef2aSThomas Huth { 50fcf5ef2aSThomas Huth /* MIPS has 128 signals */ 51fcf5ef2aSThomas Huth kvm_set_sigmask_len(s, 16); 52fcf5ef2aSThomas Huth 53fcf5ef2aSThomas Huth kvm_mips_fpu_cap = kvm_check_extension(s, KVM_CAP_MIPS_FPU); 54fcf5ef2aSThomas Huth kvm_mips_msa_cap = kvm_check_extension(s, KVM_CAP_MIPS_MSA); 55fcf5ef2aSThomas Huth 56fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 57fcf5ef2aSThomas Huth return 0; 58fcf5ef2aSThomas Huth } 59fcf5ef2aSThomas Huth 604376c40dSPaolo Bonzini int kvm_arch_irqchip_create(KVMState *s) 61d525ffabSPaolo Bonzini { 62d525ffabSPaolo Bonzini return 0; 63d525ffabSPaolo Bonzini } 64d525ffabSPaolo Bonzini 65fcf5ef2aSThomas Huth int kvm_arch_init_vcpu(CPUState *cs) 66fcf5ef2aSThomas Huth { 67fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 68fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 69fcf5ef2aSThomas Huth int ret = 0; 70fcf5ef2aSThomas Huth 71fcf5ef2aSThomas Huth qemu_add_vm_change_state_handler(kvm_mips_update_state, cs); 72fcf5ef2aSThomas Huth 73fcf5ef2aSThomas Huth if (kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) { 74fcf5ef2aSThomas Huth ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_FPU, 0, 0); 75fcf5ef2aSThomas Huth if (ret < 0) { 76fcf5ef2aSThomas Huth /* mark unsupported so it gets disabled on reset */ 77fcf5ef2aSThomas Huth kvm_mips_fpu_cap = 0; 78fcf5ef2aSThomas Huth ret = 0; 79fcf5ef2aSThomas Huth } 80fcf5ef2aSThomas Huth } 81fcf5ef2aSThomas Huth 82fcf5ef2aSThomas Huth if (kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) { 83fcf5ef2aSThomas Huth ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0); 84fcf5ef2aSThomas Huth if (ret < 0) { 85fcf5ef2aSThomas Huth /* mark unsupported so it gets disabled on reset */ 86fcf5ef2aSThomas Huth kvm_mips_msa_cap = 0; 87fcf5ef2aSThomas Huth ret = 0; 88fcf5ef2aSThomas Huth } 89fcf5ef2aSThomas Huth } 90fcf5ef2aSThomas Huth 91fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 92fcf5ef2aSThomas Huth return ret; 93fcf5ef2aSThomas Huth } 94fcf5ef2aSThomas Huth 95b1115c99SLiran Alon int kvm_arch_destroy_vcpu(CPUState *cs) 96b1115c99SLiran Alon { 97b1115c99SLiran Alon return 0; 98b1115c99SLiran Alon } 99b1115c99SLiran Alon 100fcf5ef2aSThomas Huth void kvm_mips_reset_vcpu(MIPSCPU *cpu) 101fcf5ef2aSThomas Huth { 102fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 103fcf5ef2aSThomas Huth 104fcf5ef2aSThomas Huth if (!kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) { 1052ab4b135SAlistair Francis warn_report("KVM does not support FPU, disabling"); 106fcf5ef2aSThomas Huth env->CP0_Config1 &= ~(1 << CP0C1_FP); 107fcf5ef2aSThomas Huth } 108fcf5ef2aSThomas Huth if (!kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) { 1092ab4b135SAlistair Francis warn_report("KVM does not support MSA, disabling"); 110fcf5ef2aSThomas Huth env->CP0_Config3 &= ~(1 << CP0C3_MSAP); 111fcf5ef2aSThomas Huth } 112fcf5ef2aSThomas Huth 113fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 114fcf5ef2aSThomas Huth } 115fcf5ef2aSThomas Huth 116fcf5ef2aSThomas Huth int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 117fcf5ef2aSThomas Huth { 118fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 119fcf5ef2aSThomas Huth return 0; 120fcf5ef2aSThomas Huth } 121fcf5ef2aSThomas Huth 122fcf5ef2aSThomas Huth int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 123fcf5ef2aSThomas Huth { 124fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 125fcf5ef2aSThomas Huth return 0; 126fcf5ef2aSThomas Huth } 127fcf5ef2aSThomas Huth 128fcf5ef2aSThomas Huth static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu) 129fcf5ef2aSThomas Huth { 130fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 131fcf5ef2aSThomas Huth 132fcf5ef2aSThomas Huth return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP)); 133fcf5ef2aSThomas Huth } 134fcf5ef2aSThomas Huth 135fcf5ef2aSThomas Huth 136fcf5ef2aSThomas Huth void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 137fcf5ef2aSThomas Huth { 138fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 139fcf5ef2aSThomas Huth int r; 140fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 141fcf5ef2aSThomas Huth 142fcf5ef2aSThomas Huth qemu_mutex_lock_iothread(); 143fcf5ef2aSThomas Huth 144fcf5ef2aSThomas Huth if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 145fcf5ef2aSThomas Huth cpu_mips_io_interrupts_pending(cpu)) { 146fcf5ef2aSThomas Huth intr.cpu = -1; 147fcf5ef2aSThomas Huth intr.irq = 2; 148fcf5ef2aSThomas Huth r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 149fcf5ef2aSThomas Huth if (r < 0) { 150fcf5ef2aSThomas Huth error_report("%s: cpu %d: failed to inject IRQ %x", 151fcf5ef2aSThomas Huth __func__, cs->cpu_index, intr.irq); 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth } 154fcf5ef2aSThomas Huth 155fcf5ef2aSThomas Huth qemu_mutex_unlock_iothread(); 156fcf5ef2aSThomas Huth } 157fcf5ef2aSThomas Huth 158fcf5ef2aSThomas Huth MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 159fcf5ef2aSThomas Huth { 160fcf5ef2aSThomas Huth return MEMTXATTRS_UNSPECIFIED; 161fcf5ef2aSThomas Huth } 162fcf5ef2aSThomas Huth 163fcf5ef2aSThomas Huth int kvm_arch_process_async_events(CPUState *cs) 164fcf5ef2aSThomas Huth { 165fcf5ef2aSThomas Huth return cs->halted; 166fcf5ef2aSThomas Huth } 167fcf5ef2aSThomas Huth 168fcf5ef2aSThomas Huth int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 169fcf5ef2aSThomas Huth { 170fcf5ef2aSThomas Huth int ret; 171fcf5ef2aSThomas Huth 172fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 173fcf5ef2aSThomas Huth switch (run->exit_reason) { 174fcf5ef2aSThomas Huth default: 175fcf5ef2aSThomas Huth error_report("%s: unknown exit reason %d", 176fcf5ef2aSThomas Huth __func__, run->exit_reason); 177fcf5ef2aSThomas Huth ret = -1; 178fcf5ef2aSThomas Huth break; 179fcf5ef2aSThomas Huth } 180fcf5ef2aSThomas Huth 181fcf5ef2aSThomas Huth return ret; 182fcf5ef2aSThomas Huth } 183fcf5ef2aSThomas Huth 184fcf5ef2aSThomas Huth bool kvm_arch_stop_on_emulation_error(CPUState *cs) 185fcf5ef2aSThomas Huth { 186fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 187fcf5ef2aSThomas Huth return true; 188fcf5ef2aSThomas Huth } 189fcf5ef2aSThomas Huth 190fcf5ef2aSThomas Huth void kvm_arch_init_irq_routing(KVMState *s) 191fcf5ef2aSThomas Huth { 192fcf5ef2aSThomas Huth } 193fcf5ef2aSThomas Huth 194fcf5ef2aSThomas Huth int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level) 195fcf5ef2aSThomas Huth { 196fcf5ef2aSThomas Huth CPUState *cs = CPU(cpu); 197fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 198fcf5ef2aSThomas Huth 199fcf5ef2aSThomas Huth if (!kvm_enabled()) { 200fcf5ef2aSThomas Huth return 0; 201fcf5ef2aSThomas Huth } 202fcf5ef2aSThomas Huth 203fcf5ef2aSThomas Huth intr.cpu = -1; 204fcf5ef2aSThomas Huth 205fcf5ef2aSThomas Huth if (level) { 206fcf5ef2aSThomas Huth intr.irq = irq; 207fcf5ef2aSThomas Huth } else { 208fcf5ef2aSThomas Huth intr.irq = -irq; 209fcf5ef2aSThomas Huth } 210fcf5ef2aSThomas Huth 211fcf5ef2aSThomas Huth kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 212fcf5ef2aSThomas Huth 213fcf5ef2aSThomas Huth return 0; 214fcf5ef2aSThomas Huth } 215fcf5ef2aSThomas Huth 216fcf5ef2aSThomas Huth int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) 217fcf5ef2aSThomas Huth { 218fcf5ef2aSThomas Huth CPUState *cs = current_cpu; 219fcf5ef2aSThomas Huth CPUState *dest_cs = CPU(cpu); 220fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 221fcf5ef2aSThomas Huth 222fcf5ef2aSThomas Huth if (!kvm_enabled()) { 223fcf5ef2aSThomas Huth return 0; 224fcf5ef2aSThomas Huth } 225fcf5ef2aSThomas Huth 226fcf5ef2aSThomas Huth intr.cpu = dest_cs->cpu_index; 227fcf5ef2aSThomas Huth 228fcf5ef2aSThomas Huth if (level) { 229fcf5ef2aSThomas Huth intr.irq = irq; 230fcf5ef2aSThomas Huth } else { 231fcf5ef2aSThomas Huth intr.irq = -irq; 232fcf5ef2aSThomas Huth } 233fcf5ef2aSThomas Huth 234fcf5ef2aSThomas Huth DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq); 235fcf5ef2aSThomas Huth 236fcf5ef2aSThomas Huth kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 237fcf5ef2aSThomas Huth 238fcf5ef2aSThomas Huth return 0; 239fcf5ef2aSThomas Huth } 240fcf5ef2aSThomas Huth 241fcf5ef2aSThomas Huth #define MIPS_CP0_32(_R, _S) \ 242fcf5ef2aSThomas Huth (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S))) 243fcf5ef2aSThomas Huth 244fcf5ef2aSThomas Huth #define MIPS_CP0_64(_R, _S) \ 245fcf5ef2aSThomas Huth (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) 246fcf5ef2aSThomas Huth 247fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) 248*7e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_RANDOM MIPS_CP0_32(1, 0) 249fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) 250fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) 251fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) 252*7e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) 253*7e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5) 254*7e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6) 255*7e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7) 256fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) 257*7e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6) 258fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) 259fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) 260fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) 261fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) 262fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) 263fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) 264fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) 265fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) 266fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) 267*7e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) 268fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) 269fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) 270fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) 271fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) 272fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) 273fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) 274*7e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_CONFIG6 MIPS_CP0_32(16, 6) 275*7e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) 276fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) 277*7e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2) 278*7e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3) 279*7e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4) 280*7e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5) 281*7e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6) 282*7e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7) 283fcf5ef2aSThomas Huth 284fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, 285fcf5ef2aSThomas Huth int32_t *addr) 286fcf5ef2aSThomas Huth { 287fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 288fcf5ef2aSThomas Huth .id = reg_id, 289fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 290fcf5ef2aSThomas Huth }; 291fcf5ef2aSThomas Huth 292fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 293fcf5ef2aSThomas Huth } 294fcf5ef2aSThomas Huth 295fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ureg(CPUState *cs, uint64_t reg_id, 296fcf5ef2aSThomas Huth uint32_t *addr) 297fcf5ef2aSThomas Huth { 298fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 299fcf5ef2aSThomas Huth .id = reg_id, 300fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 301fcf5ef2aSThomas Huth }; 302fcf5ef2aSThomas Huth 303fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 304fcf5ef2aSThomas Huth } 305fcf5ef2aSThomas Huth 306fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id, 307fcf5ef2aSThomas Huth target_ulong *addr) 308fcf5ef2aSThomas Huth { 309fcf5ef2aSThomas Huth uint64_t val64 = *addr; 310fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 311fcf5ef2aSThomas Huth .id = reg_id, 312fcf5ef2aSThomas Huth .addr = (uintptr_t)&val64 313fcf5ef2aSThomas Huth }; 314fcf5ef2aSThomas Huth 315fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 316fcf5ef2aSThomas Huth } 317fcf5ef2aSThomas Huth 318fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id, 319fcf5ef2aSThomas Huth int64_t *addr) 320fcf5ef2aSThomas Huth { 321fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 322fcf5ef2aSThomas Huth .id = reg_id, 323fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 324fcf5ef2aSThomas Huth }; 325fcf5ef2aSThomas Huth 326fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 327fcf5ef2aSThomas Huth } 328fcf5ef2aSThomas Huth 329fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ureg64(CPUState *cs, uint64_t reg_id, 330fcf5ef2aSThomas Huth uint64_t *addr) 331fcf5ef2aSThomas Huth { 332fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 333fcf5ef2aSThomas Huth .id = reg_id, 334fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 335fcf5ef2aSThomas Huth }; 336fcf5ef2aSThomas Huth 337fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 338fcf5ef2aSThomas Huth } 339fcf5ef2aSThomas Huth 340fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id, 341fcf5ef2aSThomas Huth int32_t *addr) 342fcf5ef2aSThomas Huth { 343fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 344fcf5ef2aSThomas Huth .id = reg_id, 345fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 346fcf5ef2aSThomas Huth }; 347fcf5ef2aSThomas Huth 348fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 349fcf5ef2aSThomas Huth } 350fcf5ef2aSThomas Huth 351fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ureg(CPUState *cs, uint64_t reg_id, 352fcf5ef2aSThomas Huth uint32_t *addr) 353fcf5ef2aSThomas Huth { 354fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 355fcf5ef2aSThomas Huth .id = reg_id, 356fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 357fcf5ef2aSThomas Huth }; 358fcf5ef2aSThomas Huth 359fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 360fcf5ef2aSThomas Huth } 361fcf5ef2aSThomas Huth 362fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64_t reg_id, 363fcf5ef2aSThomas Huth target_ulong *addr) 364fcf5ef2aSThomas Huth { 365fcf5ef2aSThomas Huth int ret; 366fcf5ef2aSThomas Huth uint64_t val64 = 0; 367fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 368fcf5ef2aSThomas Huth .id = reg_id, 369fcf5ef2aSThomas Huth .addr = (uintptr_t)&val64 370fcf5ef2aSThomas Huth }; 371fcf5ef2aSThomas Huth 372fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 373fcf5ef2aSThomas Huth if (ret >= 0) { 374fcf5ef2aSThomas Huth *addr = val64; 375fcf5ef2aSThomas Huth } 376fcf5ef2aSThomas Huth return ret; 377fcf5ef2aSThomas Huth } 378fcf5ef2aSThomas Huth 379fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64_t reg_id, 380fcf5ef2aSThomas Huth int64_t *addr) 381fcf5ef2aSThomas Huth { 382fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 383fcf5ef2aSThomas Huth .id = reg_id, 384fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 385fcf5ef2aSThomas Huth }; 386fcf5ef2aSThomas Huth 387fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 388fcf5ef2aSThomas Huth } 389fcf5ef2aSThomas Huth 390fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ureg64(CPUState *cs, uint64_t reg_id, 391fcf5ef2aSThomas Huth uint64_t *addr) 392fcf5ef2aSThomas Huth { 393fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 394fcf5ef2aSThomas Huth .id = reg_id, 395fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 396fcf5ef2aSThomas Huth }; 397fcf5ef2aSThomas Huth 398fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 399fcf5ef2aSThomas Huth } 400fcf5ef2aSThomas Huth 401fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M) 402fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG1_MASK ((1U << CP0C1_M) | \ 403fcf5ef2aSThomas Huth (1U << CP0C1_FP)) 404fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG2_MASK (1U << CP0C2_M) 405fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG3_MASK ((1U << CP0C3_M) | \ 406fcf5ef2aSThomas Huth (1U << CP0C3_MSAP)) 407fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG4_MASK (1U << CP0C4_M) 408fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG5_MASK ((1U << CP0C5_MSAEn) | \ 409fcf5ef2aSThomas Huth (1U << CP0C5_UFE) | \ 410fcf5ef2aSThomas Huth (1U << CP0C5_FRE) | \ 411fcf5ef2aSThomas Huth (1U << CP0C5_UFR)) 412*7e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ 413*7e0896b0SHuacai Chen (0x3fU << CP0C6_KPOS) | \ 414*7e0896b0SHuacai Chen (1U << CP0C6_KE) | \ 415*7e0896b0SHuacai Chen (1U << CP0C6_VTLBONLY) | \ 416*7e0896b0SHuacai Chen (1U << CP0C6_LASX) | \ 417*7e0896b0SHuacai Chen (1U << CP0C6_SSEN) | \ 418*7e0896b0SHuacai Chen (1U << CP0C6_DISDRTIME) | \ 419*7e0896b0SHuacai Chen (1U << CP0C6_PIXNUEN) | \ 420*7e0896b0SHuacai Chen (1U << CP0C6_SCRAND) | \ 421*7e0896b0SHuacai Chen (1U << CP0C6_LLEXCEN) | \ 422*7e0896b0SHuacai Chen (1U << CP0C6_DISVC) | \ 423*7e0896b0SHuacai Chen (1U << CP0C6_VCLRU) | \ 424*7e0896b0SHuacai Chen (1U << CP0C6_DCLRU) | \ 425*7e0896b0SHuacai Chen (1U << CP0C6_PIXUEN) | \ 426*7e0896b0SHuacai Chen (1U << CP0C6_DISBLKLYEN) | \ 427*7e0896b0SHuacai Chen (1U << CP0C6_UMEMUALEN) | \ 428*7e0896b0SHuacai Chen (1U << CP0C6_SFBEN) | \ 429*7e0896b0SHuacai Chen (1U << CP0C6_FLTINT) | \ 430*7e0896b0SHuacai Chen (1U << CP0C6_VLTINT) | \ 431*7e0896b0SHuacai Chen (1U << CP0C6_DISBTB) | \ 432*7e0896b0SHuacai Chen (3U << CP0C6_STPREFCTL) | \ 433*7e0896b0SHuacai Chen (1U << CP0C6_INSTPREF) | \ 434*7e0896b0SHuacai Chen (1U << CP0C6_DATAPREF)) 435fcf5ef2aSThomas Huth 436fcf5ef2aSThomas Huth static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id, 437fcf5ef2aSThomas Huth int32_t *addr, int32_t mask) 438fcf5ef2aSThomas Huth { 439fcf5ef2aSThomas Huth int err; 440fcf5ef2aSThomas Huth int32_t tmp, change; 441fcf5ef2aSThomas Huth 442fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, reg_id, &tmp); 443fcf5ef2aSThomas Huth if (err < 0) { 444fcf5ef2aSThomas Huth return err; 445fcf5ef2aSThomas Huth } 446fcf5ef2aSThomas Huth 447fcf5ef2aSThomas Huth /* only change bits in mask */ 448fcf5ef2aSThomas Huth change = (*addr ^ tmp) & mask; 449fcf5ef2aSThomas Huth if (!change) { 450fcf5ef2aSThomas Huth return 0; 451fcf5ef2aSThomas Huth } 452fcf5ef2aSThomas Huth 453fcf5ef2aSThomas Huth tmp = tmp ^ change; 454fcf5ef2aSThomas Huth return kvm_mips_put_one_reg(cs, reg_id, &tmp); 455fcf5ef2aSThomas Huth } 456fcf5ef2aSThomas Huth 457fcf5ef2aSThomas Huth /* 458fcf5ef2aSThomas Huth * We freeze the KVM timer when either the VM clock is stopped or the state is 459fcf5ef2aSThomas Huth * saved (the state is dirty). 460fcf5ef2aSThomas Huth */ 461fcf5ef2aSThomas Huth 462fcf5ef2aSThomas Huth /* 463fcf5ef2aSThomas Huth * Save the state of the KVM timer when VM clock is stopped or state is synced 464fcf5ef2aSThomas Huth * to QEMU. 465fcf5ef2aSThomas Huth */ 466fcf5ef2aSThomas Huth static int kvm_mips_save_count(CPUState *cs) 467fcf5ef2aSThomas Huth { 468fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 469fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 470fcf5ef2aSThomas Huth uint64_t count_ctl; 471fcf5ef2aSThomas Huth int err, ret = 0; 472fcf5ef2aSThomas Huth 473fcf5ef2aSThomas Huth /* freeze KVM timer */ 474fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 475fcf5ef2aSThomas Huth if (err < 0) { 476fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err); 477fcf5ef2aSThomas Huth ret = err; 478fcf5ef2aSThomas Huth } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) { 479fcf5ef2aSThomas Huth count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC; 480fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 481fcf5ef2aSThomas Huth if (err < 0) { 482fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err); 483fcf5ef2aSThomas Huth ret = err; 484fcf5ef2aSThomas Huth } 485fcf5ef2aSThomas Huth } 486fcf5ef2aSThomas Huth 487fcf5ef2aSThomas Huth /* read CP0_Cause */ 488fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause); 489fcf5ef2aSThomas Huth if (err < 0) { 490fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err); 491fcf5ef2aSThomas Huth ret = err; 492fcf5ef2aSThomas Huth } 493fcf5ef2aSThomas Huth 494fcf5ef2aSThomas Huth /* read CP0_Count */ 495fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count); 496fcf5ef2aSThomas Huth if (err < 0) { 497fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err); 498fcf5ef2aSThomas Huth ret = err; 499fcf5ef2aSThomas Huth } 500fcf5ef2aSThomas Huth 501fcf5ef2aSThomas Huth return ret; 502fcf5ef2aSThomas Huth } 503fcf5ef2aSThomas Huth 504fcf5ef2aSThomas Huth /* 505fcf5ef2aSThomas Huth * Restore the state of the KVM timer when VM clock is restarted or state is 506fcf5ef2aSThomas Huth * synced to KVM. 507fcf5ef2aSThomas Huth */ 508fcf5ef2aSThomas Huth static int kvm_mips_restore_count(CPUState *cs) 509fcf5ef2aSThomas Huth { 510fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 511fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 512fcf5ef2aSThomas Huth uint64_t count_ctl; 513fcf5ef2aSThomas Huth int err_dc, err, ret = 0; 514fcf5ef2aSThomas Huth 515fcf5ef2aSThomas Huth /* check the timer is frozen */ 516fcf5ef2aSThomas Huth err_dc = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 517fcf5ef2aSThomas Huth if (err_dc < 0) { 518fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc); 519fcf5ef2aSThomas Huth ret = err_dc; 520fcf5ef2aSThomas Huth } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) { 521fcf5ef2aSThomas Huth /* freeze timer (sets COUNT_RESUME for us) */ 522fcf5ef2aSThomas Huth count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC; 523fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 524fcf5ef2aSThomas Huth if (err < 0) { 525fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err); 526fcf5ef2aSThomas Huth ret = err; 527fcf5ef2aSThomas Huth } 528fcf5ef2aSThomas Huth } 529fcf5ef2aSThomas Huth 530fcf5ef2aSThomas Huth /* load CP0_Cause */ 531fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause); 532fcf5ef2aSThomas Huth if (err < 0) { 533fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err); 534fcf5ef2aSThomas Huth ret = err; 535fcf5ef2aSThomas Huth } 536fcf5ef2aSThomas Huth 537fcf5ef2aSThomas Huth /* load CP0_Count */ 538fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count); 539fcf5ef2aSThomas Huth if (err < 0) { 540fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err); 541fcf5ef2aSThomas Huth ret = err; 542fcf5ef2aSThomas Huth } 543fcf5ef2aSThomas Huth 544fcf5ef2aSThomas Huth /* resume KVM timer */ 545fcf5ef2aSThomas Huth if (err_dc >= 0) { 546fcf5ef2aSThomas Huth count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC; 547fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 548fcf5ef2aSThomas Huth if (err < 0) { 549fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err); 550fcf5ef2aSThomas Huth ret = err; 551fcf5ef2aSThomas Huth } 552fcf5ef2aSThomas Huth } 553fcf5ef2aSThomas Huth 554fcf5ef2aSThomas Huth return ret; 555fcf5ef2aSThomas Huth } 556fcf5ef2aSThomas Huth 557fcf5ef2aSThomas Huth /* 558fcf5ef2aSThomas Huth * Handle the VM clock being started or stopped 559fcf5ef2aSThomas Huth */ 560fcf5ef2aSThomas Huth static void kvm_mips_update_state(void *opaque, int running, RunState state) 561fcf5ef2aSThomas Huth { 562fcf5ef2aSThomas Huth CPUState *cs = opaque; 563fcf5ef2aSThomas Huth int ret; 564fcf5ef2aSThomas Huth uint64_t count_resume; 565fcf5ef2aSThomas Huth 566fcf5ef2aSThomas Huth /* 567fcf5ef2aSThomas Huth * If state is already dirty (synced to QEMU) then the KVM timer state is 568fcf5ef2aSThomas Huth * already saved and can be restored when it is synced back to KVM. 569fcf5ef2aSThomas Huth */ 570fcf5ef2aSThomas Huth if (!running) { 57199f31832SSergio Andres Gomez Del Real if (!cs->vcpu_dirty) { 572fcf5ef2aSThomas Huth ret = kvm_mips_save_count(cs); 573fcf5ef2aSThomas Huth if (ret < 0) { 574288cb949SAlistair Francis warn_report("Failed saving count"); 575fcf5ef2aSThomas Huth } 576fcf5ef2aSThomas Huth } 577fcf5ef2aSThomas Huth } else { 578fcf5ef2aSThomas Huth /* Set clock restore time to now */ 579fcf5ef2aSThomas Huth count_resume = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 580fcf5ef2aSThomas Huth ret = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_RESUME, 581fcf5ef2aSThomas Huth &count_resume); 582fcf5ef2aSThomas Huth if (ret < 0) { 583288cb949SAlistair Francis warn_report("Failed setting COUNT_RESUME"); 584fcf5ef2aSThomas Huth return; 585fcf5ef2aSThomas Huth } 586fcf5ef2aSThomas Huth 58799f31832SSergio Andres Gomez Del Real if (!cs->vcpu_dirty) { 588fcf5ef2aSThomas Huth ret = kvm_mips_restore_count(cs); 589fcf5ef2aSThomas Huth if (ret < 0) { 590288cb949SAlistair Francis warn_report("Failed restoring count"); 591fcf5ef2aSThomas Huth } 592fcf5ef2aSThomas Huth } 593fcf5ef2aSThomas Huth } 594fcf5ef2aSThomas Huth } 595fcf5ef2aSThomas Huth 596fcf5ef2aSThomas Huth static int kvm_mips_put_fpu_registers(CPUState *cs, int level) 597fcf5ef2aSThomas Huth { 598fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 599fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 600fcf5ef2aSThomas Huth int err, ret = 0; 601fcf5ef2aSThomas Huth unsigned int i; 602fcf5ef2aSThomas Huth 603fcf5ef2aSThomas Huth /* Only put FPU state if we're emulating a CPU with an FPU */ 604fcf5ef2aSThomas Huth if (env->CP0_Config1 & (1 << CP0C1_FP)) { 605fcf5ef2aSThomas Huth /* FPU Control Registers */ 606fcf5ef2aSThomas Huth if (level == KVM_PUT_FULL_STATE) { 607fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg(cs, KVM_REG_MIPS_FCR_IR, 608fcf5ef2aSThomas Huth &env->active_fpu.fcr0); 609fcf5ef2aSThomas Huth if (err < 0) { 610fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FCR_IR (%d)\n", __func__, err); 611fcf5ef2aSThomas Huth ret = err; 612fcf5ef2aSThomas Huth } 613fcf5ef2aSThomas Huth } 614fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg(cs, KVM_REG_MIPS_FCR_CSR, 615fcf5ef2aSThomas Huth &env->active_fpu.fcr31); 616fcf5ef2aSThomas Huth if (err < 0) { 617fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FCR_CSR (%d)\n", __func__, err); 618fcf5ef2aSThomas Huth ret = err; 619fcf5ef2aSThomas Huth } 620fcf5ef2aSThomas Huth 621fcf5ef2aSThomas Huth /* 622fcf5ef2aSThomas Huth * FPU register state is a subset of MSA vector state, so don't put FPU 623fcf5ef2aSThomas Huth * registers if we're emulating a CPU with MSA. 624fcf5ef2aSThomas Huth */ 625fcf5ef2aSThomas Huth if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { 626fcf5ef2aSThomas Huth /* Floating point registers */ 627fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 628fcf5ef2aSThomas Huth if (env->CP0_Status & (1 << CP0St_FR)) { 629fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i), 630fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].d); 631fcf5ef2aSThomas Huth } else { 632fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i), 633fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); 634fcf5ef2aSThomas Huth } 635fcf5ef2aSThomas Huth if (err < 0) { 636fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FPR%u (%d)\n", __func__, i, err); 637fcf5ef2aSThomas Huth ret = err; 638fcf5ef2aSThomas Huth } 639fcf5ef2aSThomas Huth } 640fcf5ef2aSThomas Huth } 641fcf5ef2aSThomas Huth } 642fcf5ef2aSThomas Huth 643fcf5ef2aSThomas Huth /* Only put MSA state if we're emulating a CPU with MSA */ 644fcf5ef2aSThomas Huth if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { 645fcf5ef2aSThomas Huth /* MSA Control Registers */ 646fcf5ef2aSThomas Huth if (level == KVM_PUT_FULL_STATE) { 647fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_IR, 648fcf5ef2aSThomas Huth &env->msair); 649fcf5ef2aSThomas Huth if (err < 0) { 650fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put MSA_IR (%d)\n", __func__, err); 651fcf5ef2aSThomas Huth ret = err; 652fcf5ef2aSThomas Huth } 653fcf5ef2aSThomas Huth } 654fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_CSR, 655fcf5ef2aSThomas Huth &env->active_tc.msacsr); 656fcf5ef2aSThomas Huth if (err < 0) { 657fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put MSA_CSR (%d)\n", __func__, err); 658fcf5ef2aSThomas Huth ret = err; 659fcf5ef2aSThomas Huth } 660fcf5ef2aSThomas Huth 661fcf5ef2aSThomas Huth /* Vector registers (includes FP registers) */ 662fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 663fcf5ef2aSThomas Huth /* Big endian MSA not supported by QEMU yet anyway */ 664fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_VEC_128(i), 665fcf5ef2aSThomas Huth env->active_fpu.fpr[i].wr.d); 666fcf5ef2aSThomas Huth if (err < 0) { 667fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put VEC%u (%d)\n", __func__, i, err); 668fcf5ef2aSThomas Huth ret = err; 669fcf5ef2aSThomas Huth } 670fcf5ef2aSThomas Huth } 671fcf5ef2aSThomas Huth } 672fcf5ef2aSThomas Huth 673fcf5ef2aSThomas Huth return ret; 674fcf5ef2aSThomas Huth } 675fcf5ef2aSThomas Huth 676fcf5ef2aSThomas Huth static int kvm_mips_get_fpu_registers(CPUState *cs) 677fcf5ef2aSThomas Huth { 678fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 679fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 680fcf5ef2aSThomas Huth int err, ret = 0; 681fcf5ef2aSThomas Huth unsigned int i; 682fcf5ef2aSThomas Huth 683fcf5ef2aSThomas Huth /* Only get FPU state if we're emulating a CPU with an FPU */ 684fcf5ef2aSThomas Huth if (env->CP0_Config1 & (1 << CP0C1_FP)) { 685fcf5ef2aSThomas Huth /* FPU Control Registers */ 686fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_IR, 687fcf5ef2aSThomas Huth &env->active_fpu.fcr0); 688fcf5ef2aSThomas Huth if (err < 0) { 689fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FCR_IR (%d)\n", __func__, err); 690fcf5ef2aSThomas Huth ret = err; 691fcf5ef2aSThomas Huth } 692fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_CSR, 693fcf5ef2aSThomas Huth &env->active_fpu.fcr31); 694fcf5ef2aSThomas Huth if (err < 0) { 695fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FCR_CSR (%d)\n", __func__, err); 696fcf5ef2aSThomas Huth ret = err; 697fcf5ef2aSThomas Huth } else { 698fcf5ef2aSThomas Huth restore_fp_status(env); 699fcf5ef2aSThomas Huth } 700fcf5ef2aSThomas Huth 701fcf5ef2aSThomas Huth /* 702fcf5ef2aSThomas Huth * FPU register state is a subset of MSA vector state, so don't save FPU 703fcf5ef2aSThomas Huth * registers if we're emulating a CPU with MSA. 704fcf5ef2aSThomas Huth */ 705fcf5ef2aSThomas Huth if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { 706fcf5ef2aSThomas Huth /* Floating point registers */ 707fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 708fcf5ef2aSThomas Huth if (env->CP0_Status & (1 << CP0St_FR)) { 709fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i), 710fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].d); 711fcf5ef2aSThomas Huth } else { 712fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i), 713fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); 714fcf5ef2aSThomas Huth } 715fcf5ef2aSThomas Huth if (err < 0) { 716fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__, i, err); 717fcf5ef2aSThomas Huth ret = err; 718fcf5ef2aSThomas Huth } 719fcf5ef2aSThomas Huth } 720fcf5ef2aSThomas Huth } 721fcf5ef2aSThomas Huth } 722fcf5ef2aSThomas Huth 723fcf5ef2aSThomas Huth /* Only get MSA state if we're emulating a CPU with MSA */ 724fcf5ef2aSThomas Huth if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { 725fcf5ef2aSThomas Huth /* MSA Control Registers */ 726fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR, 727fcf5ef2aSThomas Huth &env->msair); 728fcf5ef2aSThomas Huth if (err < 0) { 729fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get MSA_IR (%d)\n", __func__, err); 730fcf5ef2aSThomas Huth ret = err; 731fcf5ef2aSThomas Huth } 732fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_CSR, 733fcf5ef2aSThomas Huth &env->active_tc.msacsr); 734fcf5ef2aSThomas Huth if (err < 0) { 735fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get MSA_CSR (%d)\n", __func__, err); 736fcf5ef2aSThomas Huth ret = err; 737fcf5ef2aSThomas Huth } else { 738fcf5ef2aSThomas Huth restore_msa_fp_status(env); 739fcf5ef2aSThomas Huth } 740fcf5ef2aSThomas Huth 741fcf5ef2aSThomas Huth /* Vector registers (includes FP registers) */ 742fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 743fcf5ef2aSThomas Huth /* Big endian MSA not supported by QEMU yet anyway */ 744fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_VEC_128(i), 745fcf5ef2aSThomas Huth env->active_fpu.fpr[i].wr.d); 746fcf5ef2aSThomas Huth if (err < 0) { 747fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get VEC%u (%d)\n", __func__, i, err); 748fcf5ef2aSThomas Huth ret = err; 749fcf5ef2aSThomas Huth } 750fcf5ef2aSThomas Huth } 751fcf5ef2aSThomas Huth } 752fcf5ef2aSThomas Huth 753fcf5ef2aSThomas Huth return ret; 754fcf5ef2aSThomas Huth } 755fcf5ef2aSThomas Huth 756fcf5ef2aSThomas Huth 757fcf5ef2aSThomas Huth static int kvm_mips_put_cp0_registers(CPUState *cs, int level) 758fcf5ef2aSThomas Huth { 759fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 760fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 761fcf5ef2aSThomas Huth int err, ret = 0; 762fcf5ef2aSThomas Huth 763fcf5ef2aSThomas Huth (void)level; 764fcf5ef2aSThomas Huth 765fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); 766fcf5ef2aSThomas Huth if (err < 0) { 767fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err); 768fcf5ef2aSThomas Huth ret = err; 769fcf5ef2aSThomas Huth } 770*7e0896b0SHuacai Chen err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_RANDOM, &env->CP0_Random); 771*7e0896b0SHuacai Chen if (err < 0) { 772*7e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_RANDOM (%d)\n", __func__, err); 773*7e0896b0SHuacai Chen ret = err; 774*7e0896b0SHuacai Chen } 775fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, 776fcf5ef2aSThomas Huth &env->CP0_Context); 777fcf5ef2aSThomas Huth if (err < 0) { 778fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err); 779fcf5ef2aSThomas Huth ret = err; 780fcf5ef2aSThomas Huth } 781fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL, 782fcf5ef2aSThomas Huth &env->active_tc.CP0_UserLocal); 783fcf5ef2aSThomas Huth if (err < 0) { 784fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err); 785fcf5ef2aSThomas Huth ret = err; 786fcf5ef2aSThomas Huth } 787fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK, 788fcf5ef2aSThomas Huth &env->CP0_PageMask); 789fcf5ef2aSThomas Huth if (err < 0) { 790fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err); 791fcf5ef2aSThomas Huth ret = err; 792fcf5ef2aSThomas Huth } 793*7e0896b0SHuacai Chen err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEGRAIN, 794*7e0896b0SHuacai Chen &env->CP0_PageGrain); 795*7e0896b0SHuacai Chen if (err < 0) { 796*7e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_PAGEGRAIN (%d)\n", __func__, err); 797*7e0896b0SHuacai Chen ret = err; 798*7e0896b0SHuacai Chen } 799*7e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWBASE, 800*7e0896b0SHuacai Chen &env->CP0_PWBase); 801*7e0896b0SHuacai Chen if (err < 0) { 802*7e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_PWBASE (%d)\n", __func__, err); 803*7e0896b0SHuacai Chen ret = err; 804*7e0896b0SHuacai Chen } 805*7e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWFIELD, 806*7e0896b0SHuacai Chen &env->CP0_PWField); 807*7e0896b0SHuacai Chen if (err < 0) { 808*7e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_PWField (%d)\n", __func__, err); 809*7e0896b0SHuacai Chen ret = err; 810*7e0896b0SHuacai Chen } 811*7e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWSIZE, 812*7e0896b0SHuacai Chen &env->CP0_PWSize); 813*7e0896b0SHuacai Chen if (err < 0) { 814*7e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_PWSIZE (%d)\n", __func__, err); 815*7e0896b0SHuacai Chen ret = err; 816*7e0896b0SHuacai Chen } 817fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); 818fcf5ef2aSThomas Huth if (err < 0) { 819fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err); 820fcf5ef2aSThomas Huth ret = err; 821fcf5ef2aSThomas Huth } 822*7e0896b0SHuacai Chen err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PWCTL, &env->CP0_PWCtl); 823*7e0896b0SHuacai Chen if (err < 0) { 824*7e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_PWCTL (%d)\n", __func__, err); 825*7e0896b0SHuacai Chen ret = err; 826*7e0896b0SHuacai Chen } 827fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); 828fcf5ef2aSThomas Huth if (err < 0) { 829fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err); 830fcf5ef2aSThomas Huth ret = err; 831fcf5ef2aSThomas Huth } 832fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR, 833fcf5ef2aSThomas Huth &env->CP0_BadVAddr); 834fcf5ef2aSThomas Huth if (err < 0) { 835fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err); 836fcf5ef2aSThomas Huth ret = err; 837fcf5ef2aSThomas Huth } 838fcf5ef2aSThomas Huth 839fcf5ef2aSThomas Huth /* If VM clock stopped then state will be restored when it is restarted */ 840fcf5ef2aSThomas Huth if (runstate_is_running()) { 841fcf5ef2aSThomas Huth err = kvm_mips_restore_count(cs); 842fcf5ef2aSThomas Huth if (err < 0) { 843fcf5ef2aSThomas Huth ret = err; 844fcf5ef2aSThomas Huth } 845fcf5ef2aSThomas Huth } 846fcf5ef2aSThomas Huth 847fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI, 848fcf5ef2aSThomas Huth &env->CP0_EntryHi); 849fcf5ef2aSThomas Huth if (err < 0) { 850fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err); 851fcf5ef2aSThomas Huth ret = err; 852fcf5ef2aSThomas Huth } 853fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE, 854fcf5ef2aSThomas Huth &env->CP0_Compare); 855fcf5ef2aSThomas Huth if (err < 0) { 856fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err); 857fcf5ef2aSThomas Huth ret = err; 858fcf5ef2aSThomas Huth } 859fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status); 860fcf5ef2aSThomas Huth if (err < 0) { 861fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err); 862fcf5ef2aSThomas Huth ret = err; 863fcf5ef2aSThomas Huth } 864fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC); 865fcf5ef2aSThomas Huth if (err < 0) { 866fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err); 867fcf5ef2aSThomas Huth ret = err; 868fcf5ef2aSThomas Huth } 869fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); 870fcf5ef2aSThomas Huth if (err < 0) { 871fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err); 872fcf5ef2aSThomas Huth ret = err; 873fcf5ef2aSThomas Huth } 874*7e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EBASE, &env->CP0_EBase); 875*7e0896b0SHuacai Chen if (err < 0) { 876*7e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_EBASE (%d)\n", __func__, err); 877*7e0896b0SHuacai Chen ret = err; 878*7e0896b0SHuacai Chen } 879fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, 880fcf5ef2aSThomas Huth &env->CP0_Config0, 881fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG_MASK); 882fcf5ef2aSThomas Huth if (err < 0) { 883fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG (%d)\n", __func__, err); 884fcf5ef2aSThomas Huth ret = err; 885fcf5ef2aSThomas Huth } 886fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, 887fcf5ef2aSThomas Huth &env->CP0_Config1, 888fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG1_MASK); 889fcf5ef2aSThomas Huth if (err < 0) { 890fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG1 (%d)\n", __func__, err); 891fcf5ef2aSThomas Huth ret = err; 892fcf5ef2aSThomas Huth } 893fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2, 894fcf5ef2aSThomas Huth &env->CP0_Config2, 895fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG2_MASK); 896fcf5ef2aSThomas Huth if (err < 0) { 897fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG2 (%d)\n", __func__, err); 898fcf5ef2aSThomas Huth ret = err; 899fcf5ef2aSThomas Huth } 900fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3, 901fcf5ef2aSThomas Huth &env->CP0_Config3, 902fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG3_MASK); 903fcf5ef2aSThomas Huth if (err < 0) { 904fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG3 (%d)\n", __func__, err); 905fcf5ef2aSThomas Huth ret = err; 906fcf5ef2aSThomas Huth } 907fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4, 908fcf5ef2aSThomas Huth &env->CP0_Config4, 909fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG4_MASK); 910fcf5ef2aSThomas Huth if (err < 0) { 911fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG4 (%d)\n", __func__, err); 912fcf5ef2aSThomas Huth ret = err; 913fcf5ef2aSThomas Huth } 914fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, 915fcf5ef2aSThomas Huth &env->CP0_Config5, 916fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG5_MASK); 917fcf5ef2aSThomas Huth if (err < 0) { 918fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG5 (%d)\n", __func__, err); 919fcf5ef2aSThomas Huth ret = err; 920fcf5ef2aSThomas Huth } 921*7e0896b0SHuacai Chen err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG6, 922*7e0896b0SHuacai Chen &env->CP0_Config6, 923*7e0896b0SHuacai Chen KVM_REG_MIPS_CP0_CONFIG6_MASK); 924*7e0896b0SHuacai Chen if (err < 0) { 925*7e0896b0SHuacai Chen DPRINTF("%s: Failed to change CP0_CONFIG6 (%d)\n", __func__, err); 926*7e0896b0SHuacai Chen ret = err; 927*7e0896b0SHuacai Chen } 928*7e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_XCONTEXT, 929*7e0896b0SHuacai Chen &env->CP0_XContext); 930*7e0896b0SHuacai Chen if (err < 0) { 931*7e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_XCONTEXT (%d)\n", __func__, err); 932*7e0896b0SHuacai Chen ret = err; 933*7e0896b0SHuacai Chen } 934fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, 935fcf5ef2aSThomas Huth &env->CP0_ErrorEPC); 936fcf5ef2aSThomas Huth if (err < 0) { 937fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err); 938fcf5ef2aSThomas Huth ret = err; 939fcf5ef2aSThomas Huth } 940*7e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH1, 941*7e0896b0SHuacai Chen &env->CP0_KScratch[0]); 942*7e0896b0SHuacai Chen if (err < 0) { 943*7e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH1 (%d)\n", __func__, err); 944*7e0896b0SHuacai Chen ret = err; 945*7e0896b0SHuacai Chen } 946*7e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH2, 947*7e0896b0SHuacai Chen &env->CP0_KScratch[1]); 948*7e0896b0SHuacai Chen if (err < 0) { 949*7e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH2 (%d)\n", __func__, err); 950*7e0896b0SHuacai Chen ret = err; 951*7e0896b0SHuacai Chen } 952*7e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH3, 953*7e0896b0SHuacai Chen &env->CP0_KScratch[2]); 954*7e0896b0SHuacai Chen if (err < 0) { 955*7e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH3 (%d)\n", __func__, err); 956*7e0896b0SHuacai Chen ret = err; 957*7e0896b0SHuacai Chen } 958*7e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH4, 959*7e0896b0SHuacai Chen &env->CP0_KScratch[3]); 960*7e0896b0SHuacai Chen if (err < 0) { 961*7e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH4 (%d)\n", __func__, err); 962*7e0896b0SHuacai Chen ret = err; 963*7e0896b0SHuacai Chen } 964*7e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH5, 965*7e0896b0SHuacai Chen &env->CP0_KScratch[4]); 966*7e0896b0SHuacai Chen if (err < 0) { 967*7e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH5 (%d)\n", __func__, err); 968*7e0896b0SHuacai Chen ret = err; 969*7e0896b0SHuacai Chen } 970*7e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH6, 971*7e0896b0SHuacai Chen &env->CP0_KScratch[5]); 972*7e0896b0SHuacai Chen if (err < 0) { 973*7e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH6 (%d)\n", __func__, err); 974*7e0896b0SHuacai Chen ret = err; 975*7e0896b0SHuacai Chen } 976fcf5ef2aSThomas Huth 977fcf5ef2aSThomas Huth return ret; 978fcf5ef2aSThomas Huth } 979fcf5ef2aSThomas Huth 980fcf5ef2aSThomas Huth static int kvm_mips_get_cp0_registers(CPUState *cs) 981fcf5ef2aSThomas Huth { 982fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 983fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 984fcf5ef2aSThomas Huth int err, ret = 0; 985fcf5ef2aSThomas Huth 986fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); 987fcf5ef2aSThomas Huth if (err < 0) { 988fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err); 989fcf5ef2aSThomas Huth ret = err; 990fcf5ef2aSThomas Huth } 991*7e0896b0SHuacai Chen err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_RANDOM, &env->CP0_Random); 992*7e0896b0SHuacai Chen if (err < 0) { 993*7e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_RANDOM (%d)\n", __func__, err); 994*7e0896b0SHuacai Chen ret = err; 995*7e0896b0SHuacai Chen } 996fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, 997fcf5ef2aSThomas Huth &env->CP0_Context); 998fcf5ef2aSThomas Huth if (err < 0) { 999fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err); 1000fcf5ef2aSThomas Huth ret = err; 1001fcf5ef2aSThomas Huth } 1002fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL, 1003fcf5ef2aSThomas Huth &env->active_tc.CP0_UserLocal); 1004fcf5ef2aSThomas Huth if (err < 0) { 1005fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err); 1006fcf5ef2aSThomas Huth ret = err; 1007fcf5ef2aSThomas Huth } 1008fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK, 1009fcf5ef2aSThomas Huth &env->CP0_PageMask); 1010fcf5ef2aSThomas Huth if (err < 0) { 1011fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err); 1012fcf5ef2aSThomas Huth ret = err; 1013fcf5ef2aSThomas Huth } 1014*7e0896b0SHuacai Chen err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEGRAIN, 1015*7e0896b0SHuacai Chen &env->CP0_PageGrain); 1016*7e0896b0SHuacai Chen if (err < 0) { 1017*7e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_PAGEGRAIN (%d)\n", __func__, err); 1018*7e0896b0SHuacai Chen ret = err; 1019*7e0896b0SHuacai Chen } 1020*7e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWBASE, 1021*7e0896b0SHuacai Chen &env->CP0_PWBase); 1022*7e0896b0SHuacai Chen if (err < 0) { 1023*7e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_PWBASE (%d)\n", __func__, err); 1024*7e0896b0SHuacai Chen ret = err; 1025*7e0896b0SHuacai Chen } 1026*7e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWFIELD, 1027*7e0896b0SHuacai Chen &env->CP0_PWField); 1028*7e0896b0SHuacai Chen if (err < 0) { 1029*7e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_PWFIELD (%d)\n", __func__, err); 1030*7e0896b0SHuacai Chen ret = err; 1031*7e0896b0SHuacai Chen } 1032*7e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWSIZE, 1033*7e0896b0SHuacai Chen &env->CP0_PWSize); 1034*7e0896b0SHuacai Chen if (err < 0) { 1035*7e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_PWSIZE (%d)\n", __func__, err); 1036*7e0896b0SHuacai Chen ret = err; 1037*7e0896b0SHuacai Chen } 1038fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); 1039fcf5ef2aSThomas Huth if (err < 0) { 1040fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err); 1041fcf5ef2aSThomas Huth ret = err; 1042fcf5ef2aSThomas Huth } 1043*7e0896b0SHuacai Chen err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PWCTL, &env->CP0_PWCtl); 1044*7e0896b0SHuacai Chen if (err < 0) { 1045*7e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_PWCtl (%d)\n", __func__, err); 1046*7e0896b0SHuacai Chen ret = err; 1047*7e0896b0SHuacai Chen } 1048fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); 1049fcf5ef2aSThomas Huth if (err < 0) { 1050fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err); 1051fcf5ef2aSThomas Huth ret = err; 1052fcf5ef2aSThomas Huth } 1053fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR, 1054fcf5ef2aSThomas Huth &env->CP0_BadVAddr); 1055fcf5ef2aSThomas Huth if (err < 0) { 1056fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err); 1057fcf5ef2aSThomas Huth ret = err; 1058fcf5ef2aSThomas Huth } 1059fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI, 1060fcf5ef2aSThomas Huth &env->CP0_EntryHi); 1061fcf5ef2aSThomas Huth if (err < 0) { 1062fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err); 1063fcf5ef2aSThomas Huth ret = err; 1064fcf5ef2aSThomas Huth } 1065fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE, 1066fcf5ef2aSThomas Huth &env->CP0_Compare); 1067fcf5ef2aSThomas Huth if (err < 0) { 1068fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err); 1069fcf5ef2aSThomas Huth ret = err; 1070fcf5ef2aSThomas Huth } 1071fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status); 1072fcf5ef2aSThomas Huth if (err < 0) { 1073fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err); 1074fcf5ef2aSThomas Huth ret = err; 1075fcf5ef2aSThomas Huth } 1076fcf5ef2aSThomas Huth 1077fcf5ef2aSThomas Huth /* If VM clock stopped then state was already saved when it was stopped */ 1078fcf5ef2aSThomas Huth if (runstate_is_running()) { 1079fcf5ef2aSThomas Huth err = kvm_mips_save_count(cs); 1080fcf5ef2aSThomas Huth if (err < 0) { 1081fcf5ef2aSThomas Huth ret = err; 1082fcf5ef2aSThomas Huth } 1083fcf5ef2aSThomas Huth } 1084fcf5ef2aSThomas Huth 1085fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC); 1086fcf5ef2aSThomas Huth if (err < 0) { 1087fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err); 1088fcf5ef2aSThomas Huth ret = err; 1089fcf5ef2aSThomas Huth } 1090fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); 1091fcf5ef2aSThomas Huth if (err < 0) { 1092fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err); 1093fcf5ef2aSThomas Huth ret = err; 1094fcf5ef2aSThomas Huth } 1095*7e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EBASE, &env->CP0_EBase); 1096*7e0896b0SHuacai Chen if (err < 0) { 1097*7e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_EBASE (%d)\n", __func__, err); 1098*7e0896b0SHuacai Chen ret = err; 1099*7e0896b0SHuacai Chen } 1100fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, &env->CP0_Config0); 1101fcf5ef2aSThomas Huth if (err < 0) { 1102fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG (%d)\n", __func__, err); 1103fcf5ef2aSThomas Huth ret = err; 1104fcf5ef2aSThomas Huth } 1105fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, &env->CP0_Config1); 1106fcf5ef2aSThomas Huth if (err < 0) { 1107fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG1 (%d)\n", __func__, err); 1108fcf5ef2aSThomas Huth ret = err; 1109fcf5ef2aSThomas Huth } 1110fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2, &env->CP0_Config2); 1111fcf5ef2aSThomas Huth if (err < 0) { 1112fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG2 (%d)\n", __func__, err); 1113fcf5ef2aSThomas Huth ret = err; 1114fcf5ef2aSThomas Huth } 1115fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3, &env->CP0_Config3); 1116fcf5ef2aSThomas Huth if (err < 0) { 1117fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG3 (%d)\n", __func__, err); 1118fcf5ef2aSThomas Huth ret = err; 1119fcf5ef2aSThomas Huth } 1120fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4, &env->CP0_Config4); 1121fcf5ef2aSThomas Huth if (err < 0) { 1122fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG4 (%d)\n", __func__, err); 1123fcf5ef2aSThomas Huth ret = err; 1124fcf5ef2aSThomas Huth } 1125fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, &env->CP0_Config5); 1126fcf5ef2aSThomas Huth if (err < 0) { 1127fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG5 (%d)\n", __func__, err); 1128fcf5ef2aSThomas Huth ret = err; 1129fcf5ef2aSThomas Huth } 1130*7e0896b0SHuacai Chen err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG6, &env->CP0_Config6); 1131*7e0896b0SHuacai Chen if (err < 0) { 1132*7e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_CONFIG6 (%d)\n", __func__, err); 1133*7e0896b0SHuacai Chen ret = err; 1134*7e0896b0SHuacai Chen } 1135*7e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_XCONTEXT, 1136*7e0896b0SHuacai Chen &env->CP0_XContext); 1137*7e0896b0SHuacai Chen if (err < 0) { 1138*7e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_XCONTEXT (%d)\n", __func__, err); 1139*7e0896b0SHuacai Chen ret = err; 1140*7e0896b0SHuacai Chen } 1141fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, 1142fcf5ef2aSThomas Huth &env->CP0_ErrorEPC); 1143fcf5ef2aSThomas Huth if (err < 0) { 1144fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err); 1145fcf5ef2aSThomas Huth ret = err; 1146fcf5ef2aSThomas Huth } 1147*7e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH1, 1148*7e0896b0SHuacai Chen &env->CP0_KScratch[0]); 1149*7e0896b0SHuacai Chen if (err < 0) { 1150*7e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH1 (%d)\n", __func__, err); 1151*7e0896b0SHuacai Chen ret = err; 1152*7e0896b0SHuacai Chen } 1153*7e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH2, 1154*7e0896b0SHuacai Chen &env->CP0_KScratch[1]); 1155*7e0896b0SHuacai Chen if (err < 0) { 1156*7e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH2 (%d)\n", __func__, err); 1157*7e0896b0SHuacai Chen ret = err; 1158*7e0896b0SHuacai Chen } 1159*7e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH3, 1160*7e0896b0SHuacai Chen &env->CP0_KScratch[2]); 1161*7e0896b0SHuacai Chen if (err < 0) { 1162*7e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH3 (%d)\n", __func__, err); 1163*7e0896b0SHuacai Chen ret = err; 1164*7e0896b0SHuacai Chen } 1165*7e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH4, 1166*7e0896b0SHuacai Chen &env->CP0_KScratch[3]); 1167*7e0896b0SHuacai Chen if (err < 0) { 1168*7e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH4 (%d)\n", __func__, err); 1169*7e0896b0SHuacai Chen ret = err; 1170*7e0896b0SHuacai Chen } 1171*7e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH5, 1172*7e0896b0SHuacai Chen &env->CP0_KScratch[4]); 1173*7e0896b0SHuacai Chen if (err < 0) { 1174*7e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH5 (%d)\n", __func__, err); 1175*7e0896b0SHuacai Chen ret = err; 1176*7e0896b0SHuacai Chen } 1177*7e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH6, 1178*7e0896b0SHuacai Chen &env->CP0_KScratch[5]); 1179*7e0896b0SHuacai Chen if (err < 0) { 1180*7e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH6 (%d)\n", __func__, err); 1181*7e0896b0SHuacai Chen ret = err; 1182*7e0896b0SHuacai Chen } 1183fcf5ef2aSThomas Huth 1184fcf5ef2aSThomas Huth return ret; 1185fcf5ef2aSThomas Huth } 1186fcf5ef2aSThomas Huth 1187fcf5ef2aSThomas Huth int kvm_arch_put_registers(CPUState *cs, int level) 1188fcf5ef2aSThomas Huth { 1189fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 1190fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 1191fcf5ef2aSThomas Huth struct kvm_regs regs; 1192fcf5ef2aSThomas Huth int ret; 1193fcf5ef2aSThomas Huth int i; 1194fcf5ef2aSThomas Huth 1195fcf5ef2aSThomas Huth /* Set the registers based on QEMU's view of things */ 1196fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 1197fcf5ef2aSThomas Huth regs.gpr[i] = (int64_t)(target_long)env->active_tc.gpr[i]; 1198fcf5ef2aSThomas Huth } 1199fcf5ef2aSThomas Huth 1200fcf5ef2aSThomas Huth regs.hi = (int64_t)(target_long)env->active_tc.HI[0]; 1201fcf5ef2aSThomas Huth regs.lo = (int64_t)(target_long)env->active_tc.LO[0]; 1202fcf5ef2aSThomas Huth regs.pc = (int64_t)(target_long)env->active_tc.PC; 1203fcf5ef2aSThomas Huth 1204fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); 1205fcf5ef2aSThomas Huth 1206fcf5ef2aSThomas Huth if (ret < 0) { 1207fcf5ef2aSThomas Huth return ret; 1208fcf5ef2aSThomas Huth } 1209fcf5ef2aSThomas Huth 1210fcf5ef2aSThomas Huth ret = kvm_mips_put_cp0_registers(cs, level); 1211fcf5ef2aSThomas Huth if (ret < 0) { 1212fcf5ef2aSThomas Huth return ret; 1213fcf5ef2aSThomas Huth } 1214fcf5ef2aSThomas Huth 1215fcf5ef2aSThomas Huth ret = kvm_mips_put_fpu_registers(cs, level); 1216fcf5ef2aSThomas Huth if (ret < 0) { 1217fcf5ef2aSThomas Huth return ret; 1218fcf5ef2aSThomas Huth } 1219fcf5ef2aSThomas Huth 1220fcf5ef2aSThomas Huth return ret; 1221fcf5ef2aSThomas Huth } 1222fcf5ef2aSThomas Huth 1223fcf5ef2aSThomas Huth int kvm_arch_get_registers(CPUState *cs) 1224fcf5ef2aSThomas Huth { 1225fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 1226fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 1227fcf5ef2aSThomas Huth int ret = 0; 1228fcf5ef2aSThomas Huth struct kvm_regs regs; 1229fcf5ef2aSThomas Huth int i; 1230fcf5ef2aSThomas Huth 1231fcf5ef2aSThomas Huth /* Get the current register set as KVM seems it */ 1232fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 1233fcf5ef2aSThomas Huth 1234fcf5ef2aSThomas Huth if (ret < 0) { 1235fcf5ef2aSThomas Huth return ret; 1236fcf5ef2aSThomas Huth } 1237fcf5ef2aSThomas Huth 1238fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 1239fcf5ef2aSThomas Huth env->active_tc.gpr[i] = regs.gpr[i]; 1240fcf5ef2aSThomas Huth } 1241fcf5ef2aSThomas Huth 1242fcf5ef2aSThomas Huth env->active_tc.HI[0] = regs.hi; 1243fcf5ef2aSThomas Huth env->active_tc.LO[0] = regs.lo; 1244fcf5ef2aSThomas Huth env->active_tc.PC = regs.pc; 1245fcf5ef2aSThomas Huth 1246fcf5ef2aSThomas Huth kvm_mips_get_cp0_registers(cs); 1247fcf5ef2aSThomas Huth kvm_mips_get_fpu_registers(cs); 1248fcf5ef2aSThomas Huth 1249fcf5ef2aSThomas Huth return ret; 1250fcf5ef2aSThomas Huth } 1251fcf5ef2aSThomas Huth 1252fcf5ef2aSThomas Huth int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1253fcf5ef2aSThomas Huth uint64_t address, uint32_t data, PCIDevice *dev) 1254fcf5ef2aSThomas Huth { 1255fcf5ef2aSThomas Huth return 0; 1256fcf5ef2aSThomas Huth } 1257fcf5ef2aSThomas Huth 1258fcf5ef2aSThomas Huth int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1259fcf5ef2aSThomas Huth int vector, PCIDevice *dev) 1260fcf5ef2aSThomas Huth { 1261fcf5ef2aSThomas Huth return 0; 1262fcf5ef2aSThomas Huth } 1263fcf5ef2aSThomas Huth 1264fcf5ef2aSThomas Huth int kvm_arch_release_virq_post(int virq) 1265fcf5ef2aSThomas Huth { 1266fcf5ef2aSThomas Huth return 0; 1267fcf5ef2aSThomas Huth } 1268fcf5ef2aSThomas Huth 1269fcf5ef2aSThomas Huth int kvm_arch_msi_data_to_gsi(uint32_t data) 1270fcf5ef2aSThomas Huth { 1271fcf5ef2aSThomas Huth abort(); 1272fcf5ef2aSThomas Huth } 1273