1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * This file is subject to the terms and conditions of the GNU General Public 3fcf5ef2aSThomas Huth * License. See the file "COPYING" in the main directory of this archive 4fcf5ef2aSThomas Huth * for more details. 5fcf5ef2aSThomas Huth * 6fcf5ef2aSThomas Huth * KVM/MIPS: MIPS specific KVM APIs 7fcf5ef2aSThomas Huth * 8fcf5ef2aSThomas Huth * Copyright (C) 2012-2014 Imagination Technologies Ltd. 9fcf5ef2aSThomas Huth * Authors: Sanjay Lal <sanjayl@kymasys.com> 10fcf5ef2aSThomas Huth */ 11fcf5ef2aSThomas Huth 12fcf5ef2aSThomas Huth #include "qemu/osdep.h" 13fcf5ef2aSThomas Huth #include <sys/ioctl.h> 14fcf5ef2aSThomas Huth 15fcf5ef2aSThomas Huth #include <linux/kvm.h> 16fcf5ef2aSThomas Huth 17fcf5ef2aSThomas Huth #include "qemu-common.h" 18fcf5ef2aSThomas Huth #include "cpu.h" 1926aa3d9aSPhilippe Mathieu-Daudé #include "internal.h" 20fcf5ef2aSThomas Huth #include "qemu/error-report.h" 21db725815SMarkus Armbruster #include "qemu/main-loop.h" 22fcf5ef2aSThomas Huth #include "sysemu/kvm.h" 23719d109bSHuacai Chen #include "sysemu/kvm_int.h" 2454d31236SMarkus Armbruster #include "sysemu/runstate.h" 25fcf5ef2aSThomas Huth #include "kvm_mips.h" 26719d109bSHuacai Chen #include "hw/boards.h" 2781ddae7cSPhilippe Mathieu-Daudé #include "fpu_helper.h" 28fcf5ef2aSThomas Huth 29fcf5ef2aSThomas Huth #define DEBUG_KVM 0 30fcf5ef2aSThomas Huth 31fcf5ef2aSThomas Huth #define DPRINTF(fmt, ...) \ 32fcf5ef2aSThomas Huth do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0) 33fcf5ef2aSThomas Huth 34fcf5ef2aSThomas Huth static int kvm_mips_fpu_cap; 35fcf5ef2aSThomas Huth static int kvm_mips_msa_cap; 36fcf5ef2aSThomas Huth 37fcf5ef2aSThomas Huth const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 38fcf5ef2aSThomas Huth KVM_CAP_LAST_INFO 39fcf5ef2aSThomas Huth }; 40fcf5ef2aSThomas Huth 41*538f0497SPhilippe Mathieu-Daudé static void kvm_mips_update_state(void *opaque, bool running, RunState state); 42fcf5ef2aSThomas Huth 43fcf5ef2aSThomas Huth unsigned long kvm_arch_vcpu_id(CPUState *cs) 44fcf5ef2aSThomas Huth { 45fcf5ef2aSThomas Huth return cs->cpu_index; 46fcf5ef2aSThomas Huth } 47fcf5ef2aSThomas Huth 48fcf5ef2aSThomas Huth int kvm_arch_init(MachineState *ms, KVMState *s) 49fcf5ef2aSThomas Huth { 50fcf5ef2aSThomas Huth /* MIPS has 128 signals */ 51fcf5ef2aSThomas Huth kvm_set_sigmask_len(s, 16); 52fcf5ef2aSThomas Huth 53fcf5ef2aSThomas Huth kvm_mips_fpu_cap = kvm_check_extension(s, KVM_CAP_MIPS_FPU); 54fcf5ef2aSThomas Huth kvm_mips_msa_cap = kvm_check_extension(s, KVM_CAP_MIPS_MSA); 55fcf5ef2aSThomas Huth 56fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 57fcf5ef2aSThomas Huth return 0; 58fcf5ef2aSThomas Huth } 59fcf5ef2aSThomas Huth 604376c40dSPaolo Bonzini int kvm_arch_irqchip_create(KVMState *s) 61d525ffabSPaolo Bonzini { 62d525ffabSPaolo Bonzini return 0; 63d525ffabSPaolo Bonzini } 64d525ffabSPaolo Bonzini 65fcf5ef2aSThomas Huth int kvm_arch_init_vcpu(CPUState *cs) 66fcf5ef2aSThomas Huth { 67fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 68fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 69fcf5ef2aSThomas Huth int ret = 0; 70fcf5ef2aSThomas Huth 71fcf5ef2aSThomas Huth qemu_add_vm_change_state_handler(kvm_mips_update_state, cs); 72fcf5ef2aSThomas Huth 73fcf5ef2aSThomas Huth if (kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) { 74fcf5ef2aSThomas Huth ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_FPU, 0, 0); 75fcf5ef2aSThomas Huth if (ret < 0) { 76fcf5ef2aSThomas Huth /* mark unsupported so it gets disabled on reset */ 77fcf5ef2aSThomas Huth kvm_mips_fpu_cap = 0; 78fcf5ef2aSThomas Huth ret = 0; 79fcf5ef2aSThomas Huth } 80fcf5ef2aSThomas Huth } 81fcf5ef2aSThomas Huth 8225a13628SPhilippe Mathieu-Daudé if (kvm_mips_msa_cap && ase_msa_available(env)) { 83fcf5ef2aSThomas Huth ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0); 84fcf5ef2aSThomas Huth if (ret < 0) { 85fcf5ef2aSThomas Huth /* mark unsupported so it gets disabled on reset */ 86fcf5ef2aSThomas Huth kvm_mips_msa_cap = 0; 87fcf5ef2aSThomas Huth ret = 0; 88fcf5ef2aSThomas Huth } 89fcf5ef2aSThomas Huth } 90fcf5ef2aSThomas Huth 91fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 92fcf5ef2aSThomas Huth return ret; 93fcf5ef2aSThomas Huth } 94fcf5ef2aSThomas Huth 95b1115c99SLiran Alon int kvm_arch_destroy_vcpu(CPUState *cs) 96b1115c99SLiran Alon { 97b1115c99SLiran Alon return 0; 98b1115c99SLiran Alon } 99b1115c99SLiran Alon 100fcf5ef2aSThomas Huth void kvm_mips_reset_vcpu(MIPSCPU *cpu) 101fcf5ef2aSThomas Huth { 102fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 103fcf5ef2aSThomas Huth 104fcf5ef2aSThomas Huth if (!kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) { 1052ab4b135SAlistair Francis warn_report("KVM does not support FPU, disabling"); 106fcf5ef2aSThomas Huth env->CP0_Config1 &= ~(1 << CP0C1_FP); 107fcf5ef2aSThomas Huth } 10825a13628SPhilippe Mathieu-Daudé if (!kvm_mips_msa_cap && ase_msa_available(env)) { 1092ab4b135SAlistair Francis warn_report("KVM does not support MSA, disabling"); 110fcf5ef2aSThomas Huth env->CP0_Config3 &= ~(1 << CP0C3_MSAP); 111fcf5ef2aSThomas Huth } 112fcf5ef2aSThomas Huth 113fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 114fcf5ef2aSThomas Huth } 115fcf5ef2aSThomas Huth 116fcf5ef2aSThomas Huth int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 117fcf5ef2aSThomas Huth { 118fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 119fcf5ef2aSThomas Huth return 0; 120fcf5ef2aSThomas Huth } 121fcf5ef2aSThomas Huth 122fcf5ef2aSThomas Huth int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 123fcf5ef2aSThomas Huth { 124fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 125fcf5ef2aSThomas Huth return 0; 126fcf5ef2aSThomas Huth } 127fcf5ef2aSThomas Huth 128fcf5ef2aSThomas Huth static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu) 129fcf5ef2aSThomas Huth { 130fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 131fcf5ef2aSThomas Huth 132fcf5ef2aSThomas Huth return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP)); 133fcf5ef2aSThomas Huth } 134fcf5ef2aSThomas Huth 135fcf5ef2aSThomas Huth 136fcf5ef2aSThomas Huth void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 137fcf5ef2aSThomas Huth { 138fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 139fcf5ef2aSThomas Huth int r; 140fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 141fcf5ef2aSThomas Huth 142fcf5ef2aSThomas Huth qemu_mutex_lock_iothread(); 143fcf5ef2aSThomas Huth 144fcf5ef2aSThomas Huth if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 145fcf5ef2aSThomas Huth cpu_mips_io_interrupts_pending(cpu)) { 146fcf5ef2aSThomas Huth intr.cpu = -1; 147fcf5ef2aSThomas Huth intr.irq = 2; 148fcf5ef2aSThomas Huth r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 149fcf5ef2aSThomas Huth if (r < 0) { 150fcf5ef2aSThomas Huth error_report("%s: cpu %d: failed to inject IRQ %x", 151fcf5ef2aSThomas Huth __func__, cs->cpu_index, intr.irq); 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth } 154fcf5ef2aSThomas Huth 155fcf5ef2aSThomas Huth qemu_mutex_unlock_iothread(); 156fcf5ef2aSThomas Huth } 157fcf5ef2aSThomas Huth 158fcf5ef2aSThomas Huth MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 159fcf5ef2aSThomas Huth { 160fcf5ef2aSThomas Huth return MEMTXATTRS_UNSPECIFIED; 161fcf5ef2aSThomas Huth } 162fcf5ef2aSThomas Huth 163fcf5ef2aSThomas Huth int kvm_arch_process_async_events(CPUState *cs) 164fcf5ef2aSThomas Huth { 165fcf5ef2aSThomas Huth return cs->halted; 166fcf5ef2aSThomas Huth } 167fcf5ef2aSThomas Huth 168fcf5ef2aSThomas Huth int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 169fcf5ef2aSThomas Huth { 170fcf5ef2aSThomas Huth int ret; 171fcf5ef2aSThomas Huth 172fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 173fcf5ef2aSThomas Huth switch (run->exit_reason) { 174fcf5ef2aSThomas Huth default: 175fcf5ef2aSThomas Huth error_report("%s: unknown exit reason %d", 176fcf5ef2aSThomas Huth __func__, run->exit_reason); 177fcf5ef2aSThomas Huth ret = -1; 178fcf5ef2aSThomas Huth break; 179fcf5ef2aSThomas Huth } 180fcf5ef2aSThomas Huth 181fcf5ef2aSThomas Huth return ret; 182fcf5ef2aSThomas Huth } 183fcf5ef2aSThomas Huth 184fcf5ef2aSThomas Huth bool kvm_arch_stop_on_emulation_error(CPUState *cs) 185fcf5ef2aSThomas Huth { 186fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 187fcf5ef2aSThomas Huth return true; 188fcf5ef2aSThomas Huth } 189fcf5ef2aSThomas Huth 190fcf5ef2aSThomas Huth void kvm_arch_init_irq_routing(KVMState *s) 191fcf5ef2aSThomas Huth { 192fcf5ef2aSThomas Huth } 193fcf5ef2aSThomas Huth 194fcf5ef2aSThomas Huth int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level) 195fcf5ef2aSThomas Huth { 196fcf5ef2aSThomas Huth CPUState *cs = CPU(cpu); 197fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 198fcf5ef2aSThomas Huth 19911cb076bSPhilippe Mathieu-Daudé assert(kvm_enabled()); 200fcf5ef2aSThomas Huth 201fcf5ef2aSThomas Huth intr.cpu = -1; 202fcf5ef2aSThomas Huth 203fcf5ef2aSThomas Huth if (level) { 204fcf5ef2aSThomas Huth intr.irq = irq; 205fcf5ef2aSThomas Huth } else { 206fcf5ef2aSThomas Huth intr.irq = -irq; 207fcf5ef2aSThomas Huth } 208fcf5ef2aSThomas Huth 209fcf5ef2aSThomas Huth kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 210fcf5ef2aSThomas Huth 211fcf5ef2aSThomas Huth return 0; 212fcf5ef2aSThomas Huth } 213fcf5ef2aSThomas Huth 214fcf5ef2aSThomas Huth int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) 215fcf5ef2aSThomas Huth { 216fcf5ef2aSThomas Huth CPUState *cs = current_cpu; 217fcf5ef2aSThomas Huth CPUState *dest_cs = CPU(cpu); 218fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 219fcf5ef2aSThomas Huth 22011cb076bSPhilippe Mathieu-Daudé assert(kvm_enabled()); 221fcf5ef2aSThomas Huth 222fcf5ef2aSThomas Huth intr.cpu = dest_cs->cpu_index; 223fcf5ef2aSThomas Huth 224fcf5ef2aSThomas Huth if (level) { 225fcf5ef2aSThomas Huth intr.irq = irq; 226fcf5ef2aSThomas Huth } else { 227fcf5ef2aSThomas Huth intr.irq = -irq; 228fcf5ef2aSThomas Huth } 229fcf5ef2aSThomas Huth 230fcf5ef2aSThomas Huth DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq); 231fcf5ef2aSThomas Huth 232fcf5ef2aSThomas Huth kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 233fcf5ef2aSThomas Huth 234fcf5ef2aSThomas Huth return 0; 235fcf5ef2aSThomas Huth } 236fcf5ef2aSThomas Huth 237fcf5ef2aSThomas Huth #define MIPS_CP0_32(_R, _S) \ 238fcf5ef2aSThomas Huth (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S))) 239fcf5ef2aSThomas Huth 240fcf5ef2aSThomas Huth #define MIPS_CP0_64(_R, _S) \ 241fcf5ef2aSThomas Huth (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) 242fcf5ef2aSThomas Huth 243fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) 2447e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_RANDOM MIPS_CP0_32(1, 0) 245fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) 246fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) 247fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) 2487e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) 2497e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5) 2507e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6) 2517e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7) 252fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) 2537e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6) 254fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) 255fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) 256fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) 257fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) 258fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) 259fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) 260fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) 261fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) 262fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) 2637e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) 264fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) 265fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) 266fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) 267fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) 268fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) 269fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) 2707e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_CONFIG6 MIPS_CP0_32(16, 6) 2717e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) 272fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) 2737e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2) 2747e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3) 2757e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4) 2767e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5) 2777e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6) 2787e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7) 279fcf5ef2aSThomas Huth 280fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, 281fcf5ef2aSThomas Huth int32_t *addr) 282fcf5ef2aSThomas Huth { 283fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 284fcf5ef2aSThomas Huth .id = reg_id, 285fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 286fcf5ef2aSThomas Huth }; 287fcf5ef2aSThomas Huth 288fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 289fcf5ef2aSThomas Huth } 290fcf5ef2aSThomas Huth 291fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ureg(CPUState *cs, uint64_t reg_id, 292fcf5ef2aSThomas Huth uint32_t *addr) 293fcf5ef2aSThomas Huth { 294fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 295fcf5ef2aSThomas Huth .id = reg_id, 296fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 297fcf5ef2aSThomas Huth }; 298fcf5ef2aSThomas Huth 299fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 300fcf5ef2aSThomas Huth } 301fcf5ef2aSThomas Huth 302fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id, 303fcf5ef2aSThomas Huth target_ulong *addr) 304fcf5ef2aSThomas Huth { 305fcf5ef2aSThomas Huth uint64_t val64 = *addr; 306fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 307fcf5ef2aSThomas Huth .id = reg_id, 308fcf5ef2aSThomas Huth .addr = (uintptr_t)&val64 309fcf5ef2aSThomas Huth }; 310fcf5ef2aSThomas Huth 311fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 312fcf5ef2aSThomas Huth } 313fcf5ef2aSThomas Huth 314fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id, 315fcf5ef2aSThomas Huth int64_t *addr) 316fcf5ef2aSThomas Huth { 317fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 318fcf5ef2aSThomas Huth .id = reg_id, 319fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 320fcf5ef2aSThomas Huth }; 321fcf5ef2aSThomas Huth 322fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 323fcf5ef2aSThomas Huth } 324fcf5ef2aSThomas Huth 325fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ureg64(CPUState *cs, uint64_t reg_id, 326fcf5ef2aSThomas Huth uint64_t *addr) 327fcf5ef2aSThomas Huth { 328fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 329fcf5ef2aSThomas Huth .id = reg_id, 330fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 331fcf5ef2aSThomas Huth }; 332fcf5ef2aSThomas Huth 333fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 334fcf5ef2aSThomas Huth } 335fcf5ef2aSThomas Huth 336fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id, 337fcf5ef2aSThomas Huth int32_t *addr) 338fcf5ef2aSThomas Huth { 339fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 340fcf5ef2aSThomas Huth .id = reg_id, 341fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 342fcf5ef2aSThomas Huth }; 343fcf5ef2aSThomas Huth 344fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 345fcf5ef2aSThomas Huth } 346fcf5ef2aSThomas Huth 347fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ureg(CPUState *cs, uint64_t reg_id, 348fcf5ef2aSThomas Huth uint32_t *addr) 349fcf5ef2aSThomas Huth { 350fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 351fcf5ef2aSThomas Huth .id = reg_id, 352fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 353fcf5ef2aSThomas Huth }; 354fcf5ef2aSThomas Huth 355fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 356fcf5ef2aSThomas Huth } 357fcf5ef2aSThomas Huth 358fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64_t reg_id, 359fcf5ef2aSThomas Huth target_ulong *addr) 360fcf5ef2aSThomas Huth { 361fcf5ef2aSThomas Huth int ret; 362fcf5ef2aSThomas Huth uint64_t val64 = 0; 363fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 364fcf5ef2aSThomas Huth .id = reg_id, 365fcf5ef2aSThomas Huth .addr = (uintptr_t)&val64 366fcf5ef2aSThomas Huth }; 367fcf5ef2aSThomas Huth 368fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 369fcf5ef2aSThomas Huth if (ret >= 0) { 370fcf5ef2aSThomas Huth *addr = val64; 371fcf5ef2aSThomas Huth } 372fcf5ef2aSThomas Huth return ret; 373fcf5ef2aSThomas Huth } 374fcf5ef2aSThomas Huth 375fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64_t reg_id, 376fcf5ef2aSThomas Huth int64_t *addr) 377fcf5ef2aSThomas Huth { 378fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 379fcf5ef2aSThomas Huth .id = reg_id, 380fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 381fcf5ef2aSThomas Huth }; 382fcf5ef2aSThomas Huth 383fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 384fcf5ef2aSThomas Huth } 385fcf5ef2aSThomas Huth 386fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ureg64(CPUState *cs, uint64_t reg_id, 387fcf5ef2aSThomas Huth uint64_t *addr) 388fcf5ef2aSThomas Huth { 389fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 390fcf5ef2aSThomas Huth .id = reg_id, 391fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 392fcf5ef2aSThomas Huth }; 393fcf5ef2aSThomas Huth 394fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 395fcf5ef2aSThomas Huth } 396fcf5ef2aSThomas Huth 397fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M) 398fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG1_MASK ((1U << CP0C1_M) | \ 399fcf5ef2aSThomas Huth (1U << CP0C1_FP)) 400fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG2_MASK (1U << CP0C2_M) 401fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG3_MASK ((1U << CP0C3_M) | \ 402fcf5ef2aSThomas Huth (1U << CP0C3_MSAP)) 403fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG4_MASK (1U << CP0C4_M) 404fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG5_MASK ((1U << CP0C5_MSAEn) | \ 405fcf5ef2aSThomas Huth (1U << CP0C5_UFE) | \ 406fcf5ef2aSThomas Huth (1U << CP0C5_FRE) | \ 407fcf5ef2aSThomas Huth (1U << CP0C5_UFR)) 4087e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ 4097e0896b0SHuacai Chen (0x3fU << CP0C6_KPOS) | \ 4107e0896b0SHuacai Chen (1U << CP0C6_KE) | \ 4117e0896b0SHuacai Chen (1U << CP0C6_VTLBONLY) | \ 4127e0896b0SHuacai Chen (1U << CP0C6_LASX) | \ 4137e0896b0SHuacai Chen (1U << CP0C6_SSEN) | \ 4147e0896b0SHuacai Chen (1U << CP0C6_DISDRTIME) | \ 4157e0896b0SHuacai Chen (1U << CP0C6_PIXNUEN) | \ 4167e0896b0SHuacai Chen (1U << CP0C6_SCRAND) | \ 4177e0896b0SHuacai Chen (1U << CP0C6_LLEXCEN) | \ 4187e0896b0SHuacai Chen (1U << CP0C6_DISVC) | \ 4197e0896b0SHuacai Chen (1U << CP0C6_VCLRU) | \ 4207e0896b0SHuacai Chen (1U << CP0C6_DCLRU) | \ 4217e0896b0SHuacai Chen (1U << CP0C6_PIXUEN) | \ 4227e0896b0SHuacai Chen (1U << CP0C6_DISBLKLYEN) | \ 4237e0896b0SHuacai Chen (1U << CP0C6_UMEMUALEN) | \ 4247e0896b0SHuacai Chen (1U << CP0C6_SFBEN) | \ 4257e0896b0SHuacai Chen (1U << CP0C6_FLTINT) | \ 4267e0896b0SHuacai Chen (1U << CP0C6_VLTINT) | \ 4277e0896b0SHuacai Chen (1U << CP0C6_DISBTB) | \ 4287e0896b0SHuacai Chen (3U << CP0C6_STPREFCTL) | \ 4297e0896b0SHuacai Chen (1U << CP0C6_INSTPREF) | \ 4307e0896b0SHuacai Chen (1U << CP0C6_DATAPREF)) 431fcf5ef2aSThomas Huth 432fcf5ef2aSThomas Huth static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id, 433fcf5ef2aSThomas Huth int32_t *addr, int32_t mask) 434fcf5ef2aSThomas Huth { 435fcf5ef2aSThomas Huth int err; 436fcf5ef2aSThomas Huth int32_t tmp, change; 437fcf5ef2aSThomas Huth 438fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, reg_id, &tmp); 439fcf5ef2aSThomas Huth if (err < 0) { 440fcf5ef2aSThomas Huth return err; 441fcf5ef2aSThomas Huth } 442fcf5ef2aSThomas Huth 443fcf5ef2aSThomas Huth /* only change bits in mask */ 444fcf5ef2aSThomas Huth change = (*addr ^ tmp) & mask; 445fcf5ef2aSThomas Huth if (!change) { 446fcf5ef2aSThomas Huth return 0; 447fcf5ef2aSThomas Huth } 448fcf5ef2aSThomas Huth 449fcf5ef2aSThomas Huth tmp = tmp ^ change; 450fcf5ef2aSThomas Huth return kvm_mips_put_one_reg(cs, reg_id, &tmp); 451fcf5ef2aSThomas Huth } 452fcf5ef2aSThomas Huth 453fcf5ef2aSThomas Huth /* 454fcf5ef2aSThomas Huth * We freeze the KVM timer when either the VM clock is stopped or the state is 455fcf5ef2aSThomas Huth * saved (the state is dirty). 456fcf5ef2aSThomas Huth */ 457fcf5ef2aSThomas Huth 458fcf5ef2aSThomas Huth /* 459fcf5ef2aSThomas Huth * Save the state of the KVM timer when VM clock is stopped or state is synced 460fcf5ef2aSThomas Huth * to QEMU. 461fcf5ef2aSThomas Huth */ 462fcf5ef2aSThomas Huth static int kvm_mips_save_count(CPUState *cs) 463fcf5ef2aSThomas Huth { 464fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 465fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 466fcf5ef2aSThomas Huth uint64_t count_ctl; 467fcf5ef2aSThomas Huth int err, ret = 0; 468fcf5ef2aSThomas Huth 469fcf5ef2aSThomas Huth /* freeze KVM timer */ 470fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 471fcf5ef2aSThomas Huth if (err < 0) { 472fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err); 473fcf5ef2aSThomas Huth ret = err; 474fcf5ef2aSThomas Huth } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) { 475fcf5ef2aSThomas Huth count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC; 476fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 477fcf5ef2aSThomas Huth if (err < 0) { 478fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err); 479fcf5ef2aSThomas Huth ret = err; 480fcf5ef2aSThomas Huth } 481fcf5ef2aSThomas Huth } 482fcf5ef2aSThomas Huth 483fcf5ef2aSThomas Huth /* read CP0_Cause */ 484fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause); 485fcf5ef2aSThomas Huth if (err < 0) { 486fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err); 487fcf5ef2aSThomas Huth ret = err; 488fcf5ef2aSThomas Huth } 489fcf5ef2aSThomas Huth 490fcf5ef2aSThomas Huth /* read CP0_Count */ 491fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count); 492fcf5ef2aSThomas Huth if (err < 0) { 493fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err); 494fcf5ef2aSThomas Huth ret = err; 495fcf5ef2aSThomas Huth } 496fcf5ef2aSThomas Huth 497fcf5ef2aSThomas Huth return ret; 498fcf5ef2aSThomas Huth } 499fcf5ef2aSThomas Huth 500fcf5ef2aSThomas Huth /* 501fcf5ef2aSThomas Huth * Restore the state of the KVM timer when VM clock is restarted or state is 502fcf5ef2aSThomas Huth * synced to KVM. 503fcf5ef2aSThomas Huth */ 504fcf5ef2aSThomas Huth static int kvm_mips_restore_count(CPUState *cs) 505fcf5ef2aSThomas Huth { 506fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 507fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 508fcf5ef2aSThomas Huth uint64_t count_ctl; 509fcf5ef2aSThomas Huth int err_dc, err, ret = 0; 510fcf5ef2aSThomas Huth 511fcf5ef2aSThomas Huth /* check the timer is frozen */ 512fcf5ef2aSThomas Huth err_dc = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 513fcf5ef2aSThomas Huth if (err_dc < 0) { 514fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc); 515fcf5ef2aSThomas Huth ret = err_dc; 516fcf5ef2aSThomas Huth } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) { 517fcf5ef2aSThomas Huth /* freeze timer (sets COUNT_RESUME for us) */ 518fcf5ef2aSThomas Huth count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC; 519fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 520fcf5ef2aSThomas Huth if (err < 0) { 521fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err); 522fcf5ef2aSThomas Huth ret = err; 523fcf5ef2aSThomas Huth } 524fcf5ef2aSThomas Huth } 525fcf5ef2aSThomas Huth 526fcf5ef2aSThomas Huth /* load CP0_Cause */ 527fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause); 528fcf5ef2aSThomas Huth if (err < 0) { 529fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err); 530fcf5ef2aSThomas Huth ret = err; 531fcf5ef2aSThomas Huth } 532fcf5ef2aSThomas Huth 533fcf5ef2aSThomas Huth /* load CP0_Count */ 534fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count); 535fcf5ef2aSThomas Huth if (err < 0) { 536fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err); 537fcf5ef2aSThomas Huth ret = err; 538fcf5ef2aSThomas Huth } 539fcf5ef2aSThomas Huth 540fcf5ef2aSThomas Huth /* resume KVM timer */ 541fcf5ef2aSThomas Huth if (err_dc >= 0) { 542fcf5ef2aSThomas Huth count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC; 543fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 544fcf5ef2aSThomas Huth if (err < 0) { 545fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err); 546fcf5ef2aSThomas Huth ret = err; 547fcf5ef2aSThomas Huth } 548fcf5ef2aSThomas Huth } 549fcf5ef2aSThomas Huth 550fcf5ef2aSThomas Huth return ret; 551fcf5ef2aSThomas Huth } 552fcf5ef2aSThomas Huth 553fcf5ef2aSThomas Huth /* 554fcf5ef2aSThomas Huth * Handle the VM clock being started or stopped 555fcf5ef2aSThomas Huth */ 556*538f0497SPhilippe Mathieu-Daudé static void kvm_mips_update_state(void *opaque, bool running, RunState state) 557fcf5ef2aSThomas Huth { 558fcf5ef2aSThomas Huth CPUState *cs = opaque; 559fcf5ef2aSThomas Huth int ret; 560fcf5ef2aSThomas Huth uint64_t count_resume; 561fcf5ef2aSThomas Huth 562fcf5ef2aSThomas Huth /* 563fcf5ef2aSThomas Huth * If state is already dirty (synced to QEMU) then the KVM timer state is 564fcf5ef2aSThomas Huth * already saved and can be restored when it is synced back to KVM. 565fcf5ef2aSThomas Huth */ 566fcf5ef2aSThomas Huth if (!running) { 56799f31832SSergio Andres Gomez Del Real if (!cs->vcpu_dirty) { 568fcf5ef2aSThomas Huth ret = kvm_mips_save_count(cs); 569fcf5ef2aSThomas Huth if (ret < 0) { 570288cb949SAlistair Francis warn_report("Failed saving count"); 571fcf5ef2aSThomas Huth } 572fcf5ef2aSThomas Huth } 573fcf5ef2aSThomas Huth } else { 574fcf5ef2aSThomas Huth /* Set clock restore time to now */ 575fcf5ef2aSThomas Huth count_resume = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 576fcf5ef2aSThomas Huth ret = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_RESUME, 577fcf5ef2aSThomas Huth &count_resume); 578fcf5ef2aSThomas Huth if (ret < 0) { 579288cb949SAlistair Francis warn_report("Failed setting COUNT_RESUME"); 580fcf5ef2aSThomas Huth return; 581fcf5ef2aSThomas Huth } 582fcf5ef2aSThomas Huth 58399f31832SSergio Andres Gomez Del Real if (!cs->vcpu_dirty) { 584fcf5ef2aSThomas Huth ret = kvm_mips_restore_count(cs); 585fcf5ef2aSThomas Huth if (ret < 0) { 586288cb949SAlistair Francis warn_report("Failed restoring count"); 587fcf5ef2aSThomas Huth } 588fcf5ef2aSThomas Huth } 589fcf5ef2aSThomas Huth } 590fcf5ef2aSThomas Huth } 591fcf5ef2aSThomas Huth 592fcf5ef2aSThomas Huth static int kvm_mips_put_fpu_registers(CPUState *cs, int level) 593fcf5ef2aSThomas Huth { 594fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 595fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 596fcf5ef2aSThomas Huth int err, ret = 0; 597fcf5ef2aSThomas Huth unsigned int i; 598fcf5ef2aSThomas Huth 599fcf5ef2aSThomas Huth /* Only put FPU state if we're emulating a CPU with an FPU */ 600fcf5ef2aSThomas Huth if (env->CP0_Config1 & (1 << CP0C1_FP)) { 601fcf5ef2aSThomas Huth /* FPU Control Registers */ 602fcf5ef2aSThomas Huth if (level == KVM_PUT_FULL_STATE) { 603fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg(cs, KVM_REG_MIPS_FCR_IR, 604fcf5ef2aSThomas Huth &env->active_fpu.fcr0); 605fcf5ef2aSThomas Huth if (err < 0) { 606fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FCR_IR (%d)\n", __func__, err); 607fcf5ef2aSThomas Huth ret = err; 608fcf5ef2aSThomas Huth } 609fcf5ef2aSThomas Huth } 610fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg(cs, KVM_REG_MIPS_FCR_CSR, 611fcf5ef2aSThomas Huth &env->active_fpu.fcr31); 612fcf5ef2aSThomas Huth if (err < 0) { 613fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FCR_CSR (%d)\n", __func__, err); 614fcf5ef2aSThomas Huth ret = err; 615fcf5ef2aSThomas Huth } 616fcf5ef2aSThomas Huth 617fcf5ef2aSThomas Huth /* 618fcf5ef2aSThomas Huth * FPU register state is a subset of MSA vector state, so don't put FPU 619fcf5ef2aSThomas Huth * registers if we're emulating a CPU with MSA. 620fcf5ef2aSThomas Huth */ 62125a13628SPhilippe Mathieu-Daudé if (!ase_msa_available(env)) { 622fcf5ef2aSThomas Huth /* Floating point registers */ 623fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 624fcf5ef2aSThomas Huth if (env->CP0_Status & (1 << CP0St_FR)) { 625fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i), 626fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].d); 627fcf5ef2aSThomas Huth } else { 628fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i), 629fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); 630fcf5ef2aSThomas Huth } 631fcf5ef2aSThomas Huth if (err < 0) { 632fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FPR%u (%d)\n", __func__, i, err); 633fcf5ef2aSThomas Huth ret = err; 634fcf5ef2aSThomas Huth } 635fcf5ef2aSThomas Huth } 636fcf5ef2aSThomas Huth } 637fcf5ef2aSThomas Huth } 638fcf5ef2aSThomas Huth 639fcf5ef2aSThomas Huth /* Only put MSA state if we're emulating a CPU with MSA */ 64025a13628SPhilippe Mathieu-Daudé if (ase_msa_available(env)) { 641fcf5ef2aSThomas Huth /* MSA Control Registers */ 642fcf5ef2aSThomas Huth if (level == KVM_PUT_FULL_STATE) { 643fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_IR, 644fcf5ef2aSThomas Huth &env->msair); 645fcf5ef2aSThomas Huth if (err < 0) { 646fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put MSA_IR (%d)\n", __func__, err); 647fcf5ef2aSThomas Huth ret = err; 648fcf5ef2aSThomas Huth } 649fcf5ef2aSThomas Huth } 650fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_CSR, 651fcf5ef2aSThomas Huth &env->active_tc.msacsr); 652fcf5ef2aSThomas Huth if (err < 0) { 653fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put MSA_CSR (%d)\n", __func__, err); 654fcf5ef2aSThomas Huth ret = err; 655fcf5ef2aSThomas Huth } 656fcf5ef2aSThomas Huth 657fcf5ef2aSThomas Huth /* Vector registers (includes FP registers) */ 658fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 659fcf5ef2aSThomas Huth /* Big endian MSA not supported by QEMU yet anyway */ 660fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_VEC_128(i), 661fcf5ef2aSThomas Huth env->active_fpu.fpr[i].wr.d); 662fcf5ef2aSThomas Huth if (err < 0) { 663fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put VEC%u (%d)\n", __func__, i, err); 664fcf5ef2aSThomas Huth ret = err; 665fcf5ef2aSThomas Huth } 666fcf5ef2aSThomas Huth } 667fcf5ef2aSThomas Huth } 668fcf5ef2aSThomas Huth 669fcf5ef2aSThomas Huth return ret; 670fcf5ef2aSThomas Huth } 671fcf5ef2aSThomas Huth 672fcf5ef2aSThomas Huth static int kvm_mips_get_fpu_registers(CPUState *cs) 673fcf5ef2aSThomas Huth { 674fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 675fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 676fcf5ef2aSThomas Huth int err, ret = 0; 677fcf5ef2aSThomas Huth unsigned int i; 678fcf5ef2aSThomas Huth 679fcf5ef2aSThomas Huth /* Only get FPU state if we're emulating a CPU with an FPU */ 680fcf5ef2aSThomas Huth if (env->CP0_Config1 & (1 << CP0C1_FP)) { 681fcf5ef2aSThomas Huth /* FPU Control Registers */ 682fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_IR, 683fcf5ef2aSThomas Huth &env->active_fpu.fcr0); 684fcf5ef2aSThomas Huth if (err < 0) { 685fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FCR_IR (%d)\n", __func__, err); 686fcf5ef2aSThomas Huth ret = err; 687fcf5ef2aSThomas Huth } 688fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_CSR, 689fcf5ef2aSThomas Huth &env->active_fpu.fcr31); 690fcf5ef2aSThomas Huth if (err < 0) { 691fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FCR_CSR (%d)\n", __func__, err); 692fcf5ef2aSThomas Huth ret = err; 693fcf5ef2aSThomas Huth } else { 694fcf5ef2aSThomas Huth restore_fp_status(env); 695fcf5ef2aSThomas Huth } 696fcf5ef2aSThomas Huth 697fcf5ef2aSThomas Huth /* 698fcf5ef2aSThomas Huth * FPU register state is a subset of MSA vector state, so don't save FPU 699fcf5ef2aSThomas Huth * registers if we're emulating a CPU with MSA. 700fcf5ef2aSThomas Huth */ 70125a13628SPhilippe Mathieu-Daudé if (!ase_msa_available(env)) { 702fcf5ef2aSThomas Huth /* Floating point registers */ 703fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 704fcf5ef2aSThomas Huth if (env->CP0_Status & (1 << CP0St_FR)) { 705fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i), 706fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].d); 707fcf5ef2aSThomas Huth } else { 708fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i), 709fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); 710fcf5ef2aSThomas Huth } 711fcf5ef2aSThomas Huth if (err < 0) { 712fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__, i, err); 713fcf5ef2aSThomas Huth ret = err; 714fcf5ef2aSThomas Huth } 715fcf5ef2aSThomas Huth } 716fcf5ef2aSThomas Huth } 717fcf5ef2aSThomas Huth } 718fcf5ef2aSThomas Huth 719fcf5ef2aSThomas Huth /* Only get MSA state if we're emulating a CPU with MSA */ 72025a13628SPhilippe Mathieu-Daudé if (ase_msa_available(env)) { 721fcf5ef2aSThomas Huth /* MSA Control Registers */ 722fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR, 723fcf5ef2aSThomas Huth &env->msair); 724fcf5ef2aSThomas Huth if (err < 0) { 725fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get MSA_IR (%d)\n", __func__, err); 726fcf5ef2aSThomas Huth ret = err; 727fcf5ef2aSThomas Huth } 728fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_CSR, 729fcf5ef2aSThomas Huth &env->active_tc.msacsr); 730fcf5ef2aSThomas Huth if (err < 0) { 731fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get MSA_CSR (%d)\n", __func__, err); 732fcf5ef2aSThomas Huth ret = err; 733fcf5ef2aSThomas Huth } else { 734fcf5ef2aSThomas Huth restore_msa_fp_status(env); 735fcf5ef2aSThomas Huth } 736fcf5ef2aSThomas Huth 737fcf5ef2aSThomas Huth /* Vector registers (includes FP registers) */ 738fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 739fcf5ef2aSThomas Huth /* Big endian MSA not supported by QEMU yet anyway */ 740fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_VEC_128(i), 741fcf5ef2aSThomas Huth env->active_fpu.fpr[i].wr.d); 742fcf5ef2aSThomas Huth if (err < 0) { 743fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get VEC%u (%d)\n", __func__, i, err); 744fcf5ef2aSThomas Huth ret = err; 745fcf5ef2aSThomas Huth } 746fcf5ef2aSThomas Huth } 747fcf5ef2aSThomas Huth } 748fcf5ef2aSThomas Huth 749fcf5ef2aSThomas Huth return ret; 750fcf5ef2aSThomas Huth } 751fcf5ef2aSThomas Huth 752fcf5ef2aSThomas Huth 753fcf5ef2aSThomas Huth static int kvm_mips_put_cp0_registers(CPUState *cs, int level) 754fcf5ef2aSThomas Huth { 755fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 756fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 757fcf5ef2aSThomas Huth int err, ret = 0; 758fcf5ef2aSThomas Huth 759fcf5ef2aSThomas Huth (void)level; 760fcf5ef2aSThomas Huth 761fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); 762fcf5ef2aSThomas Huth if (err < 0) { 763fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err); 764fcf5ef2aSThomas Huth ret = err; 765fcf5ef2aSThomas Huth } 7667e0896b0SHuacai Chen err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_RANDOM, &env->CP0_Random); 7677e0896b0SHuacai Chen if (err < 0) { 7687e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_RANDOM (%d)\n", __func__, err); 7697e0896b0SHuacai Chen ret = err; 7707e0896b0SHuacai Chen } 771fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, 772fcf5ef2aSThomas Huth &env->CP0_Context); 773fcf5ef2aSThomas Huth if (err < 0) { 774fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err); 775fcf5ef2aSThomas Huth ret = err; 776fcf5ef2aSThomas Huth } 777fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL, 778fcf5ef2aSThomas Huth &env->active_tc.CP0_UserLocal); 779fcf5ef2aSThomas Huth if (err < 0) { 780fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err); 781fcf5ef2aSThomas Huth ret = err; 782fcf5ef2aSThomas Huth } 783fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK, 784fcf5ef2aSThomas Huth &env->CP0_PageMask); 785fcf5ef2aSThomas Huth if (err < 0) { 786fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err); 787fcf5ef2aSThomas Huth ret = err; 788fcf5ef2aSThomas Huth } 7897e0896b0SHuacai Chen err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEGRAIN, 7907e0896b0SHuacai Chen &env->CP0_PageGrain); 7917e0896b0SHuacai Chen if (err < 0) { 7927e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_PAGEGRAIN (%d)\n", __func__, err); 7937e0896b0SHuacai Chen ret = err; 7947e0896b0SHuacai Chen } 7957e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWBASE, 7967e0896b0SHuacai Chen &env->CP0_PWBase); 7977e0896b0SHuacai Chen if (err < 0) { 7987e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_PWBASE (%d)\n", __func__, err); 7997e0896b0SHuacai Chen ret = err; 8007e0896b0SHuacai Chen } 8017e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWFIELD, 8027e0896b0SHuacai Chen &env->CP0_PWField); 8037e0896b0SHuacai Chen if (err < 0) { 8047e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_PWField (%d)\n", __func__, err); 8057e0896b0SHuacai Chen ret = err; 8067e0896b0SHuacai Chen } 8077e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWSIZE, 8087e0896b0SHuacai Chen &env->CP0_PWSize); 8097e0896b0SHuacai Chen if (err < 0) { 8107e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_PWSIZE (%d)\n", __func__, err); 8117e0896b0SHuacai Chen ret = err; 8127e0896b0SHuacai Chen } 813fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); 814fcf5ef2aSThomas Huth if (err < 0) { 815fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err); 816fcf5ef2aSThomas Huth ret = err; 817fcf5ef2aSThomas Huth } 8187e0896b0SHuacai Chen err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PWCTL, &env->CP0_PWCtl); 8197e0896b0SHuacai Chen if (err < 0) { 8207e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_PWCTL (%d)\n", __func__, err); 8217e0896b0SHuacai Chen ret = err; 8227e0896b0SHuacai Chen } 823fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); 824fcf5ef2aSThomas Huth if (err < 0) { 825fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err); 826fcf5ef2aSThomas Huth ret = err; 827fcf5ef2aSThomas Huth } 828fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR, 829fcf5ef2aSThomas Huth &env->CP0_BadVAddr); 830fcf5ef2aSThomas Huth if (err < 0) { 831fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err); 832fcf5ef2aSThomas Huth ret = err; 833fcf5ef2aSThomas Huth } 834fcf5ef2aSThomas Huth 835fcf5ef2aSThomas Huth /* If VM clock stopped then state will be restored when it is restarted */ 836fcf5ef2aSThomas Huth if (runstate_is_running()) { 837fcf5ef2aSThomas Huth err = kvm_mips_restore_count(cs); 838fcf5ef2aSThomas Huth if (err < 0) { 839fcf5ef2aSThomas Huth ret = err; 840fcf5ef2aSThomas Huth } 841fcf5ef2aSThomas Huth } 842fcf5ef2aSThomas Huth 843fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI, 844fcf5ef2aSThomas Huth &env->CP0_EntryHi); 845fcf5ef2aSThomas Huth if (err < 0) { 846fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err); 847fcf5ef2aSThomas Huth ret = err; 848fcf5ef2aSThomas Huth } 849fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE, 850fcf5ef2aSThomas Huth &env->CP0_Compare); 851fcf5ef2aSThomas Huth if (err < 0) { 852fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err); 853fcf5ef2aSThomas Huth ret = err; 854fcf5ef2aSThomas Huth } 855fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status); 856fcf5ef2aSThomas Huth if (err < 0) { 857fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err); 858fcf5ef2aSThomas Huth ret = err; 859fcf5ef2aSThomas Huth } 860fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC); 861fcf5ef2aSThomas Huth if (err < 0) { 862fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err); 863fcf5ef2aSThomas Huth ret = err; 864fcf5ef2aSThomas Huth } 865fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); 866fcf5ef2aSThomas Huth if (err < 0) { 867fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err); 868fcf5ef2aSThomas Huth ret = err; 869fcf5ef2aSThomas Huth } 8707e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EBASE, &env->CP0_EBase); 8717e0896b0SHuacai Chen if (err < 0) { 8727e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_EBASE (%d)\n", __func__, err); 8737e0896b0SHuacai Chen ret = err; 8747e0896b0SHuacai Chen } 875fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, 876fcf5ef2aSThomas Huth &env->CP0_Config0, 877fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG_MASK); 878fcf5ef2aSThomas Huth if (err < 0) { 879fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG (%d)\n", __func__, err); 880fcf5ef2aSThomas Huth ret = err; 881fcf5ef2aSThomas Huth } 882fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, 883fcf5ef2aSThomas Huth &env->CP0_Config1, 884fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG1_MASK); 885fcf5ef2aSThomas Huth if (err < 0) { 886fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG1 (%d)\n", __func__, err); 887fcf5ef2aSThomas Huth ret = err; 888fcf5ef2aSThomas Huth } 889fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2, 890fcf5ef2aSThomas Huth &env->CP0_Config2, 891fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG2_MASK); 892fcf5ef2aSThomas Huth if (err < 0) { 893fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG2 (%d)\n", __func__, err); 894fcf5ef2aSThomas Huth ret = err; 895fcf5ef2aSThomas Huth } 896fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3, 897fcf5ef2aSThomas Huth &env->CP0_Config3, 898fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG3_MASK); 899fcf5ef2aSThomas Huth if (err < 0) { 900fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG3 (%d)\n", __func__, err); 901fcf5ef2aSThomas Huth ret = err; 902fcf5ef2aSThomas Huth } 903fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4, 904fcf5ef2aSThomas Huth &env->CP0_Config4, 905fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG4_MASK); 906fcf5ef2aSThomas Huth if (err < 0) { 907fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG4 (%d)\n", __func__, err); 908fcf5ef2aSThomas Huth ret = err; 909fcf5ef2aSThomas Huth } 910fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, 911fcf5ef2aSThomas Huth &env->CP0_Config5, 912fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG5_MASK); 913fcf5ef2aSThomas Huth if (err < 0) { 914fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG5 (%d)\n", __func__, err); 915fcf5ef2aSThomas Huth ret = err; 916fcf5ef2aSThomas Huth } 9177e0896b0SHuacai Chen err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG6, 9187e0896b0SHuacai Chen &env->CP0_Config6, 9197e0896b0SHuacai Chen KVM_REG_MIPS_CP0_CONFIG6_MASK); 9207e0896b0SHuacai Chen if (err < 0) { 9217e0896b0SHuacai Chen DPRINTF("%s: Failed to change CP0_CONFIG6 (%d)\n", __func__, err); 9227e0896b0SHuacai Chen ret = err; 9237e0896b0SHuacai Chen } 9247e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_XCONTEXT, 9257e0896b0SHuacai Chen &env->CP0_XContext); 9267e0896b0SHuacai Chen if (err < 0) { 9277e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_XCONTEXT (%d)\n", __func__, err); 9287e0896b0SHuacai Chen ret = err; 9297e0896b0SHuacai Chen } 930fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, 931fcf5ef2aSThomas Huth &env->CP0_ErrorEPC); 932fcf5ef2aSThomas Huth if (err < 0) { 933fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err); 934fcf5ef2aSThomas Huth ret = err; 935fcf5ef2aSThomas Huth } 9367e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH1, 9377e0896b0SHuacai Chen &env->CP0_KScratch[0]); 9387e0896b0SHuacai Chen if (err < 0) { 9397e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH1 (%d)\n", __func__, err); 9407e0896b0SHuacai Chen ret = err; 9417e0896b0SHuacai Chen } 9427e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH2, 9437e0896b0SHuacai Chen &env->CP0_KScratch[1]); 9447e0896b0SHuacai Chen if (err < 0) { 9457e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH2 (%d)\n", __func__, err); 9467e0896b0SHuacai Chen ret = err; 9477e0896b0SHuacai Chen } 9487e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH3, 9497e0896b0SHuacai Chen &env->CP0_KScratch[2]); 9507e0896b0SHuacai Chen if (err < 0) { 9517e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH3 (%d)\n", __func__, err); 9527e0896b0SHuacai Chen ret = err; 9537e0896b0SHuacai Chen } 9547e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH4, 9557e0896b0SHuacai Chen &env->CP0_KScratch[3]); 9567e0896b0SHuacai Chen if (err < 0) { 9577e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH4 (%d)\n", __func__, err); 9587e0896b0SHuacai Chen ret = err; 9597e0896b0SHuacai Chen } 9607e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH5, 9617e0896b0SHuacai Chen &env->CP0_KScratch[4]); 9627e0896b0SHuacai Chen if (err < 0) { 9637e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH5 (%d)\n", __func__, err); 9647e0896b0SHuacai Chen ret = err; 9657e0896b0SHuacai Chen } 9667e0896b0SHuacai Chen err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH6, 9677e0896b0SHuacai Chen &env->CP0_KScratch[5]); 9687e0896b0SHuacai Chen if (err < 0) { 9697e0896b0SHuacai Chen DPRINTF("%s: Failed to put CP0_KSCRATCH6 (%d)\n", __func__, err); 9707e0896b0SHuacai Chen ret = err; 9717e0896b0SHuacai Chen } 972fcf5ef2aSThomas Huth 973fcf5ef2aSThomas Huth return ret; 974fcf5ef2aSThomas Huth } 975fcf5ef2aSThomas Huth 976fcf5ef2aSThomas Huth static int kvm_mips_get_cp0_registers(CPUState *cs) 977fcf5ef2aSThomas Huth { 978fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 979fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 980fcf5ef2aSThomas Huth int err, ret = 0; 981fcf5ef2aSThomas Huth 982fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); 983fcf5ef2aSThomas Huth if (err < 0) { 984fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err); 985fcf5ef2aSThomas Huth ret = err; 986fcf5ef2aSThomas Huth } 9877e0896b0SHuacai Chen err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_RANDOM, &env->CP0_Random); 9887e0896b0SHuacai Chen if (err < 0) { 9897e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_RANDOM (%d)\n", __func__, err); 9907e0896b0SHuacai Chen ret = err; 9917e0896b0SHuacai Chen } 992fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, 993fcf5ef2aSThomas Huth &env->CP0_Context); 994fcf5ef2aSThomas Huth if (err < 0) { 995fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err); 996fcf5ef2aSThomas Huth ret = err; 997fcf5ef2aSThomas Huth } 998fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL, 999fcf5ef2aSThomas Huth &env->active_tc.CP0_UserLocal); 1000fcf5ef2aSThomas Huth if (err < 0) { 1001fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err); 1002fcf5ef2aSThomas Huth ret = err; 1003fcf5ef2aSThomas Huth } 1004fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK, 1005fcf5ef2aSThomas Huth &env->CP0_PageMask); 1006fcf5ef2aSThomas Huth if (err < 0) { 1007fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err); 1008fcf5ef2aSThomas Huth ret = err; 1009fcf5ef2aSThomas Huth } 10107e0896b0SHuacai Chen err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEGRAIN, 10117e0896b0SHuacai Chen &env->CP0_PageGrain); 10127e0896b0SHuacai Chen if (err < 0) { 10137e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_PAGEGRAIN (%d)\n", __func__, err); 10147e0896b0SHuacai Chen ret = err; 10157e0896b0SHuacai Chen } 10167e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWBASE, 10177e0896b0SHuacai Chen &env->CP0_PWBase); 10187e0896b0SHuacai Chen if (err < 0) { 10197e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_PWBASE (%d)\n", __func__, err); 10207e0896b0SHuacai Chen ret = err; 10217e0896b0SHuacai Chen } 10227e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWFIELD, 10237e0896b0SHuacai Chen &env->CP0_PWField); 10247e0896b0SHuacai Chen if (err < 0) { 10257e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_PWFIELD (%d)\n", __func__, err); 10267e0896b0SHuacai Chen ret = err; 10277e0896b0SHuacai Chen } 10287e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWSIZE, 10297e0896b0SHuacai Chen &env->CP0_PWSize); 10307e0896b0SHuacai Chen if (err < 0) { 10317e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_PWSIZE (%d)\n", __func__, err); 10327e0896b0SHuacai Chen ret = err; 10337e0896b0SHuacai Chen } 1034fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); 1035fcf5ef2aSThomas Huth if (err < 0) { 1036fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err); 1037fcf5ef2aSThomas Huth ret = err; 1038fcf5ef2aSThomas Huth } 10397e0896b0SHuacai Chen err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PWCTL, &env->CP0_PWCtl); 10407e0896b0SHuacai Chen if (err < 0) { 10417e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_PWCtl (%d)\n", __func__, err); 10427e0896b0SHuacai Chen ret = err; 10437e0896b0SHuacai Chen } 1044fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); 1045fcf5ef2aSThomas Huth if (err < 0) { 1046fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err); 1047fcf5ef2aSThomas Huth ret = err; 1048fcf5ef2aSThomas Huth } 1049fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR, 1050fcf5ef2aSThomas Huth &env->CP0_BadVAddr); 1051fcf5ef2aSThomas Huth if (err < 0) { 1052fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err); 1053fcf5ef2aSThomas Huth ret = err; 1054fcf5ef2aSThomas Huth } 1055fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI, 1056fcf5ef2aSThomas Huth &env->CP0_EntryHi); 1057fcf5ef2aSThomas Huth if (err < 0) { 1058fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err); 1059fcf5ef2aSThomas Huth ret = err; 1060fcf5ef2aSThomas Huth } 1061fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE, 1062fcf5ef2aSThomas Huth &env->CP0_Compare); 1063fcf5ef2aSThomas Huth if (err < 0) { 1064fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err); 1065fcf5ef2aSThomas Huth ret = err; 1066fcf5ef2aSThomas Huth } 1067fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status); 1068fcf5ef2aSThomas Huth if (err < 0) { 1069fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err); 1070fcf5ef2aSThomas Huth ret = err; 1071fcf5ef2aSThomas Huth } 1072fcf5ef2aSThomas Huth 1073fcf5ef2aSThomas Huth /* If VM clock stopped then state was already saved when it was stopped */ 1074fcf5ef2aSThomas Huth if (runstate_is_running()) { 1075fcf5ef2aSThomas Huth err = kvm_mips_save_count(cs); 1076fcf5ef2aSThomas Huth if (err < 0) { 1077fcf5ef2aSThomas Huth ret = err; 1078fcf5ef2aSThomas Huth } 1079fcf5ef2aSThomas Huth } 1080fcf5ef2aSThomas Huth 1081fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC); 1082fcf5ef2aSThomas Huth if (err < 0) { 1083fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err); 1084fcf5ef2aSThomas Huth ret = err; 1085fcf5ef2aSThomas Huth } 1086fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); 1087fcf5ef2aSThomas Huth if (err < 0) { 1088fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err); 1089fcf5ef2aSThomas Huth ret = err; 1090fcf5ef2aSThomas Huth } 10917e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EBASE, &env->CP0_EBase); 10927e0896b0SHuacai Chen if (err < 0) { 10937e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_EBASE (%d)\n", __func__, err); 10947e0896b0SHuacai Chen ret = err; 10957e0896b0SHuacai Chen } 1096fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, &env->CP0_Config0); 1097fcf5ef2aSThomas Huth if (err < 0) { 1098fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG (%d)\n", __func__, err); 1099fcf5ef2aSThomas Huth ret = err; 1100fcf5ef2aSThomas Huth } 1101fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, &env->CP0_Config1); 1102fcf5ef2aSThomas Huth if (err < 0) { 1103fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG1 (%d)\n", __func__, err); 1104fcf5ef2aSThomas Huth ret = err; 1105fcf5ef2aSThomas Huth } 1106fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2, &env->CP0_Config2); 1107fcf5ef2aSThomas Huth if (err < 0) { 1108fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG2 (%d)\n", __func__, err); 1109fcf5ef2aSThomas Huth ret = err; 1110fcf5ef2aSThomas Huth } 1111fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3, &env->CP0_Config3); 1112fcf5ef2aSThomas Huth if (err < 0) { 1113fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG3 (%d)\n", __func__, err); 1114fcf5ef2aSThomas Huth ret = err; 1115fcf5ef2aSThomas Huth } 1116fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4, &env->CP0_Config4); 1117fcf5ef2aSThomas Huth if (err < 0) { 1118fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG4 (%d)\n", __func__, err); 1119fcf5ef2aSThomas Huth ret = err; 1120fcf5ef2aSThomas Huth } 1121fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, &env->CP0_Config5); 1122fcf5ef2aSThomas Huth if (err < 0) { 1123fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG5 (%d)\n", __func__, err); 1124fcf5ef2aSThomas Huth ret = err; 1125fcf5ef2aSThomas Huth } 11267e0896b0SHuacai Chen err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG6, &env->CP0_Config6); 11277e0896b0SHuacai Chen if (err < 0) { 11287e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_CONFIG6 (%d)\n", __func__, err); 11297e0896b0SHuacai Chen ret = err; 11307e0896b0SHuacai Chen } 11317e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_XCONTEXT, 11327e0896b0SHuacai Chen &env->CP0_XContext); 11337e0896b0SHuacai Chen if (err < 0) { 11347e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_XCONTEXT (%d)\n", __func__, err); 11357e0896b0SHuacai Chen ret = err; 11367e0896b0SHuacai Chen } 1137fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, 1138fcf5ef2aSThomas Huth &env->CP0_ErrorEPC); 1139fcf5ef2aSThomas Huth if (err < 0) { 1140fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err); 1141fcf5ef2aSThomas Huth ret = err; 1142fcf5ef2aSThomas Huth } 11437e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH1, 11447e0896b0SHuacai Chen &env->CP0_KScratch[0]); 11457e0896b0SHuacai Chen if (err < 0) { 11467e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH1 (%d)\n", __func__, err); 11477e0896b0SHuacai Chen ret = err; 11487e0896b0SHuacai Chen } 11497e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH2, 11507e0896b0SHuacai Chen &env->CP0_KScratch[1]); 11517e0896b0SHuacai Chen if (err < 0) { 11527e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH2 (%d)\n", __func__, err); 11537e0896b0SHuacai Chen ret = err; 11547e0896b0SHuacai Chen } 11557e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH3, 11567e0896b0SHuacai Chen &env->CP0_KScratch[2]); 11577e0896b0SHuacai Chen if (err < 0) { 11587e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH3 (%d)\n", __func__, err); 11597e0896b0SHuacai Chen ret = err; 11607e0896b0SHuacai Chen } 11617e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH4, 11627e0896b0SHuacai Chen &env->CP0_KScratch[3]); 11637e0896b0SHuacai Chen if (err < 0) { 11647e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH4 (%d)\n", __func__, err); 11657e0896b0SHuacai Chen ret = err; 11667e0896b0SHuacai Chen } 11677e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH5, 11687e0896b0SHuacai Chen &env->CP0_KScratch[4]); 11697e0896b0SHuacai Chen if (err < 0) { 11707e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH5 (%d)\n", __func__, err); 11717e0896b0SHuacai Chen ret = err; 11727e0896b0SHuacai Chen } 11737e0896b0SHuacai Chen err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH6, 11747e0896b0SHuacai Chen &env->CP0_KScratch[5]); 11757e0896b0SHuacai Chen if (err < 0) { 11767e0896b0SHuacai Chen DPRINTF("%s: Failed to get CP0_KSCRATCH6 (%d)\n", __func__, err); 11777e0896b0SHuacai Chen ret = err; 11787e0896b0SHuacai Chen } 1179fcf5ef2aSThomas Huth 1180fcf5ef2aSThomas Huth return ret; 1181fcf5ef2aSThomas Huth } 1182fcf5ef2aSThomas Huth 1183fcf5ef2aSThomas Huth int kvm_arch_put_registers(CPUState *cs, int level) 1184fcf5ef2aSThomas Huth { 1185fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 1186fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 1187fcf5ef2aSThomas Huth struct kvm_regs regs; 1188fcf5ef2aSThomas Huth int ret; 1189fcf5ef2aSThomas Huth int i; 1190fcf5ef2aSThomas Huth 1191fcf5ef2aSThomas Huth /* Set the registers based on QEMU's view of things */ 1192fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 1193fcf5ef2aSThomas Huth regs.gpr[i] = (int64_t)(target_long)env->active_tc.gpr[i]; 1194fcf5ef2aSThomas Huth } 1195fcf5ef2aSThomas Huth 1196fcf5ef2aSThomas Huth regs.hi = (int64_t)(target_long)env->active_tc.HI[0]; 1197fcf5ef2aSThomas Huth regs.lo = (int64_t)(target_long)env->active_tc.LO[0]; 1198fcf5ef2aSThomas Huth regs.pc = (int64_t)(target_long)env->active_tc.PC; 1199fcf5ef2aSThomas Huth 1200fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); 1201fcf5ef2aSThomas Huth 1202fcf5ef2aSThomas Huth if (ret < 0) { 1203fcf5ef2aSThomas Huth return ret; 1204fcf5ef2aSThomas Huth } 1205fcf5ef2aSThomas Huth 1206fcf5ef2aSThomas Huth ret = kvm_mips_put_cp0_registers(cs, level); 1207fcf5ef2aSThomas Huth if (ret < 0) { 1208fcf5ef2aSThomas Huth return ret; 1209fcf5ef2aSThomas Huth } 1210fcf5ef2aSThomas Huth 1211fcf5ef2aSThomas Huth ret = kvm_mips_put_fpu_registers(cs, level); 1212fcf5ef2aSThomas Huth if (ret < 0) { 1213fcf5ef2aSThomas Huth return ret; 1214fcf5ef2aSThomas Huth } 1215fcf5ef2aSThomas Huth 1216fcf5ef2aSThomas Huth return ret; 1217fcf5ef2aSThomas Huth } 1218fcf5ef2aSThomas Huth 1219fcf5ef2aSThomas Huth int kvm_arch_get_registers(CPUState *cs) 1220fcf5ef2aSThomas Huth { 1221fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 1222fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 1223fcf5ef2aSThomas Huth int ret = 0; 1224fcf5ef2aSThomas Huth struct kvm_regs regs; 1225fcf5ef2aSThomas Huth int i; 1226fcf5ef2aSThomas Huth 1227fcf5ef2aSThomas Huth /* Get the current register set as KVM seems it */ 1228fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 1229fcf5ef2aSThomas Huth 1230fcf5ef2aSThomas Huth if (ret < 0) { 1231fcf5ef2aSThomas Huth return ret; 1232fcf5ef2aSThomas Huth } 1233fcf5ef2aSThomas Huth 1234fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 1235fcf5ef2aSThomas Huth env->active_tc.gpr[i] = regs.gpr[i]; 1236fcf5ef2aSThomas Huth } 1237fcf5ef2aSThomas Huth 1238fcf5ef2aSThomas Huth env->active_tc.HI[0] = regs.hi; 1239fcf5ef2aSThomas Huth env->active_tc.LO[0] = regs.lo; 1240fcf5ef2aSThomas Huth env->active_tc.PC = regs.pc; 1241fcf5ef2aSThomas Huth 1242fcf5ef2aSThomas Huth kvm_mips_get_cp0_registers(cs); 1243fcf5ef2aSThomas Huth kvm_mips_get_fpu_registers(cs); 1244fcf5ef2aSThomas Huth 1245fcf5ef2aSThomas Huth return ret; 1246fcf5ef2aSThomas Huth } 1247fcf5ef2aSThomas Huth 1248fcf5ef2aSThomas Huth int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1249fcf5ef2aSThomas Huth uint64_t address, uint32_t data, PCIDevice *dev) 1250fcf5ef2aSThomas Huth { 1251fcf5ef2aSThomas Huth return 0; 1252fcf5ef2aSThomas Huth } 1253fcf5ef2aSThomas Huth 1254fcf5ef2aSThomas Huth int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1255fcf5ef2aSThomas Huth int vector, PCIDevice *dev) 1256fcf5ef2aSThomas Huth { 1257fcf5ef2aSThomas Huth return 0; 1258fcf5ef2aSThomas Huth } 1259fcf5ef2aSThomas Huth 1260fcf5ef2aSThomas Huth int kvm_arch_release_virq_post(int virq) 1261fcf5ef2aSThomas Huth { 1262fcf5ef2aSThomas Huth return 0; 1263fcf5ef2aSThomas Huth } 1264fcf5ef2aSThomas Huth 1265fcf5ef2aSThomas Huth int kvm_arch_msi_data_to_gsi(uint32_t data) 1266fcf5ef2aSThomas Huth { 1267fcf5ef2aSThomas Huth abort(); 1268fcf5ef2aSThomas Huth } 1269719d109bSHuacai Chen 1270719d109bSHuacai Chen int mips_kvm_type(MachineState *machine, const char *vm_type) 1271719d109bSHuacai Chen { 1272719d109bSHuacai Chen #if defined(KVM_CAP_MIPS_VZ) || defined(KVM_CAP_MIPS_TE) 1273719d109bSHuacai Chen int r; 1274719d109bSHuacai Chen KVMState *s = KVM_STATE(machine->accelerator); 1275719d109bSHuacai Chen #endif 1276719d109bSHuacai Chen 1277719d109bSHuacai Chen #if defined(KVM_CAP_MIPS_VZ) 1278719d109bSHuacai Chen r = kvm_check_extension(s, KVM_CAP_MIPS_VZ); 1279719d109bSHuacai Chen if (r > 0) { 1280719d109bSHuacai Chen return KVM_VM_MIPS_VZ; 1281719d109bSHuacai Chen } 1282719d109bSHuacai Chen #endif 1283719d109bSHuacai Chen 1284719d109bSHuacai Chen #if defined(KVM_CAP_MIPS_TE) 1285719d109bSHuacai Chen r = kvm_check_extension(s, KVM_CAP_MIPS_TE); 1286719d109bSHuacai Chen if (r > 0) { 1287719d109bSHuacai Chen return KVM_VM_MIPS_TE; 1288719d109bSHuacai Chen } 1289719d109bSHuacai Chen #endif 1290719d109bSHuacai Chen 1291719d109bSHuacai Chen return -1; 1292719d109bSHuacai Chen } 129392a5199bSTom Lendacky 129492a5199bSTom Lendacky bool kvm_arch_cpu_check_are_resettable(void) 129592a5199bSTom Lendacky { 129692a5199bSTom Lendacky return true; 129792a5199bSTom Lendacky } 1298