1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * This file is subject to the terms and conditions of the GNU General Public 3fcf5ef2aSThomas Huth * License. See the file "COPYING" in the main directory of this archive 4fcf5ef2aSThomas Huth * for more details. 5fcf5ef2aSThomas Huth * 6fcf5ef2aSThomas Huth * KVM/MIPS: MIPS specific KVM APIs 7fcf5ef2aSThomas Huth * 8fcf5ef2aSThomas Huth * Copyright (C) 2012-2014 Imagination Technologies Ltd. 9fcf5ef2aSThomas Huth * Authors: Sanjay Lal <sanjayl@kymasys.com> 10fcf5ef2aSThomas Huth */ 11fcf5ef2aSThomas Huth 12fcf5ef2aSThomas Huth #include "qemu/osdep.h" 13fcf5ef2aSThomas Huth #include <sys/ioctl.h> 14fcf5ef2aSThomas Huth 15fcf5ef2aSThomas Huth #include <linux/kvm.h> 16fcf5ef2aSThomas Huth 17fcf5ef2aSThomas Huth #include "qemu-common.h" 18fcf5ef2aSThomas Huth #include "cpu.h" 1926aa3d9aSPhilippe Mathieu-Daudé #include "internal.h" 20fcf5ef2aSThomas Huth #include "qemu/error-report.h" 21db725815SMarkus Armbruster #include "qemu/main-loop.h" 22fcf5ef2aSThomas Huth #include "qemu/timer.h" 23fcf5ef2aSThomas Huth #include "sysemu/kvm.h" 2454d31236SMarkus Armbruster #include "sysemu/runstate.h" 25fcf5ef2aSThomas Huth #include "sysemu/cpus.h" 26fcf5ef2aSThomas Huth #include "kvm_mips.h" 27fcf5ef2aSThomas Huth #include "exec/memattrs.h" 28fcf5ef2aSThomas Huth 29fcf5ef2aSThomas Huth #define DEBUG_KVM 0 30fcf5ef2aSThomas Huth 31fcf5ef2aSThomas Huth #define DPRINTF(fmt, ...) \ 32fcf5ef2aSThomas Huth do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0) 33fcf5ef2aSThomas Huth 34fcf5ef2aSThomas Huth static int kvm_mips_fpu_cap; 35fcf5ef2aSThomas Huth static int kvm_mips_msa_cap; 36fcf5ef2aSThomas Huth 37fcf5ef2aSThomas Huth const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 38fcf5ef2aSThomas Huth KVM_CAP_LAST_INFO 39fcf5ef2aSThomas Huth }; 40fcf5ef2aSThomas Huth 41fcf5ef2aSThomas Huth static void kvm_mips_update_state(void *opaque, int running, RunState state); 42fcf5ef2aSThomas Huth 43fcf5ef2aSThomas Huth unsigned long kvm_arch_vcpu_id(CPUState *cs) 44fcf5ef2aSThomas Huth { 45fcf5ef2aSThomas Huth return cs->cpu_index; 46fcf5ef2aSThomas Huth } 47fcf5ef2aSThomas Huth 48fcf5ef2aSThomas Huth int kvm_arch_init(MachineState *ms, KVMState *s) 49fcf5ef2aSThomas Huth { 50fcf5ef2aSThomas Huth /* MIPS has 128 signals */ 51fcf5ef2aSThomas Huth kvm_set_sigmask_len(s, 16); 52fcf5ef2aSThomas Huth 53fcf5ef2aSThomas Huth kvm_mips_fpu_cap = kvm_check_extension(s, KVM_CAP_MIPS_FPU); 54fcf5ef2aSThomas Huth kvm_mips_msa_cap = kvm_check_extension(s, KVM_CAP_MIPS_MSA); 55fcf5ef2aSThomas Huth 56fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 57fcf5ef2aSThomas Huth return 0; 58fcf5ef2aSThomas Huth } 59fcf5ef2aSThomas Huth 60*4376c40dSPaolo Bonzini int kvm_arch_irqchip_create(KVMState *s) 61d525ffabSPaolo Bonzini { 62d525ffabSPaolo Bonzini return 0; 63d525ffabSPaolo Bonzini } 64d525ffabSPaolo Bonzini 65fcf5ef2aSThomas Huth int kvm_arch_init_vcpu(CPUState *cs) 66fcf5ef2aSThomas Huth { 67fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 68fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 69fcf5ef2aSThomas Huth int ret = 0; 70fcf5ef2aSThomas Huth 71fcf5ef2aSThomas Huth qemu_add_vm_change_state_handler(kvm_mips_update_state, cs); 72fcf5ef2aSThomas Huth 73fcf5ef2aSThomas Huth if (kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) { 74fcf5ef2aSThomas Huth ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_FPU, 0, 0); 75fcf5ef2aSThomas Huth if (ret < 0) { 76fcf5ef2aSThomas Huth /* mark unsupported so it gets disabled on reset */ 77fcf5ef2aSThomas Huth kvm_mips_fpu_cap = 0; 78fcf5ef2aSThomas Huth ret = 0; 79fcf5ef2aSThomas Huth } 80fcf5ef2aSThomas Huth } 81fcf5ef2aSThomas Huth 82fcf5ef2aSThomas Huth if (kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) { 83fcf5ef2aSThomas Huth ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0); 84fcf5ef2aSThomas Huth if (ret < 0) { 85fcf5ef2aSThomas Huth /* mark unsupported so it gets disabled on reset */ 86fcf5ef2aSThomas Huth kvm_mips_msa_cap = 0; 87fcf5ef2aSThomas Huth ret = 0; 88fcf5ef2aSThomas Huth } 89fcf5ef2aSThomas Huth } 90fcf5ef2aSThomas Huth 91fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 92fcf5ef2aSThomas Huth return ret; 93fcf5ef2aSThomas Huth } 94fcf5ef2aSThomas Huth 95b1115c99SLiran Alon int kvm_arch_destroy_vcpu(CPUState *cs) 96b1115c99SLiran Alon { 97b1115c99SLiran Alon return 0; 98b1115c99SLiran Alon } 99b1115c99SLiran Alon 100fcf5ef2aSThomas Huth void kvm_mips_reset_vcpu(MIPSCPU *cpu) 101fcf5ef2aSThomas Huth { 102fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 103fcf5ef2aSThomas Huth 104fcf5ef2aSThomas Huth if (!kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) { 1052ab4b135SAlistair Francis warn_report("KVM does not support FPU, disabling"); 106fcf5ef2aSThomas Huth env->CP0_Config1 &= ~(1 << CP0C1_FP); 107fcf5ef2aSThomas Huth } 108fcf5ef2aSThomas Huth if (!kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) { 1092ab4b135SAlistair Francis warn_report("KVM does not support MSA, disabling"); 110fcf5ef2aSThomas Huth env->CP0_Config3 &= ~(1 << CP0C3_MSAP); 111fcf5ef2aSThomas Huth } 112fcf5ef2aSThomas Huth 113fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 114fcf5ef2aSThomas Huth } 115fcf5ef2aSThomas Huth 116fcf5ef2aSThomas Huth int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 117fcf5ef2aSThomas Huth { 118fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 119fcf5ef2aSThomas Huth return 0; 120fcf5ef2aSThomas Huth } 121fcf5ef2aSThomas Huth 122fcf5ef2aSThomas Huth int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 123fcf5ef2aSThomas Huth { 124fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 125fcf5ef2aSThomas Huth return 0; 126fcf5ef2aSThomas Huth } 127fcf5ef2aSThomas Huth 128fcf5ef2aSThomas Huth static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu) 129fcf5ef2aSThomas Huth { 130fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 131fcf5ef2aSThomas Huth 132fcf5ef2aSThomas Huth return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP)); 133fcf5ef2aSThomas Huth } 134fcf5ef2aSThomas Huth 135fcf5ef2aSThomas Huth 136fcf5ef2aSThomas Huth void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 137fcf5ef2aSThomas Huth { 138fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 139fcf5ef2aSThomas Huth int r; 140fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 141fcf5ef2aSThomas Huth 142fcf5ef2aSThomas Huth qemu_mutex_lock_iothread(); 143fcf5ef2aSThomas Huth 144fcf5ef2aSThomas Huth if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 145fcf5ef2aSThomas Huth cpu_mips_io_interrupts_pending(cpu)) { 146fcf5ef2aSThomas Huth intr.cpu = -1; 147fcf5ef2aSThomas Huth intr.irq = 2; 148fcf5ef2aSThomas Huth r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 149fcf5ef2aSThomas Huth if (r < 0) { 150fcf5ef2aSThomas Huth error_report("%s: cpu %d: failed to inject IRQ %x", 151fcf5ef2aSThomas Huth __func__, cs->cpu_index, intr.irq); 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth } 154fcf5ef2aSThomas Huth 155fcf5ef2aSThomas Huth qemu_mutex_unlock_iothread(); 156fcf5ef2aSThomas Huth } 157fcf5ef2aSThomas Huth 158fcf5ef2aSThomas Huth MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 159fcf5ef2aSThomas Huth { 160fcf5ef2aSThomas Huth return MEMTXATTRS_UNSPECIFIED; 161fcf5ef2aSThomas Huth } 162fcf5ef2aSThomas Huth 163fcf5ef2aSThomas Huth int kvm_arch_process_async_events(CPUState *cs) 164fcf5ef2aSThomas Huth { 165fcf5ef2aSThomas Huth return cs->halted; 166fcf5ef2aSThomas Huth } 167fcf5ef2aSThomas Huth 168fcf5ef2aSThomas Huth int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 169fcf5ef2aSThomas Huth { 170fcf5ef2aSThomas Huth int ret; 171fcf5ef2aSThomas Huth 172fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 173fcf5ef2aSThomas Huth switch (run->exit_reason) { 174fcf5ef2aSThomas Huth default: 175fcf5ef2aSThomas Huth error_report("%s: unknown exit reason %d", 176fcf5ef2aSThomas Huth __func__, run->exit_reason); 177fcf5ef2aSThomas Huth ret = -1; 178fcf5ef2aSThomas Huth break; 179fcf5ef2aSThomas Huth } 180fcf5ef2aSThomas Huth 181fcf5ef2aSThomas Huth return ret; 182fcf5ef2aSThomas Huth } 183fcf5ef2aSThomas Huth 184fcf5ef2aSThomas Huth bool kvm_arch_stop_on_emulation_error(CPUState *cs) 185fcf5ef2aSThomas Huth { 186fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 187fcf5ef2aSThomas Huth return true; 188fcf5ef2aSThomas Huth } 189fcf5ef2aSThomas Huth 190fcf5ef2aSThomas Huth void kvm_arch_init_irq_routing(KVMState *s) 191fcf5ef2aSThomas Huth { 192fcf5ef2aSThomas Huth } 193fcf5ef2aSThomas Huth 194fcf5ef2aSThomas Huth int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level) 195fcf5ef2aSThomas Huth { 196fcf5ef2aSThomas Huth CPUState *cs = CPU(cpu); 197fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 198fcf5ef2aSThomas Huth 199fcf5ef2aSThomas Huth if (!kvm_enabled()) { 200fcf5ef2aSThomas Huth return 0; 201fcf5ef2aSThomas Huth } 202fcf5ef2aSThomas Huth 203fcf5ef2aSThomas Huth intr.cpu = -1; 204fcf5ef2aSThomas Huth 205fcf5ef2aSThomas Huth if (level) { 206fcf5ef2aSThomas Huth intr.irq = irq; 207fcf5ef2aSThomas Huth } else { 208fcf5ef2aSThomas Huth intr.irq = -irq; 209fcf5ef2aSThomas Huth } 210fcf5ef2aSThomas Huth 211fcf5ef2aSThomas Huth kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 212fcf5ef2aSThomas Huth 213fcf5ef2aSThomas Huth return 0; 214fcf5ef2aSThomas Huth } 215fcf5ef2aSThomas Huth 216fcf5ef2aSThomas Huth int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) 217fcf5ef2aSThomas Huth { 218fcf5ef2aSThomas Huth CPUState *cs = current_cpu; 219fcf5ef2aSThomas Huth CPUState *dest_cs = CPU(cpu); 220fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 221fcf5ef2aSThomas Huth 222fcf5ef2aSThomas Huth if (!kvm_enabled()) { 223fcf5ef2aSThomas Huth return 0; 224fcf5ef2aSThomas Huth } 225fcf5ef2aSThomas Huth 226fcf5ef2aSThomas Huth intr.cpu = dest_cs->cpu_index; 227fcf5ef2aSThomas Huth 228fcf5ef2aSThomas Huth if (level) { 229fcf5ef2aSThomas Huth intr.irq = irq; 230fcf5ef2aSThomas Huth } else { 231fcf5ef2aSThomas Huth intr.irq = -irq; 232fcf5ef2aSThomas Huth } 233fcf5ef2aSThomas Huth 234fcf5ef2aSThomas Huth DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq); 235fcf5ef2aSThomas Huth 236fcf5ef2aSThomas Huth kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 237fcf5ef2aSThomas Huth 238fcf5ef2aSThomas Huth return 0; 239fcf5ef2aSThomas Huth } 240fcf5ef2aSThomas Huth 241fcf5ef2aSThomas Huth #define MIPS_CP0_32(_R, _S) \ 242fcf5ef2aSThomas Huth (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S))) 243fcf5ef2aSThomas Huth 244fcf5ef2aSThomas Huth #define MIPS_CP0_64(_R, _S) \ 245fcf5ef2aSThomas Huth (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) 246fcf5ef2aSThomas Huth 247fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) 248fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) 249fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) 250fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) 251fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) 252fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) 253fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) 254fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) 255fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) 256fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) 257fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) 258fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) 259fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) 260fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) 261fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) 262fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) 263fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) 264fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) 265fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) 266fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) 267fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) 268fcf5ef2aSThomas Huth 269fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, 270fcf5ef2aSThomas Huth int32_t *addr) 271fcf5ef2aSThomas Huth { 272fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 273fcf5ef2aSThomas Huth .id = reg_id, 274fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 275fcf5ef2aSThomas Huth }; 276fcf5ef2aSThomas Huth 277fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 278fcf5ef2aSThomas Huth } 279fcf5ef2aSThomas Huth 280fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ureg(CPUState *cs, uint64_t reg_id, 281fcf5ef2aSThomas Huth uint32_t *addr) 282fcf5ef2aSThomas Huth { 283fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 284fcf5ef2aSThomas Huth .id = reg_id, 285fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 286fcf5ef2aSThomas Huth }; 287fcf5ef2aSThomas Huth 288fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 289fcf5ef2aSThomas Huth } 290fcf5ef2aSThomas Huth 291fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id, 292fcf5ef2aSThomas Huth target_ulong *addr) 293fcf5ef2aSThomas Huth { 294fcf5ef2aSThomas Huth uint64_t val64 = *addr; 295fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 296fcf5ef2aSThomas Huth .id = reg_id, 297fcf5ef2aSThomas Huth .addr = (uintptr_t)&val64 298fcf5ef2aSThomas Huth }; 299fcf5ef2aSThomas Huth 300fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 301fcf5ef2aSThomas Huth } 302fcf5ef2aSThomas Huth 303fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id, 304fcf5ef2aSThomas Huth int64_t *addr) 305fcf5ef2aSThomas Huth { 306fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 307fcf5ef2aSThomas Huth .id = reg_id, 308fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 309fcf5ef2aSThomas Huth }; 310fcf5ef2aSThomas Huth 311fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 312fcf5ef2aSThomas Huth } 313fcf5ef2aSThomas Huth 314fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ureg64(CPUState *cs, uint64_t reg_id, 315fcf5ef2aSThomas Huth uint64_t *addr) 316fcf5ef2aSThomas Huth { 317fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 318fcf5ef2aSThomas Huth .id = reg_id, 319fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 320fcf5ef2aSThomas Huth }; 321fcf5ef2aSThomas Huth 322fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 323fcf5ef2aSThomas Huth } 324fcf5ef2aSThomas Huth 325fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id, 326fcf5ef2aSThomas Huth int32_t *addr) 327fcf5ef2aSThomas Huth { 328fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 329fcf5ef2aSThomas Huth .id = reg_id, 330fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 331fcf5ef2aSThomas Huth }; 332fcf5ef2aSThomas Huth 333fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 334fcf5ef2aSThomas Huth } 335fcf5ef2aSThomas Huth 336fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ureg(CPUState *cs, uint64_t reg_id, 337fcf5ef2aSThomas Huth uint32_t *addr) 338fcf5ef2aSThomas Huth { 339fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 340fcf5ef2aSThomas Huth .id = reg_id, 341fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 342fcf5ef2aSThomas Huth }; 343fcf5ef2aSThomas Huth 344fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 345fcf5ef2aSThomas Huth } 346fcf5ef2aSThomas Huth 347fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64_t reg_id, 348fcf5ef2aSThomas Huth target_ulong *addr) 349fcf5ef2aSThomas Huth { 350fcf5ef2aSThomas Huth int ret; 351fcf5ef2aSThomas Huth uint64_t val64 = 0; 352fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 353fcf5ef2aSThomas Huth .id = reg_id, 354fcf5ef2aSThomas Huth .addr = (uintptr_t)&val64 355fcf5ef2aSThomas Huth }; 356fcf5ef2aSThomas Huth 357fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 358fcf5ef2aSThomas Huth if (ret >= 0) { 359fcf5ef2aSThomas Huth *addr = val64; 360fcf5ef2aSThomas Huth } 361fcf5ef2aSThomas Huth return ret; 362fcf5ef2aSThomas Huth } 363fcf5ef2aSThomas Huth 364fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64_t reg_id, 365fcf5ef2aSThomas Huth int64_t *addr) 366fcf5ef2aSThomas Huth { 367fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 368fcf5ef2aSThomas Huth .id = reg_id, 369fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 370fcf5ef2aSThomas Huth }; 371fcf5ef2aSThomas Huth 372fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 373fcf5ef2aSThomas Huth } 374fcf5ef2aSThomas Huth 375fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ureg64(CPUState *cs, uint64_t reg_id, 376fcf5ef2aSThomas Huth uint64_t *addr) 377fcf5ef2aSThomas Huth { 378fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 379fcf5ef2aSThomas Huth .id = reg_id, 380fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 381fcf5ef2aSThomas Huth }; 382fcf5ef2aSThomas Huth 383fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 384fcf5ef2aSThomas Huth } 385fcf5ef2aSThomas Huth 386fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M) 387fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG1_MASK ((1U << CP0C1_M) | \ 388fcf5ef2aSThomas Huth (1U << CP0C1_FP)) 389fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG2_MASK (1U << CP0C2_M) 390fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG3_MASK ((1U << CP0C3_M) | \ 391fcf5ef2aSThomas Huth (1U << CP0C3_MSAP)) 392fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG4_MASK (1U << CP0C4_M) 393fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG5_MASK ((1U << CP0C5_MSAEn) | \ 394fcf5ef2aSThomas Huth (1U << CP0C5_UFE) | \ 395fcf5ef2aSThomas Huth (1U << CP0C5_FRE) | \ 396fcf5ef2aSThomas Huth (1U << CP0C5_UFR)) 397fcf5ef2aSThomas Huth 398fcf5ef2aSThomas Huth static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id, 399fcf5ef2aSThomas Huth int32_t *addr, int32_t mask) 400fcf5ef2aSThomas Huth { 401fcf5ef2aSThomas Huth int err; 402fcf5ef2aSThomas Huth int32_t tmp, change; 403fcf5ef2aSThomas Huth 404fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, reg_id, &tmp); 405fcf5ef2aSThomas Huth if (err < 0) { 406fcf5ef2aSThomas Huth return err; 407fcf5ef2aSThomas Huth } 408fcf5ef2aSThomas Huth 409fcf5ef2aSThomas Huth /* only change bits in mask */ 410fcf5ef2aSThomas Huth change = (*addr ^ tmp) & mask; 411fcf5ef2aSThomas Huth if (!change) { 412fcf5ef2aSThomas Huth return 0; 413fcf5ef2aSThomas Huth } 414fcf5ef2aSThomas Huth 415fcf5ef2aSThomas Huth tmp = tmp ^ change; 416fcf5ef2aSThomas Huth return kvm_mips_put_one_reg(cs, reg_id, &tmp); 417fcf5ef2aSThomas Huth } 418fcf5ef2aSThomas Huth 419fcf5ef2aSThomas Huth /* 420fcf5ef2aSThomas Huth * We freeze the KVM timer when either the VM clock is stopped or the state is 421fcf5ef2aSThomas Huth * saved (the state is dirty). 422fcf5ef2aSThomas Huth */ 423fcf5ef2aSThomas Huth 424fcf5ef2aSThomas Huth /* 425fcf5ef2aSThomas Huth * Save the state of the KVM timer when VM clock is stopped or state is synced 426fcf5ef2aSThomas Huth * to QEMU. 427fcf5ef2aSThomas Huth */ 428fcf5ef2aSThomas Huth static int kvm_mips_save_count(CPUState *cs) 429fcf5ef2aSThomas Huth { 430fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 431fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 432fcf5ef2aSThomas Huth uint64_t count_ctl; 433fcf5ef2aSThomas Huth int err, ret = 0; 434fcf5ef2aSThomas Huth 435fcf5ef2aSThomas Huth /* freeze KVM timer */ 436fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 437fcf5ef2aSThomas Huth if (err < 0) { 438fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err); 439fcf5ef2aSThomas Huth ret = err; 440fcf5ef2aSThomas Huth } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) { 441fcf5ef2aSThomas Huth count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC; 442fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 443fcf5ef2aSThomas Huth if (err < 0) { 444fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err); 445fcf5ef2aSThomas Huth ret = err; 446fcf5ef2aSThomas Huth } 447fcf5ef2aSThomas Huth } 448fcf5ef2aSThomas Huth 449fcf5ef2aSThomas Huth /* read CP0_Cause */ 450fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause); 451fcf5ef2aSThomas Huth if (err < 0) { 452fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err); 453fcf5ef2aSThomas Huth ret = err; 454fcf5ef2aSThomas Huth } 455fcf5ef2aSThomas Huth 456fcf5ef2aSThomas Huth /* read CP0_Count */ 457fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count); 458fcf5ef2aSThomas Huth if (err < 0) { 459fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err); 460fcf5ef2aSThomas Huth ret = err; 461fcf5ef2aSThomas Huth } 462fcf5ef2aSThomas Huth 463fcf5ef2aSThomas Huth return ret; 464fcf5ef2aSThomas Huth } 465fcf5ef2aSThomas Huth 466fcf5ef2aSThomas Huth /* 467fcf5ef2aSThomas Huth * Restore the state of the KVM timer when VM clock is restarted or state is 468fcf5ef2aSThomas Huth * synced to KVM. 469fcf5ef2aSThomas Huth */ 470fcf5ef2aSThomas Huth static int kvm_mips_restore_count(CPUState *cs) 471fcf5ef2aSThomas Huth { 472fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 473fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 474fcf5ef2aSThomas Huth uint64_t count_ctl; 475fcf5ef2aSThomas Huth int err_dc, err, ret = 0; 476fcf5ef2aSThomas Huth 477fcf5ef2aSThomas Huth /* check the timer is frozen */ 478fcf5ef2aSThomas Huth err_dc = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 479fcf5ef2aSThomas Huth if (err_dc < 0) { 480fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc); 481fcf5ef2aSThomas Huth ret = err_dc; 482fcf5ef2aSThomas Huth } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) { 483fcf5ef2aSThomas Huth /* freeze timer (sets COUNT_RESUME for us) */ 484fcf5ef2aSThomas Huth count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC; 485fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 486fcf5ef2aSThomas Huth if (err < 0) { 487fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err); 488fcf5ef2aSThomas Huth ret = err; 489fcf5ef2aSThomas Huth } 490fcf5ef2aSThomas Huth } 491fcf5ef2aSThomas Huth 492fcf5ef2aSThomas Huth /* load CP0_Cause */ 493fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause); 494fcf5ef2aSThomas Huth if (err < 0) { 495fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err); 496fcf5ef2aSThomas Huth ret = err; 497fcf5ef2aSThomas Huth } 498fcf5ef2aSThomas Huth 499fcf5ef2aSThomas Huth /* load CP0_Count */ 500fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count); 501fcf5ef2aSThomas Huth if (err < 0) { 502fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err); 503fcf5ef2aSThomas Huth ret = err; 504fcf5ef2aSThomas Huth } 505fcf5ef2aSThomas Huth 506fcf5ef2aSThomas Huth /* resume KVM timer */ 507fcf5ef2aSThomas Huth if (err_dc >= 0) { 508fcf5ef2aSThomas Huth count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC; 509fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 510fcf5ef2aSThomas Huth if (err < 0) { 511fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err); 512fcf5ef2aSThomas Huth ret = err; 513fcf5ef2aSThomas Huth } 514fcf5ef2aSThomas Huth } 515fcf5ef2aSThomas Huth 516fcf5ef2aSThomas Huth return ret; 517fcf5ef2aSThomas Huth } 518fcf5ef2aSThomas Huth 519fcf5ef2aSThomas Huth /* 520fcf5ef2aSThomas Huth * Handle the VM clock being started or stopped 521fcf5ef2aSThomas Huth */ 522fcf5ef2aSThomas Huth static void kvm_mips_update_state(void *opaque, int running, RunState state) 523fcf5ef2aSThomas Huth { 524fcf5ef2aSThomas Huth CPUState *cs = opaque; 525fcf5ef2aSThomas Huth int ret; 526fcf5ef2aSThomas Huth uint64_t count_resume; 527fcf5ef2aSThomas Huth 528fcf5ef2aSThomas Huth /* 529fcf5ef2aSThomas Huth * If state is already dirty (synced to QEMU) then the KVM timer state is 530fcf5ef2aSThomas Huth * already saved and can be restored when it is synced back to KVM. 531fcf5ef2aSThomas Huth */ 532fcf5ef2aSThomas Huth if (!running) { 53399f31832SSergio Andres Gomez Del Real if (!cs->vcpu_dirty) { 534fcf5ef2aSThomas Huth ret = kvm_mips_save_count(cs); 535fcf5ef2aSThomas Huth if (ret < 0) { 536288cb949SAlistair Francis warn_report("Failed saving count"); 537fcf5ef2aSThomas Huth } 538fcf5ef2aSThomas Huth } 539fcf5ef2aSThomas Huth } else { 540fcf5ef2aSThomas Huth /* Set clock restore time to now */ 541fcf5ef2aSThomas Huth count_resume = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 542fcf5ef2aSThomas Huth ret = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_RESUME, 543fcf5ef2aSThomas Huth &count_resume); 544fcf5ef2aSThomas Huth if (ret < 0) { 545288cb949SAlistair Francis warn_report("Failed setting COUNT_RESUME"); 546fcf5ef2aSThomas Huth return; 547fcf5ef2aSThomas Huth } 548fcf5ef2aSThomas Huth 54999f31832SSergio Andres Gomez Del Real if (!cs->vcpu_dirty) { 550fcf5ef2aSThomas Huth ret = kvm_mips_restore_count(cs); 551fcf5ef2aSThomas Huth if (ret < 0) { 552288cb949SAlistair Francis warn_report("Failed restoring count"); 553fcf5ef2aSThomas Huth } 554fcf5ef2aSThomas Huth } 555fcf5ef2aSThomas Huth } 556fcf5ef2aSThomas Huth } 557fcf5ef2aSThomas Huth 558fcf5ef2aSThomas Huth static int kvm_mips_put_fpu_registers(CPUState *cs, int level) 559fcf5ef2aSThomas Huth { 560fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 561fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 562fcf5ef2aSThomas Huth int err, ret = 0; 563fcf5ef2aSThomas Huth unsigned int i; 564fcf5ef2aSThomas Huth 565fcf5ef2aSThomas Huth /* Only put FPU state if we're emulating a CPU with an FPU */ 566fcf5ef2aSThomas Huth if (env->CP0_Config1 & (1 << CP0C1_FP)) { 567fcf5ef2aSThomas Huth /* FPU Control Registers */ 568fcf5ef2aSThomas Huth if (level == KVM_PUT_FULL_STATE) { 569fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg(cs, KVM_REG_MIPS_FCR_IR, 570fcf5ef2aSThomas Huth &env->active_fpu.fcr0); 571fcf5ef2aSThomas Huth if (err < 0) { 572fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FCR_IR (%d)\n", __func__, err); 573fcf5ef2aSThomas Huth ret = err; 574fcf5ef2aSThomas Huth } 575fcf5ef2aSThomas Huth } 576fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg(cs, KVM_REG_MIPS_FCR_CSR, 577fcf5ef2aSThomas Huth &env->active_fpu.fcr31); 578fcf5ef2aSThomas Huth if (err < 0) { 579fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FCR_CSR (%d)\n", __func__, err); 580fcf5ef2aSThomas Huth ret = err; 581fcf5ef2aSThomas Huth } 582fcf5ef2aSThomas Huth 583fcf5ef2aSThomas Huth /* 584fcf5ef2aSThomas Huth * FPU register state is a subset of MSA vector state, so don't put FPU 585fcf5ef2aSThomas Huth * registers if we're emulating a CPU with MSA. 586fcf5ef2aSThomas Huth */ 587fcf5ef2aSThomas Huth if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { 588fcf5ef2aSThomas Huth /* Floating point registers */ 589fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 590fcf5ef2aSThomas Huth if (env->CP0_Status & (1 << CP0St_FR)) { 591fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i), 592fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].d); 593fcf5ef2aSThomas Huth } else { 594fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i), 595fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); 596fcf5ef2aSThomas Huth } 597fcf5ef2aSThomas Huth if (err < 0) { 598fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FPR%u (%d)\n", __func__, i, err); 599fcf5ef2aSThomas Huth ret = err; 600fcf5ef2aSThomas Huth } 601fcf5ef2aSThomas Huth } 602fcf5ef2aSThomas Huth } 603fcf5ef2aSThomas Huth } 604fcf5ef2aSThomas Huth 605fcf5ef2aSThomas Huth /* Only put MSA state if we're emulating a CPU with MSA */ 606fcf5ef2aSThomas Huth if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { 607fcf5ef2aSThomas Huth /* MSA Control Registers */ 608fcf5ef2aSThomas Huth if (level == KVM_PUT_FULL_STATE) { 609fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_IR, 610fcf5ef2aSThomas Huth &env->msair); 611fcf5ef2aSThomas Huth if (err < 0) { 612fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put MSA_IR (%d)\n", __func__, err); 613fcf5ef2aSThomas Huth ret = err; 614fcf5ef2aSThomas Huth } 615fcf5ef2aSThomas Huth } 616fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_CSR, 617fcf5ef2aSThomas Huth &env->active_tc.msacsr); 618fcf5ef2aSThomas Huth if (err < 0) { 619fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put MSA_CSR (%d)\n", __func__, err); 620fcf5ef2aSThomas Huth ret = err; 621fcf5ef2aSThomas Huth } 622fcf5ef2aSThomas Huth 623fcf5ef2aSThomas Huth /* Vector registers (includes FP registers) */ 624fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 625fcf5ef2aSThomas Huth /* Big endian MSA not supported by QEMU yet anyway */ 626fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_VEC_128(i), 627fcf5ef2aSThomas Huth env->active_fpu.fpr[i].wr.d); 628fcf5ef2aSThomas Huth if (err < 0) { 629fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put VEC%u (%d)\n", __func__, i, err); 630fcf5ef2aSThomas Huth ret = err; 631fcf5ef2aSThomas Huth } 632fcf5ef2aSThomas Huth } 633fcf5ef2aSThomas Huth } 634fcf5ef2aSThomas Huth 635fcf5ef2aSThomas Huth return ret; 636fcf5ef2aSThomas Huth } 637fcf5ef2aSThomas Huth 638fcf5ef2aSThomas Huth static int kvm_mips_get_fpu_registers(CPUState *cs) 639fcf5ef2aSThomas Huth { 640fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 641fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 642fcf5ef2aSThomas Huth int err, ret = 0; 643fcf5ef2aSThomas Huth unsigned int i; 644fcf5ef2aSThomas Huth 645fcf5ef2aSThomas Huth /* Only get FPU state if we're emulating a CPU with an FPU */ 646fcf5ef2aSThomas Huth if (env->CP0_Config1 & (1 << CP0C1_FP)) { 647fcf5ef2aSThomas Huth /* FPU Control Registers */ 648fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_IR, 649fcf5ef2aSThomas Huth &env->active_fpu.fcr0); 650fcf5ef2aSThomas Huth if (err < 0) { 651fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FCR_IR (%d)\n", __func__, err); 652fcf5ef2aSThomas Huth ret = err; 653fcf5ef2aSThomas Huth } 654fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_CSR, 655fcf5ef2aSThomas Huth &env->active_fpu.fcr31); 656fcf5ef2aSThomas Huth if (err < 0) { 657fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FCR_CSR (%d)\n", __func__, err); 658fcf5ef2aSThomas Huth ret = err; 659fcf5ef2aSThomas Huth } else { 660fcf5ef2aSThomas Huth restore_fp_status(env); 661fcf5ef2aSThomas Huth } 662fcf5ef2aSThomas Huth 663fcf5ef2aSThomas Huth /* 664fcf5ef2aSThomas Huth * FPU register state is a subset of MSA vector state, so don't save FPU 665fcf5ef2aSThomas Huth * registers if we're emulating a CPU with MSA. 666fcf5ef2aSThomas Huth */ 667fcf5ef2aSThomas Huth if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { 668fcf5ef2aSThomas Huth /* Floating point registers */ 669fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 670fcf5ef2aSThomas Huth if (env->CP0_Status & (1 << CP0St_FR)) { 671fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i), 672fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].d); 673fcf5ef2aSThomas Huth } else { 674fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i), 675fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); 676fcf5ef2aSThomas Huth } 677fcf5ef2aSThomas Huth if (err < 0) { 678fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__, i, err); 679fcf5ef2aSThomas Huth ret = err; 680fcf5ef2aSThomas Huth } 681fcf5ef2aSThomas Huth } 682fcf5ef2aSThomas Huth } 683fcf5ef2aSThomas Huth } 684fcf5ef2aSThomas Huth 685fcf5ef2aSThomas Huth /* Only get MSA state if we're emulating a CPU with MSA */ 686fcf5ef2aSThomas Huth if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { 687fcf5ef2aSThomas Huth /* MSA Control Registers */ 688fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR, 689fcf5ef2aSThomas Huth &env->msair); 690fcf5ef2aSThomas Huth if (err < 0) { 691fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get MSA_IR (%d)\n", __func__, err); 692fcf5ef2aSThomas Huth ret = err; 693fcf5ef2aSThomas Huth } 694fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_CSR, 695fcf5ef2aSThomas Huth &env->active_tc.msacsr); 696fcf5ef2aSThomas Huth if (err < 0) { 697fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get MSA_CSR (%d)\n", __func__, err); 698fcf5ef2aSThomas Huth ret = err; 699fcf5ef2aSThomas Huth } else { 700fcf5ef2aSThomas Huth restore_msa_fp_status(env); 701fcf5ef2aSThomas Huth } 702fcf5ef2aSThomas Huth 703fcf5ef2aSThomas Huth /* Vector registers (includes FP registers) */ 704fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 705fcf5ef2aSThomas Huth /* Big endian MSA not supported by QEMU yet anyway */ 706fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_VEC_128(i), 707fcf5ef2aSThomas Huth env->active_fpu.fpr[i].wr.d); 708fcf5ef2aSThomas Huth if (err < 0) { 709fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get VEC%u (%d)\n", __func__, i, err); 710fcf5ef2aSThomas Huth ret = err; 711fcf5ef2aSThomas Huth } 712fcf5ef2aSThomas Huth } 713fcf5ef2aSThomas Huth } 714fcf5ef2aSThomas Huth 715fcf5ef2aSThomas Huth return ret; 716fcf5ef2aSThomas Huth } 717fcf5ef2aSThomas Huth 718fcf5ef2aSThomas Huth 719fcf5ef2aSThomas Huth static int kvm_mips_put_cp0_registers(CPUState *cs, int level) 720fcf5ef2aSThomas Huth { 721fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 722fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 723fcf5ef2aSThomas Huth int err, ret = 0; 724fcf5ef2aSThomas Huth 725fcf5ef2aSThomas Huth (void)level; 726fcf5ef2aSThomas Huth 727fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); 728fcf5ef2aSThomas Huth if (err < 0) { 729fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err); 730fcf5ef2aSThomas Huth ret = err; 731fcf5ef2aSThomas Huth } 732fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, 733fcf5ef2aSThomas Huth &env->CP0_Context); 734fcf5ef2aSThomas Huth if (err < 0) { 735fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err); 736fcf5ef2aSThomas Huth ret = err; 737fcf5ef2aSThomas Huth } 738fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL, 739fcf5ef2aSThomas Huth &env->active_tc.CP0_UserLocal); 740fcf5ef2aSThomas Huth if (err < 0) { 741fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err); 742fcf5ef2aSThomas Huth ret = err; 743fcf5ef2aSThomas Huth } 744fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK, 745fcf5ef2aSThomas Huth &env->CP0_PageMask); 746fcf5ef2aSThomas Huth if (err < 0) { 747fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err); 748fcf5ef2aSThomas Huth ret = err; 749fcf5ef2aSThomas Huth } 750fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); 751fcf5ef2aSThomas Huth if (err < 0) { 752fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err); 753fcf5ef2aSThomas Huth ret = err; 754fcf5ef2aSThomas Huth } 755fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); 756fcf5ef2aSThomas Huth if (err < 0) { 757fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err); 758fcf5ef2aSThomas Huth ret = err; 759fcf5ef2aSThomas Huth } 760fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR, 761fcf5ef2aSThomas Huth &env->CP0_BadVAddr); 762fcf5ef2aSThomas Huth if (err < 0) { 763fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err); 764fcf5ef2aSThomas Huth ret = err; 765fcf5ef2aSThomas Huth } 766fcf5ef2aSThomas Huth 767fcf5ef2aSThomas Huth /* If VM clock stopped then state will be restored when it is restarted */ 768fcf5ef2aSThomas Huth if (runstate_is_running()) { 769fcf5ef2aSThomas Huth err = kvm_mips_restore_count(cs); 770fcf5ef2aSThomas Huth if (err < 0) { 771fcf5ef2aSThomas Huth ret = err; 772fcf5ef2aSThomas Huth } 773fcf5ef2aSThomas Huth } 774fcf5ef2aSThomas Huth 775fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI, 776fcf5ef2aSThomas Huth &env->CP0_EntryHi); 777fcf5ef2aSThomas Huth if (err < 0) { 778fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err); 779fcf5ef2aSThomas Huth ret = err; 780fcf5ef2aSThomas Huth } 781fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE, 782fcf5ef2aSThomas Huth &env->CP0_Compare); 783fcf5ef2aSThomas Huth if (err < 0) { 784fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err); 785fcf5ef2aSThomas Huth ret = err; 786fcf5ef2aSThomas Huth } 787fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status); 788fcf5ef2aSThomas Huth if (err < 0) { 789fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err); 790fcf5ef2aSThomas Huth ret = err; 791fcf5ef2aSThomas Huth } 792fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC); 793fcf5ef2aSThomas Huth if (err < 0) { 794fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err); 795fcf5ef2aSThomas Huth ret = err; 796fcf5ef2aSThomas Huth } 797fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); 798fcf5ef2aSThomas Huth if (err < 0) { 799fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err); 800fcf5ef2aSThomas Huth ret = err; 801fcf5ef2aSThomas Huth } 802fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, 803fcf5ef2aSThomas Huth &env->CP0_Config0, 804fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG_MASK); 805fcf5ef2aSThomas Huth if (err < 0) { 806fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG (%d)\n", __func__, err); 807fcf5ef2aSThomas Huth ret = err; 808fcf5ef2aSThomas Huth } 809fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, 810fcf5ef2aSThomas Huth &env->CP0_Config1, 811fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG1_MASK); 812fcf5ef2aSThomas Huth if (err < 0) { 813fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG1 (%d)\n", __func__, err); 814fcf5ef2aSThomas Huth ret = err; 815fcf5ef2aSThomas Huth } 816fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2, 817fcf5ef2aSThomas Huth &env->CP0_Config2, 818fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG2_MASK); 819fcf5ef2aSThomas Huth if (err < 0) { 820fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG2 (%d)\n", __func__, err); 821fcf5ef2aSThomas Huth ret = err; 822fcf5ef2aSThomas Huth } 823fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3, 824fcf5ef2aSThomas Huth &env->CP0_Config3, 825fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG3_MASK); 826fcf5ef2aSThomas Huth if (err < 0) { 827fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG3 (%d)\n", __func__, err); 828fcf5ef2aSThomas Huth ret = err; 829fcf5ef2aSThomas Huth } 830fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4, 831fcf5ef2aSThomas Huth &env->CP0_Config4, 832fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG4_MASK); 833fcf5ef2aSThomas Huth if (err < 0) { 834fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG4 (%d)\n", __func__, err); 835fcf5ef2aSThomas Huth ret = err; 836fcf5ef2aSThomas Huth } 837fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, 838fcf5ef2aSThomas Huth &env->CP0_Config5, 839fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG5_MASK); 840fcf5ef2aSThomas Huth if (err < 0) { 841fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG5 (%d)\n", __func__, err); 842fcf5ef2aSThomas Huth ret = err; 843fcf5ef2aSThomas Huth } 844fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, 845fcf5ef2aSThomas Huth &env->CP0_ErrorEPC); 846fcf5ef2aSThomas Huth if (err < 0) { 847fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err); 848fcf5ef2aSThomas Huth ret = err; 849fcf5ef2aSThomas Huth } 850fcf5ef2aSThomas Huth 851fcf5ef2aSThomas Huth return ret; 852fcf5ef2aSThomas Huth } 853fcf5ef2aSThomas Huth 854fcf5ef2aSThomas Huth static int kvm_mips_get_cp0_registers(CPUState *cs) 855fcf5ef2aSThomas Huth { 856fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 857fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 858fcf5ef2aSThomas Huth int err, ret = 0; 859fcf5ef2aSThomas Huth 860fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); 861fcf5ef2aSThomas Huth if (err < 0) { 862fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err); 863fcf5ef2aSThomas Huth ret = err; 864fcf5ef2aSThomas Huth } 865fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, 866fcf5ef2aSThomas Huth &env->CP0_Context); 867fcf5ef2aSThomas Huth if (err < 0) { 868fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err); 869fcf5ef2aSThomas Huth ret = err; 870fcf5ef2aSThomas Huth } 871fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL, 872fcf5ef2aSThomas Huth &env->active_tc.CP0_UserLocal); 873fcf5ef2aSThomas Huth if (err < 0) { 874fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err); 875fcf5ef2aSThomas Huth ret = err; 876fcf5ef2aSThomas Huth } 877fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK, 878fcf5ef2aSThomas Huth &env->CP0_PageMask); 879fcf5ef2aSThomas Huth if (err < 0) { 880fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err); 881fcf5ef2aSThomas Huth ret = err; 882fcf5ef2aSThomas Huth } 883fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); 884fcf5ef2aSThomas Huth if (err < 0) { 885fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err); 886fcf5ef2aSThomas Huth ret = err; 887fcf5ef2aSThomas Huth } 888fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); 889fcf5ef2aSThomas Huth if (err < 0) { 890fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err); 891fcf5ef2aSThomas Huth ret = err; 892fcf5ef2aSThomas Huth } 893fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR, 894fcf5ef2aSThomas Huth &env->CP0_BadVAddr); 895fcf5ef2aSThomas Huth if (err < 0) { 896fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err); 897fcf5ef2aSThomas Huth ret = err; 898fcf5ef2aSThomas Huth } 899fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI, 900fcf5ef2aSThomas Huth &env->CP0_EntryHi); 901fcf5ef2aSThomas Huth if (err < 0) { 902fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err); 903fcf5ef2aSThomas Huth ret = err; 904fcf5ef2aSThomas Huth } 905fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE, 906fcf5ef2aSThomas Huth &env->CP0_Compare); 907fcf5ef2aSThomas Huth if (err < 0) { 908fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err); 909fcf5ef2aSThomas Huth ret = err; 910fcf5ef2aSThomas Huth } 911fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status); 912fcf5ef2aSThomas Huth if (err < 0) { 913fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err); 914fcf5ef2aSThomas Huth ret = err; 915fcf5ef2aSThomas Huth } 916fcf5ef2aSThomas Huth 917fcf5ef2aSThomas Huth /* If VM clock stopped then state was already saved when it was stopped */ 918fcf5ef2aSThomas Huth if (runstate_is_running()) { 919fcf5ef2aSThomas Huth err = kvm_mips_save_count(cs); 920fcf5ef2aSThomas Huth if (err < 0) { 921fcf5ef2aSThomas Huth ret = err; 922fcf5ef2aSThomas Huth } 923fcf5ef2aSThomas Huth } 924fcf5ef2aSThomas Huth 925fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC); 926fcf5ef2aSThomas Huth if (err < 0) { 927fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err); 928fcf5ef2aSThomas Huth ret = err; 929fcf5ef2aSThomas Huth } 930fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); 931fcf5ef2aSThomas Huth if (err < 0) { 932fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err); 933fcf5ef2aSThomas Huth ret = err; 934fcf5ef2aSThomas Huth } 935fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, &env->CP0_Config0); 936fcf5ef2aSThomas Huth if (err < 0) { 937fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG (%d)\n", __func__, err); 938fcf5ef2aSThomas Huth ret = err; 939fcf5ef2aSThomas Huth } 940fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, &env->CP0_Config1); 941fcf5ef2aSThomas Huth if (err < 0) { 942fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG1 (%d)\n", __func__, err); 943fcf5ef2aSThomas Huth ret = err; 944fcf5ef2aSThomas Huth } 945fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2, &env->CP0_Config2); 946fcf5ef2aSThomas Huth if (err < 0) { 947fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG2 (%d)\n", __func__, err); 948fcf5ef2aSThomas Huth ret = err; 949fcf5ef2aSThomas Huth } 950fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3, &env->CP0_Config3); 951fcf5ef2aSThomas Huth if (err < 0) { 952fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG3 (%d)\n", __func__, err); 953fcf5ef2aSThomas Huth ret = err; 954fcf5ef2aSThomas Huth } 955fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4, &env->CP0_Config4); 956fcf5ef2aSThomas Huth if (err < 0) { 957fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG4 (%d)\n", __func__, err); 958fcf5ef2aSThomas Huth ret = err; 959fcf5ef2aSThomas Huth } 960fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, &env->CP0_Config5); 961fcf5ef2aSThomas Huth if (err < 0) { 962fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG5 (%d)\n", __func__, err); 963fcf5ef2aSThomas Huth ret = err; 964fcf5ef2aSThomas Huth } 965fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, 966fcf5ef2aSThomas Huth &env->CP0_ErrorEPC); 967fcf5ef2aSThomas Huth if (err < 0) { 968fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err); 969fcf5ef2aSThomas Huth ret = err; 970fcf5ef2aSThomas Huth } 971fcf5ef2aSThomas Huth 972fcf5ef2aSThomas Huth return ret; 973fcf5ef2aSThomas Huth } 974fcf5ef2aSThomas Huth 975fcf5ef2aSThomas Huth int kvm_arch_put_registers(CPUState *cs, int level) 976fcf5ef2aSThomas Huth { 977fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 978fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 979fcf5ef2aSThomas Huth struct kvm_regs regs; 980fcf5ef2aSThomas Huth int ret; 981fcf5ef2aSThomas Huth int i; 982fcf5ef2aSThomas Huth 983fcf5ef2aSThomas Huth /* Set the registers based on QEMU's view of things */ 984fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 985fcf5ef2aSThomas Huth regs.gpr[i] = (int64_t)(target_long)env->active_tc.gpr[i]; 986fcf5ef2aSThomas Huth } 987fcf5ef2aSThomas Huth 988fcf5ef2aSThomas Huth regs.hi = (int64_t)(target_long)env->active_tc.HI[0]; 989fcf5ef2aSThomas Huth regs.lo = (int64_t)(target_long)env->active_tc.LO[0]; 990fcf5ef2aSThomas Huth regs.pc = (int64_t)(target_long)env->active_tc.PC; 991fcf5ef2aSThomas Huth 992fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); 993fcf5ef2aSThomas Huth 994fcf5ef2aSThomas Huth if (ret < 0) { 995fcf5ef2aSThomas Huth return ret; 996fcf5ef2aSThomas Huth } 997fcf5ef2aSThomas Huth 998fcf5ef2aSThomas Huth ret = kvm_mips_put_cp0_registers(cs, level); 999fcf5ef2aSThomas Huth if (ret < 0) { 1000fcf5ef2aSThomas Huth return ret; 1001fcf5ef2aSThomas Huth } 1002fcf5ef2aSThomas Huth 1003fcf5ef2aSThomas Huth ret = kvm_mips_put_fpu_registers(cs, level); 1004fcf5ef2aSThomas Huth if (ret < 0) { 1005fcf5ef2aSThomas Huth return ret; 1006fcf5ef2aSThomas Huth } 1007fcf5ef2aSThomas Huth 1008fcf5ef2aSThomas Huth return ret; 1009fcf5ef2aSThomas Huth } 1010fcf5ef2aSThomas Huth 1011fcf5ef2aSThomas Huth int kvm_arch_get_registers(CPUState *cs) 1012fcf5ef2aSThomas Huth { 1013fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 1014fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 1015fcf5ef2aSThomas Huth int ret = 0; 1016fcf5ef2aSThomas Huth struct kvm_regs regs; 1017fcf5ef2aSThomas Huth int i; 1018fcf5ef2aSThomas Huth 1019fcf5ef2aSThomas Huth /* Get the current register set as KVM seems it */ 1020fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 1021fcf5ef2aSThomas Huth 1022fcf5ef2aSThomas Huth if (ret < 0) { 1023fcf5ef2aSThomas Huth return ret; 1024fcf5ef2aSThomas Huth } 1025fcf5ef2aSThomas Huth 1026fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 1027fcf5ef2aSThomas Huth env->active_tc.gpr[i] = regs.gpr[i]; 1028fcf5ef2aSThomas Huth } 1029fcf5ef2aSThomas Huth 1030fcf5ef2aSThomas Huth env->active_tc.HI[0] = regs.hi; 1031fcf5ef2aSThomas Huth env->active_tc.LO[0] = regs.lo; 1032fcf5ef2aSThomas Huth env->active_tc.PC = regs.pc; 1033fcf5ef2aSThomas Huth 1034fcf5ef2aSThomas Huth kvm_mips_get_cp0_registers(cs); 1035fcf5ef2aSThomas Huth kvm_mips_get_fpu_registers(cs); 1036fcf5ef2aSThomas Huth 1037fcf5ef2aSThomas Huth return ret; 1038fcf5ef2aSThomas Huth } 1039fcf5ef2aSThomas Huth 1040fcf5ef2aSThomas Huth int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1041fcf5ef2aSThomas Huth uint64_t address, uint32_t data, PCIDevice *dev) 1042fcf5ef2aSThomas Huth { 1043fcf5ef2aSThomas Huth return 0; 1044fcf5ef2aSThomas Huth } 1045fcf5ef2aSThomas Huth 1046fcf5ef2aSThomas Huth int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1047fcf5ef2aSThomas Huth int vector, PCIDevice *dev) 1048fcf5ef2aSThomas Huth { 1049fcf5ef2aSThomas Huth return 0; 1050fcf5ef2aSThomas Huth } 1051fcf5ef2aSThomas Huth 1052fcf5ef2aSThomas Huth int kvm_arch_release_virq_post(int virq) 1053fcf5ef2aSThomas Huth { 1054fcf5ef2aSThomas Huth return 0; 1055fcf5ef2aSThomas Huth } 1056fcf5ef2aSThomas Huth 1057fcf5ef2aSThomas Huth int kvm_arch_msi_data_to_gsi(uint32_t data) 1058fcf5ef2aSThomas Huth { 1059fcf5ef2aSThomas Huth abort(); 1060fcf5ef2aSThomas Huth } 1061