1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * This file is subject to the terms and conditions of the GNU General Public 3fcf5ef2aSThomas Huth * License. See the file "COPYING" in the main directory of this archive 4fcf5ef2aSThomas Huth * for more details. 5fcf5ef2aSThomas Huth * 6fcf5ef2aSThomas Huth * KVM/MIPS: MIPS specific KVM APIs 7fcf5ef2aSThomas Huth * 8fcf5ef2aSThomas Huth * Copyright (C) 2012-2014 Imagination Technologies Ltd. 9fcf5ef2aSThomas Huth * Authors: Sanjay Lal <sanjayl@kymasys.com> 10fcf5ef2aSThomas Huth */ 11fcf5ef2aSThomas Huth 12fcf5ef2aSThomas Huth #include "qemu/osdep.h" 13fcf5ef2aSThomas Huth #include <sys/ioctl.h> 14fcf5ef2aSThomas Huth 15fcf5ef2aSThomas Huth #include <linux/kvm.h> 16fcf5ef2aSThomas Huth 17fcf5ef2aSThomas Huth #include "qemu-common.h" 18fcf5ef2aSThomas Huth #include "cpu.h" 19*26aa3d9aSPhilippe Mathieu-Daudé #include "internal.h" 20fcf5ef2aSThomas Huth #include "qemu/error-report.h" 21fcf5ef2aSThomas Huth #include "qemu/timer.h" 22fcf5ef2aSThomas Huth #include "sysemu/sysemu.h" 23fcf5ef2aSThomas Huth #include "sysemu/kvm.h" 24fcf5ef2aSThomas Huth #include "sysemu/cpus.h" 25fcf5ef2aSThomas Huth #include "kvm_mips.h" 26fcf5ef2aSThomas Huth #include "exec/memattrs.h" 27fcf5ef2aSThomas Huth 28fcf5ef2aSThomas Huth #define DEBUG_KVM 0 29fcf5ef2aSThomas Huth 30fcf5ef2aSThomas Huth #define DPRINTF(fmt, ...) \ 31fcf5ef2aSThomas Huth do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0) 32fcf5ef2aSThomas Huth 33fcf5ef2aSThomas Huth static int kvm_mips_fpu_cap; 34fcf5ef2aSThomas Huth static int kvm_mips_msa_cap; 35fcf5ef2aSThomas Huth 36fcf5ef2aSThomas Huth const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 37fcf5ef2aSThomas Huth KVM_CAP_LAST_INFO 38fcf5ef2aSThomas Huth }; 39fcf5ef2aSThomas Huth 40fcf5ef2aSThomas Huth static void kvm_mips_update_state(void *opaque, int running, RunState state); 41fcf5ef2aSThomas Huth 42fcf5ef2aSThomas Huth unsigned long kvm_arch_vcpu_id(CPUState *cs) 43fcf5ef2aSThomas Huth { 44fcf5ef2aSThomas Huth return cs->cpu_index; 45fcf5ef2aSThomas Huth } 46fcf5ef2aSThomas Huth 47fcf5ef2aSThomas Huth int kvm_arch_init(MachineState *ms, KVMState *s) 48fcf5ef2aSThomas Huth { 49fcf5ef2aSThomas Huth /* MIPS has 128 signals */ 50fcf5ef2aSThomas Huth kvm_set_sigmask_len(s, 16); 51fcf5ef2aSThomas Huth 52fcf5ef2aSThomas Huth kvm_mips_fpu_cap = kvm_check_extension(s, KVM_CAP_MIPS_FPU); 53fcf5ef2aSThomas Huth kvm_mips_msa_cap = kvm_check_extension(s, KVM_CAP_MIPS_MSA); 54fcf5ef2aSThomas Huth 55fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 56fcf5ef2aSThomas Huth return 0; 57fcf5ef2aSThomas Huth } 58fcf5ef2aSThomas Huth 59d525ffabSPaolo Bonzini int kvm_arch_irqchip_create(MachineState *ms, KVMState *s) 60d525ffabSPaolo Bonzini { 61d525ffabSPaolo Bonzini return 0; 62d525ffabSPaolo Bonzini } 63d525ffabSPaolo Bonzini 64fcf5ef2aSThomas Huth int kvm_arch_init_vcpu(CPUState *cs) 65fcf5ef2aSThomas Huth { 66fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 67fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 68fcf5ef2aSThomas Huth int ret = 0; 69fcf5ef2aSThomas Huth 70fcf5ef2aSThomas Huth qemu_add_vm_change_state_handler(kvm_mips_update_state, cs); 71fcf5ef2aSThomas Huth 72fcf5ef2aSThomas Huth if (kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) { 73fcf5ef2aSThomas Huth ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_FPU, 0, 0); 74fcf5ef2aSThomas Huth if (ret < 0) { 75fcf5ef2aSThomas Huth /* mark unsupported so it gets disabled on reset */ 76fcf5ef2aSThomas Huth kvm_mips_fpu_cap = 0; 77fcf5ef2aSThomas Huth ret = 0; 78fcf5ef2aSThomas Huth } 79fcf5ef2aSThomas Huth } 80fcf5ef2aSThomas Huth 81fcf5ef2aSThomas Huth if (kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) { 82fcf5ef2aSThomas Huth ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0); 83fcf5ef2aSThomas Huth if (ret < 0) { 84fcf5ef2aSThomas Huth /* mark unsupported so it gets disabled on reset */ 85fcf5ef2aSThomas Huth kvm_mips_msa_cap = 0; 86fcf5ef2aSThomas Huth ret = 0; 87fcf5ef2aSThomas Huth } 88fcf5ef2aSThomas Huth } 89fcf5ef2aSThomas Huth 90fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 91fcf5ef2aSThomas Huth return ret; 92fcf5ef2aSThomas Huth } 93fcf5ef2aSThomas Huth 94fcf5ef2aSThomas Huth void kvm_mips_reset_vcpu(MIPSCPU *cpu) 95fcf5ef2aSThomas Huth { 96fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 97fcf5ef2aSThomas Huth 98fcf5ef2aSThomas Huth if (!kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) { 992ab4b135SAlistair Francis warn_report("KVM does not support FPU, disabling"); 100fcf5ef2aSThomas Huth env->CP0_Config1 &= ~(1 << CP0C1_FP); 101fcf5ef2aSThomas Huth } 102fcf5ef2aSThomas Huth if (!kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) { 1032ab4b135SAlistair Francis warn_report("KVM does not support MSA, disabling"); 104fcf5ef2aSThomas Huth env->CP0_Config3 &= ~(1 << CP0C3_MSAP); 105fcf5ef2aSThomas Huth } 106fcf5ef2aSThomas Huth 107fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 108fcf5ef2aSThomas Huth } 109fcf5ef2aSThomas Huth 110fcf5ef2aSThomas Huth int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 111fcf5ef2aSThomas Huth { 112fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 113fcf5ef2aSThomas Huth return 0; 114fcf5ef2aSThomas Huth } 115fcf5ef2aSThomas Huth 116fcf5ef2aSThomas Huth int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 117fcf5ef2aSThomas Huth { 118fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 119fcf5ef2aSThomas Huth return 0; 120fcf5ef2aSThomas Huth } 121fcf5ef2aSThomas Huth 122fcf5ef2aSThomas Huth static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu) 123fcf5ef2aSThomas Huth { 124fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP)); 127fcf5ef2aSThomas Huth } 128fcf5ef2aSThomas Huth 129fcf5ef2aSThomas Huth 130fcf5ef2aSThomas Huth void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 131fcf5ef2aSThomas Huth { 132fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 133fcf5ef2aSThomas Huth int r; 134fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 135fcf5ef2aSThomas Huth 136fcf5ef2aSThomas Huth qemu_mutex_lock_iothread(); 137fcf5ef2aSThomas Huth 138fcf5ef2aSThomas Huth if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 139fcf5ef2aSThomas Huth cpu_mips_io_interrupts_pending(cpu)) { 140fcf5ef2aSThomas Huth intr.cpu = -1; 141fcf5ef2aSThomas Huth intr.irq = 2; 142fcf5ef2aSThomas Huth r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 143fcf5ef2aSThomas Huth if (r < 0) { 144fcf5ef2aSThomas Huth error_report("%s: cpu %d: failed to inject IRQ %x", 145fcf5ef2aSThomas Huth __func__, cs->cpu_index, intr.irq); 146fcf5ef2aSThomas Huth } 147fcf5ef2aSThomas Huth } 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth qemu_mutex_unlock_iothread(); 150fcf5ef2aSThomas Huth } 151fcf5ef2aSThomas Huth 152fcf5ef2aSThomas Huth MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 153fcf5ef2aSThomas Huth { 154fcf5ef2aSThomas Huth return MEMTXATTRS_UNSPECIFIED; 155fcf5ef2aSThomas Huth } 156fcf5ef2aSThomas Huth 157fcf5ef2aSThomas Huth int kvm_arch_process_async_events(CPUState *cs) 158fcf5ef2aSThomas Huth { 159fcf5ef2aSThomas Huth return cs->halted; 160fcf5ef2aSThomas Huth } 161fcf5ef2aSThomas Huth 162fcf5ef2aSThomas Huth int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 163fcf5ef2aSThomas Huth { 164fcf5ef2aSThomas Huth int ret; 165fcf5ef2aSThomas Huth 166fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 167fcf5ef2aSThomas Huth switch (run->exit_reason) { 168fcf5ef2aSThomas Huth default: 169fcf5ef2aSThomas Huth error_report("%s: unknown exit reason %d", 170fcf5ef2aSThomas Huth __func__, run->exit_reason); 171fcf5ef2aSThomas Huth ret = -1; 172fcf5ef2aSThomas Huth break; 173fcf5ef2aSThomas Huth } 174fcf5ef2aSThomas Huth 175fcf5ef2aSThomas Huth return ret; 176fcf5ef2aSThomas Huth } 177fcf5ef2aSThomas Huth 178fcf5ef2aSThomas Huth bool kvm_arch_stop_on_emulation_error(CPUState *cs) 179fcf5ef2aSThomas Huth { 180fcf5ef2aSThomas Huth DPRINTF("%s\n", __func__); 181fcf5ef2aSThomas Huth return true; 182fcf5ef2aSThomas Huth } 183fcf5ef2aSThomas Huth 184fcf5ef2aSThomas Huth void kvm_arch_init_irq_routing(KVMState *s) 185fcf5ef2aSThomas Huth { 186fcf5ef2aSThomas Huth } 187fcf5ef2aSThomas Huth 188fcf5ef2aSThomas Huth int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level) 189fcf5ef2aSThomas Huth { 190fcf5ef2aSThomas Huth CPUState *cs = CPU(cpu); 191fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 192fcf5ef2aSThomas Huth 193fcf5ef2aSThomas Huth if (!kvm_enabled()) { 194fcf5ef2aSThomas Huth return 0; 195fcf5ef2aSThomas Huth } 196fcf5ef2aSThomas Huth 197fcf5ef2aSThomas Huth intr.cpu = -1; 198fcf5ef2aSThomas Huth 199fcf5ef2aSThomas Huth if (level) { 200fcf5ef2aSThomas Huth intr.irq = irq; 201fcf5ef2aSThomas Huth } else { 202fcf5ef2aSThomas Huth intr.irq = -irq; 203fcf5ef2aSThomas Huth } 204fcf5ef2aSThomas Huth 205fcf5ef2aSThomas Huth kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 206fcf5ef2aSThomas Huth 207fcf5ef2aSThomas Huth return 0; 208fcf5ef2aSThomas Huth } 209fcf5ef2aSThomas Huth 210fcf5ef2aSThomas Huth int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) 211fcf5ef2aSThomas Huth { 212fcf5ef2aSThomas Huth CPUState *cs = current_cpu; 213fcf5ef2aSThomas Huth CPUState *dest_cs = CPU(cpu); 214fcf5ef2aSThomas Huth struct kvm_mips_interrupt intr; 215fcf5ef2aSThomas Huth 216fcf5ef2aSThomas Huth if (!kvm_enabled()) { 217fcf5ef2aSThomas Huth return 0; 218fcf5ef2aSThomas Huth } 219fcf5ef2aSThomas Huth 220fcf5ef2aSThomas Huth intr.cpu = dest_cs->cpu_index; 221fcf5ef2aSThomas Huth 222fcf5ef2aSThomas Huth if (level) { 223fcf5ef2aSThomas Huth intr.irq = irq; 224fcf5ef2aSThomas Huth } else { 225fcf5ef2aSThomas Huth intr.irq = -irq; 226fcf5ef2aSThomas Huth } 227fcf5ef2aSThomas Huth 228fcf5ef2aSThomas Huth DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq); 229fcf5ef2aSThomas Huth 230fcf5ef2aSThomas Huth kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); 231fcf5ef2aSThomas Huth 232fcf5ef2aSThomas Huth return 0; 233fcf5ef2aSThomas Huth } 234fcf5ef2aSThomas Huth 235fcf5ef2aSThomas Huth #define MIPS_CP0_32(_R, _S) \ 236fcf5ef2aSThomas Huth (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S))) 237fcf5ef2aSThomas Huth 238fcf5ef2aSThomas Huth #define MIPS_CP0_64(_R, _S) \ 239fcf5ef2aSThomas Huth (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) 240fcf5ef2aSThomas Huth 241fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) 242fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) 243fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) 244fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) 245fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) 246fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) 247fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) 248fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) 249fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) 250fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) 251fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) 252fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) 253fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) 254fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) 255fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) 256fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) 257fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) 258fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) 259fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) 260fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) 261fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) 262fcf5ef2aSThomas Huth 263fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, 264fcf5ef2aSThomas Huth int32_t *addr) 265fcf5ef2aSThomas Huth { 266fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 267fcf5ef2aSThomas Huth .id = reg_id, 268fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 269fcf5ef2aSThomas Huth }; 270fcf5ef2aSThomas Huth 271fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 272fcf5ef2aSThomas Huth } 273fcf5ef2aSThomas Huth 274fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ureg(CPUState *cs, uint64_t reg_id, 275fcf5ef2aSThomas Huth uint32_t *addr) 276fcf5ef2aSThomas Huth { 277fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 278fcf5ef2aSThomas Huth .id = reg_id, 279fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 280fcf5ef2aSThomas Huth }; 281fcf5ef2aSThomas Huth 282fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 283fcf5ef2aSThomas Huth } 284fcf5ef2aSThomas Huth 285fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id, 286fcf5ef2aSThomas Huth target_ulong *addr) 287fcf5ef2aSThomas Huth { 288fcf5ef2aSThomas Huth uint64_t val64 = *addr; 289fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 290fcf5ef2aSThomas Huth .id = reg_id, 291fcf5ef2aSThomas Huth .addr = (uintptr_t)&val64 292fcf5ef2aSThomas Huth }; 293fcf5ef2aSThomas Huth 294fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 295fcf5ef2aSThomas Huth } 296fcf5ef2aSThomas Huth 297fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id, 298fcf5ef2aSThomas Huth int64_t *addr) 299fcf5ef2aSThomas Huth { 300fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 301fcf5ef2aSThomas Huth .id = reg_id, 302fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 303fcf5ef2aSThomas Huth }; 304fcf5ef2aSThomas Huth 305fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 306fcf5ef2aSThomas Huth } 307fcf5ef2aSThomas Huth 308fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ureg64(CPUState *cs, uint64_t reg_id, 309fcf5ef2aSThomas Huth uint64_t *addr) 310fcf5ef2aSThomas Huth { 311fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 312fcf5ef2aSThomas Huth .id = reg_id, 313fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 314fcf5ef2aSThomas Huth }; 315fcf5ef2aSThomas Huth 316fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); 317fcf5ef2aSThomas Huth } 318fcf5ef2aSThomas Huth 319fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id, 320fcf5ef2aSThomas Huth int32_t *addr) 321fcf5ef2aSThomas Huth { 322fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 323fcf5ef2aSThomas Huth .id = reg_id, 324fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 325fcf5ef2aSThomas Huth }; 326fcf5ef2aSThomas Huth 327fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 328fcf5ef2aSThomas Huth } 329fcf5ef2aSThomas Huth 330fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ureg(CPUState *cs, uint64_t reg_id, 331fcf5ef2aSThomas Huth uint32_t *addr) 332fcf5ef2aSThomas Huth { 333fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 334fcf5ef2aSThomas Huth .id = reg_id, 335fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 336fcf5ef2aSThomas Huth }; 337fcf5ef2aSThomas Huth 338fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 339fcf5ef2aSThomas Huth } 340fcf5ef2aSThomas Huth 341fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64_t reg_id, 342fcf5ef2aSThomas Huth target_ulong *addr) 343fcf5ef2aSThomas Huth { 344fcf5ef2aSThomas Huth int ret; 345fcf5ef2aSThomas Huth uint64_t val64 = 0; 346fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 347fcf5ef2aSThomas Huth .id = reg_id, 348fcf5ef2aSThomas Huth .addr = (uintptr_t)&val64 349fcf5ef2aSThomas Huth }; 350fcf5ef2aSThomas Huth 351fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 352fcf5ef2aSThomas Huth if (ret >= 0) { 353fcf5ef2aSThomas Huth *addr = val64; 354fcf5ef2aSThomas Huth } 355fcf5ef2aSThomas Huth return ret; 356fcf5ef2aSThomas Huth } 357fcf5ef2aSThomas Huth 358fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64_t reg_id, 359fcf5ef2aSThomas Huth int64_t *addr) 360fcf5ef2aSThomas Huth { 361fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 362fcf5ef2aSThomas Huth .id = reg_id, 363fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 364fcf5ef2aSThomas Huth }; 365fcf5ef2aSThomas Huth 366fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 367fcf5ef2aSThomas Huth } 368fcf5ef2aSThomas Huth 369fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ureg64(CPUState *cs, uint64_t reg_id, 370fcf5ef2aSThomas Huth uint64_t *addr) 371fcf5ef2aSThomas Huth { 372fcf5ef2aSThomas Huth struct kvm_one_reg cp0reg = { 373fcf5ef2aSThomas Huth .id = reg_id, 374fcf5ef2aSThomas Huth .addr = (uintptr_t)addr 375fcf5ef2aSThomas Huth }; 376fcf5ef2aSThomas Huth 377fcf5ef2aSThomas Huth return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); 378fcf5ef2aSThomas Huth } 379fcf5ef2aSThomas Huth 380fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG_MASK (1U << CP0C0_M) 381fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG1_MASK ((1U << CP0C1_M) | \ 382fcf5ef2aSThomas Huth (1U << CP0C1_FP)) 383fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG2_MASK (1U << CP0C2_M) 384fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG3_MASK ((1U << CP0C3_M) | \ 385fcf5ef2aSThomas Huth (1U << CP0C3_MSAP)) 386fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG4_MASK (1U << CP0C4_M) 387fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG5_MASK ((1U << CP0C5_MSAEn) | \ 388fcf5ef2aSThomas Huth (1U << CP0C5_UFE) | \ 389fcf5ef2aSThomas Huth (1U << CP0C5_FRE) | \ 390fcf5ef2aSThomas Huth (1U << CP0C5_UFR)) 391fcf5ef2aSThomas Huth 392fcf5ef2aSThomas Huth static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id, 393fcf5ef2aSThomas Huth int32_t *addr, int32_t mask) 394fcf5ef2aSThomas Huth { 395fcf5ef2aSThomas Huth int err; 396fcf5ef2aSThomas Huth int32_t tmp, change; 397fcf5ef2aSThomas Huth 398fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, reg_id, &tmp); 399fcf5ef2aSThomas Huth if (err < 0) { 400fcf5ef2aSThomas Huth return err; 401fcf5ef2aSThomas Huth } 402fcf5ef2aSThomas Huth 403fcf5ef2aSThomas Huth /* only change bits in mask */ 404fcf5ef2aSThomas Huth change = (*addr ^ tmp) & mask; 405fcf5ef2aSThomas Huth if (!change) { 406fcf5ef2aSThomas Huth return 0; 407fcf5ef2aSThomas Huth } 408fcf5ef2aSThomas Huth 409fcf5ef2aSThomas Huth tmp = tmp ^ change; 410fcf5ef2aSThomas Huth return kvm_mips_put_one_reg(cs, reg_id, &tmp); 411fcf5ef2aSThomas Huth } 412fcf5ef2aSThomas Huth 413fcf5ef2aSThomas Huth /* 414fcf5ef2aSThomas Huth * We freeze the KVM timer when either the VM clock is stopped or the state is 415fcf5ef2aSThomas Huth * saved (the state is dirty). 416fcf5ef2aSThomas Huth */ 417fcf5ef2aSThomas Huth 418fcf5ef2aSThomas Huth /* 419fcf5ef2aSThomas Huth * Save the state of the KVM timer when VM clock is stopped or state is synced 420fcf5ef2aSThomas Huth * to QEMU. 421fcf5ef2aSThomas Huth */ 422fcf5ef2aSThomas Huth static int kvm_mips_save_count(CPUState *cs) 423fcf5ef2aSThomas Huth { 424fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 425fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 426fcf5ef2aSThomas Huth uint64_t count_ctl; 427fcf5ef2aSThomas Huth int err, ret = 0; 428fcf5ef2aSThomas Huth 429fcf5ef2aSThomas Huth /* freeze KVM timer */ 430fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 431fcf5ef2aSThomas Huth if (err < 0) { 432fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err); 433fcf5ef2aSThomas Huth ret = err; 434fcf5ef2aSThomas Huth } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) { 435fcf5ef2aSThomas Huth count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC; 436fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 437fcf5ef2aSThomas Huth if (err < 0) { 438fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err); 439fcf5ef2aSThomas Huth ret = err; 440fcf5ef2aSThomas Huth } 441fcf5ef2aSThomas Huth } 442fcf5ef2aSThomas Huth 443fcf5ef2aSThomas Huth /* read CP0_Cause */ 444fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause); 445fcf5ef2aSThomas Huth if (err < 0) { 446fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err); 447fcf5ef2aSThomas Huth ret = err; 448fcf5ef2aSThomas Huth } 449fcf5ef2aSThomas Huth 450fcf5ef2aSThomas Huth /* read CP0_Count */ 451fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count); 452fcf5ef2aSThomas Huth if (err < 0) { 453fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err); 454fcf5ef2aSThomas Huth ret = err; 455fcf5ef2aSThomas Huth } 456fcf5ef2aSThomas Huth 457fcf5ef2aSThomas Huth return ret; 458fcf5ef2aSThomas Huth } 459fcf5ef2aSThomas Huth 460fcf5ef2aSThomas Huth /* 461fcf5ef2aSThomas Huth * Restore the state of the KVM timer when VM clock is restarted or state is 462fcf5ef2aSThomas Huth * synced to KVM. 463fcf5ef2aSThomas Huth */ 464fcf5ef2aSThomas Huth static int kvm_mips_restore_count(CPUState *cs) 465fcf5ef2aSThomas Huth { 466fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 467fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 468fcf5ef2aSThomas Huth uint64_t count_ctl; 469fcf5ef2aSThomas Huth int err_dc, err, ret = 0; 470fcf5ef2aSThomas Huth 471fcf5ef2aSThomas Huth /* check the timer is frozen */ 472fcf5ef2aSThomas Huth err_dc = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 473fcf5ef2aSThomas Huth if (err_dc < 0) { 474fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc); 475fcf5ef2aSThomas Huth ret = err_dc; 476fcf5ef2aSThomas Huth } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) { 477fcf5ef2aSThomas Huth /* freeze timer (sets COUNT_RESUME for us) */ 478fcf5ef2aSThomas Huth count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC; 479fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 480fcf5ef2aSThomas Huth if (err < 0) { 481fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err); 482fcf5ef2aSThomas Huth ret = err; 483fcf5ef2aSThomas Huth } 484fcf5ef2aSThomas Huth } 485fcf5ef2aSThomas Huth 486fcf5ef2aSThomas Huth /* load CP0_Cause */ 487fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause); 488fcf5ef2aSThomas Huth if (err < 0) { 489fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err); 490fcf5ef2aSThomas Huth ret = err; 491fcf5ef2aSThomas Huth } 492fcf5ef2aSThomas Huth 493fcf5ef2aSThomas Huth /* load CP0_Count */ 494fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count); 495fcf5ef2aSThomas Huth if (err < 0) { 496fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err); 497fcf5ef2aSThomas Huth ret = err; 498fcf5ef2aSThomas Huth } 499fcf5ef2aSThomas Huth 500fcf5ef2aSThomas Huth /* resume KVM timer */ 501fcf5ef2aSThomas Huth if (err_dc >= 0) { 502fcf5ef2aSThomas Huth count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC; 503fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); 504fcf5ef2aSThomas Huth if (err < 0) { 505fcf5ef2aSThomas Huth DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err); 506fcf5ef2aSThomas Huth ret = err; 507fcf5ef2aSThomas Huth } 508fcf5ef2aSThomas Huth } 509fcf5ef2aSThomas Huth 510fcf5ef2aSThomas Huth return ret; 511fcf5ef2aSThomas Huth } 512fcf5ef2aSThomas Huth 513fcf5ef2aSThomas Huth /* 514fcf5ef2aSThomas Huth * Handle the VM clock being started or stopped 515fcf5ef2aSThomas Huth */ 516fcf5ef2aSThomas Huth static void kvm_mips_update_state(void *opaque, int running, RunState state) 517fcf5ef2aSThomas Huth { 518fcf5ef2aSThomas Huth CPUState *cs = opaque; 519fcf5ef2aSThomas Huth int ret; 520fcf5ef2aSThomas Huth uint64_t count_resume; 521fcf5ef2aSThomas Huth 522fcf5ef2aSThomas Huth /* 523fcf5ef2aSThomas Huth * If state is already dirty (synced to QEMU) then the KVM timer state is 524fcf5ef2aSThomas Huth * already saved and can be restored when it is synced back to KVM. 525fcf5ef2aSThomas Huth */ 526fcf5ef2aSThomas Huth if (!running) { 52799f31832SSergio Andres Gomez Del Real if (!cs->vcpu_dirty) { 528fcf5ef2aSThomas Huth ret = kvm_mips_save_count(cs); 529fcf5ef2aSThomas Huth if (ret < 0) { 530288cb949SAlistair Francis warn_report("Failed saving count"); 531fcf5ef2aSThomas Huth } 532fcf5ef2aSThomas Huth } 533fcf5ef2aSThomas Huth } else { 534fcf5ef2aSThomas Huth /* Set clock restore time to now */ 535fcf5ef2aSThomas Huth count_resume = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 536fcf5ef2aSThomas Huth ret = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_RESUME, 537fcf5ef2aSThomas Huth &count_resume); 538fcf5ef2aSThomas Huth if (ret < 0) { 539288cb949SAlistair Francis warn_report("Failed setting COUNT_RESUME"); 540fcf5ef2aSThomas Huth return; 541fcf5ef2aSThomas Huth } 542fcf5ef2aSThomas Huth 54399f31832SSergio Andres Gomez Del Real if (!cs->vcpu_dirty) { 544fcf5ef2aSThomas Huth ret = kvm_mips_restore_count(cs); 545fcf5ef2aSThomas Huth if (ret < 0) { 546288cb949SAlistair Francis warn_report("Failed restoring count"); 547fcf5ef2aSThomas Huth } 548fcf5ef2aSThomas Huth } 549fcf5ef2aSThomas Huth } 550fcf5ef2aSThomas Huth } 551fcf5ef2aSThomas Huth 552fcf5ef2aSThomas Huth static int kvm_mips_put_fpu_registers(CPUState *cs, int level) 553fcf5ef2aSThomas Huth { 554fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 555fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 556fcf5ef2aSThomas Huth int err, ret = 0; 557fcf5ef2aSThomas Huth unsigned int i; 558fcf5ef2aSThomas Huth 559fcf5ef2aSThomas Huth /* Only put FPU state if we're emulating a CPU with an FPU */ 560fcf5ef2aSThomas Huth if (env->CP0_Config1 & (1 << CP0C1_FP)) { 561fcf5ef2aSThomas Huth /* FPU Control Registers */ 562fcf5ef2aSThomas Huth if (level == KVM_PUT_FULL_STATE) { 563fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg(cs, KVM_REG_MIPS_FCR_IR, 564fcf5ef2aSThomas Huth &env->active_fpu.fcr0); 565fcf5ef2aSThomas Huth if (err < 0) { 566fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FCR_IR (%d)\n", __func__, err); 567fcf5ef2aSThomas Huth ret = err; 568fcf5ef2aSThomas Huth } 569fcf5ef2aSThomas Huth } 570fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg(cs, KVM_REG_MIPS_FCR_CSR, 571fcf5ef2aSThomas Huth &env->active_fpu.fcr31); 572fcf5ef2aSThomas Huth if (err < 0) { 573fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FCR_CSR (%d)\n", __func__, err); 574fcf5ef2aSThomas Huth ret = err; 575fcf5ef2aSThomas Huth } 576fcf5ef2aSThomas Huth 577fcf5ef2aSThomas Huth /* 578fcf5ef2aSThomas Huth * FPU register state is a subset of MSA vector state, so don't put FPU 579fcf5ef2aSThomas Huth * registers if we're emulating a CPU with MSA. 580fcf5ef2aSThomas Huth */ 581fcf5ef2aSThomas Huth if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { 582fcf5ef2aSThomas Huth /* Floating point registers */ 583fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 584fcf5ef2aSThomas Huth if (env->CP0_Status & (1 << CP0St_FR)) { 585fcf5ef2aSThomas Huth err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i), 586fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].d); 587fcf5ef2aSThomas Huth } else { 588fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i), 589fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); 590fcf5ef2aSThomas Huth } 591fcf5ef2aSThomas Huth if (err < 0) { 592fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put FPR%u (%d)\n", __func__, i, err); 593fcf5ef2aSThomas Huth ret = err; 594fcf5ef2aSThomas Huth } 595fcf5ef2aSThomas Huth } 596fcf5ef2aSThomas Huth } 597fcf5ef2aSThomas Huth } 598fcf5ef2aSThomas Huth 599fcf5ef2aSThomas Huth /* Only put MSA state if we're emulating a CPU with MSA */ 600fcf5ef2aSThomas Huth if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { 601fcf5ef2aSThomas Huth /* MSA Control Registers */ 602fcf5ef2aSThomas Huth if (level == KVM_PUT_FULL_STATE) { 603fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_IR, 604fcf5ef2aSThomas Huth &env->msair); 605fcf5ef2aSThomas Huth if (err < 0) { 606fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put MSA_IR (%d)\n", __func__, err); 607fcf5ef2aSThomas Huth ret = err; 608fcf5ef2aSThomas Huth } 609fcf5ef2aSThomas Huth } 610fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_CSR, 611fcf5ef2aSThomas Huth &env->active_tc.msacsr); 612fcf5ef2aSThomas Huth if (err < 0) { 613fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put MSA_CSR (%d)\n", __func__, err); 614fcf5ef2aSThomas Huth ret = err; 615fcf5ef2aSThomas Huth } 616fcf5ef2aSThomas Huth 617fcf5ef2aSThomas Huth /* Vector registers (includes FP registers) */ 618fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 619fcf5ef2aSThomas Huth /* Big endian MSA not supported by QEMU yet anyway */ 620fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_VEC_128(i), 621fcf5ef2aSThomas Huth env->active_fpu.fpr[i].wr.d); 622fcf5ef2aSThomas Huth if (err < 0) { 623fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put VEC%u (%d)\n", __func__, i, err); 624fcf5ef2aSThomas Huth ret = err; 625fcf5ef2aSThomas Huth } 626fcf5ef2aSThomas Huth } 627fcf5ef2aSThomas Huth } 628fcf5ef2aSThomas Huth 629fcf5ef2aSThomas Huth return ret; 630fcf5ef2aSThomas Huth } 631fcf5ef2aSThomas Huth 632fcf5ef2aSThomas Huth static int kvm_mips_get_fpu_registers(CPUState *cs) 633fcf5ef2aSThomas Huth { 634fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 635fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 636fcf5ef2aSThomas Huth int err, ret = 0; 637fcf5ef2aSThomas Huth unsigned int i; 638fcf5ef2aSThomas Huth 639fcf5ef2aSThomas Huth /* Only get FPU state if we're emulating a CPU with an FPU */ 640fcf5ef2aSThomas Huth if (env->CP0_Config1 & (1 << CP0C1_FP)) { 641fcf5ef2aSThomas Huth /* FPU Control Registers */ 642fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_IR, 643fcf5ef2aSThomas Huth &env->active_fpu.fcr0); 644fcf5ef2aSThomas Huth if (err < 0) { 645fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FCR_IR (%d)\n", __func__, err); 646fcf5ef2aSThomas Huth ret = err; 647fcf5ef2aSThomas Huth } 648fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_CSR, 649fcf5ef2aSThomas Huth &env->active_fpu.fcr31); 650fcf5ef2aSThomas Huth if (err < 0) { 651fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FCR_CSR (%d)\n", __func__, err); 652fcf5ef2aSThomas Huth ret = err; 653fcf5ef2aSThomas Huth } else { 654fcf5ef2aSThomas Huth restore_fp_status(env); 655fcf5ef2aSThomas Huth } 656fcf5ef2aSThomas Huth 657fcf5ef2aSThomas Huth /* 658fcf5ef2aSThomas Huth * FPU register state is a subset of MSA vector state, so don't save FPU 659fcf5ef2aSThomas Huth * registers if we're emulating a CPU with MSA. 660fcf5ef2aSThomas Huth */ 661fcf5ef2aSThomas Huth if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { 662fcf5ef2aSThomas Huth /* Floating point registers */ 663fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 664fcf5ef2aSThomas Huth if (env->CP0_Status & (1 << CP0St_FR)) { 665fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i), 666fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].d); 667fcf5ef2aSThomas Huth } else { 668fcf5ef2aSThomas Huth err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i), 669fcf5ef2aSThomas Huth &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); 670fcf5ef2aSThomas Huth } 671fcf5ef2aSThomas Huth if (err < 0) { 672fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__, i, err); 673fcf5ef2aSThomas Huth ret = err; 674fcf5ef2aSThomas Huth } 675fcf5ef2aSThomas Huth } 676fcf5ef2aSThomas Huth } 677fcf5ef2aSThomas Huth } 678fcf5ef2aSThomas Huth 679fcf5ef2aSThomas Huth /* Only get MSA state if we're emulating a CPU with MSA */ 680fcf5ef2aSThomas Huth if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { 681fcf5ef2aSThomas Huth /* MSA Control Registers */ 682fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR, 683fcf5ef2aSThomas Huth &env->msair); 684fcf5ef2aSThomas Huth if (err < 0) { 685fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get MSA_IR (%d)\n", __func__, err); 686fcf5ef2aSThomas Huth ret = err; 687fcf5ef2aSThomas Huth } 688fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_CSR, 689fcf5ef2aSThomas Huth &env->active_tc.msacsr); 690fcf5ef2aSThomas Huth if (err < 0) { 691fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get MSA_CSR (%d)\n", __func__, err); 692fcf5ef2aSThomas Huth ret = err; 693fcf5ef2aSThomas Huth } else { 694fcf5ef2aSThomas Huth restore_msa_fp_status(env); 695fcf5ef2aSThomas Huth } 696fcf5ef2aSThomas Huth 697fcf5ef2aSThomas Huth /* Vector registers (includes FP registers) */ 698fcf5ef2aSThomas Huth for (i = 0; i < 32; ++i) { 699fcf5ef2aSThomas Huth /* Big endian MSA not supported by QEMU yet anyway */ 700fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_VEC_128(i), 701fcf5ef2aSThomas Huth env->active_fpu.fpr[i].wr.d); 702fcf5ef2aSThomas Huth if (err < 0) { 703fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get VEC%u (%d)\n", __func__, i, err); 704fcf5ef2aSThomas Huth ret = err; 705fcf5ef2aSThomas Huth } 706fcf5ef2aSThomas Huth } 707fcf5ef2aSThomas Huth } 708fcf5ef2aSThomas Huth 709fcf5ef2aSThomas Huth return ret; 710fcf5ef2aSThomas Huth } 711fcf5ef2aSThomas Huth 712fcf5ef2aSThomas Huth 713fcf5ef2aSThomas Huth static int kvm_mips_put_cp0_registers(CPUState *cs, int level) 714fcf5ef2aSThomas Huth { 715fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 716fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 717fcf5ef2aSThomas Huth int err, ret = 0; 718fcf5ef2aSThomas Huth 719fcf5ef2aSThomas Huth (void)level; 720fcf5ef2aSThomas Huth 721fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); 722fcf5ef2aSThomas Huth if (err < 0) { 723fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err); 724fcf5ef2aSThomas Huth ret = err; 725fcf5ef2aSThomas Huth } 726fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, 727fcf5ef2aSThomas Huth &env->CP0_Context); 728fcf5ef2aSThomas Huth if (err < 0) { 729fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err); 730fcf5ef2aSThomas Huth ret = err; 731fcf5ef2aSThomas Huth } 732fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL, 733fcf5ef2aSThomas Huth &env->active_tc.CP0_UserLocal); 734fcf5ef2aSThomas Huth if (err < 0) { 735fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err); 736fcf5ef2aSThomas Huth ret = err; 737fcf5ef2aSThomas Huth } 738fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK, 739fcf5ef2aSThomas Huth &env->CP0_PageMask); 740fcf5ef2aSThomas Huth if (err < 0) { 741fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err); 742fcf5ef2aSThomas Huth ret = err; 743fcf5ef2aSThomas Huth } 744fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); 745fcf5ef2aSThomas Huth if (err < 0) { 746fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err); 747fcf5ef2aSThomas Huth ret = err; 748fcf5ef2aSThomas Huth } 749fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); 750fcf5ef2aSThomas Huth if (err < 0) { 751fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err); 752fcf5ef2aSThomas Huth ret = err; 753fcf5ef2aSThomas Huth } 754fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR, 755fcf5ef2aSThomas Huth &env->CP0_BadVAddr); 756fcf5ef2aSThomas Huth if (err < 0) { 757fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err); 758fcf5ef2aSThomas Huth ret = err; 759fcf5ef2aSThomas Huth } 760fcf5ef2aSThomas Huth 761fcf5ef2aSThomas Huth /* If VM clock stopped then state will be restored when it is restarted */ 762fcf5ef2aSThomas Huth if (runstate_is_running()) { 763fcf5ef2aSThomas Huth err = kvm_mips_restore_count(cs); 764fcf5ef2aSThomas Huth if (err < 0) { 765fcf5ef2aSThomas Huth ret = err; 766fcf5ef2aSThomas Huth } 767fcf5ef2aSThomas Huth } 768fcf5ef2aSThomas Huth 769fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI, 770fcf5ef2aSThomas Huth &env->CP0_EntryHi); 771fcf5ef2aSThomas Huth if (err < 0) { 772fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err); 773fcf5ef2aSThomas Huth ret = err; 774fcf5ef2aSThomas Huth } 775fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE, 776fcf5ef2aSThomas Huth &env->CP0_Compare); 777fcf5ef2aSThomas Huth if (err < 0) { 778fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err); 779fcf5ef2aSThomas Huth ret = err; 780fcf5ef2aSThomas Huth } 781fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status); 782fcf5ef2aSThomas Huth if (err < 0) { 783fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err); 784fcf5ef2aSThomas Huth ret = err; 785fcf5ef2aSThomas Huth } 786fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC); 787fcf5ef2aSThomas Huth if (err < 0) { 788fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err); 789fcf5ef2aSThomas Huth ret = err; 790fcf5ef2aSThomas Huth } 791fcf5ef2aSThomas Huth err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); 792fcf5ef2aSThomas Huth if (err < 0) { 793fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err); 794fcf5ef2aSThomas Huth ret = err; 795fcf5ef2aSThomas Huth } 796fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, 797fcf5ef2aSThomas Huth &env->CP0_Config0, 798fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG_MASK); 799fcf5ef2aSThomas Huth if (err < 0) { 800fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG (%d)\n", __func__, err); 801fcf5ef2aSThomas Huth ret = err; 802fcf5ef2aSThomas Huth } 803fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, 804fcf5ef2aSThomas Huth &env->CP0_Config1, 805fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG1_MASK); 806fcf5ef2aSThomas Huth if (err < 0) { 807fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG1 (%d)\n", __func__, err); 808fcf5ef2aSThomas Huth ret = err; 809fcf5ef2aSThomas Huth } 810fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2, 811fcf5ef2aSThomas Huth &env->CP0_Config2, 812fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG2_MASK); 813fcf5ef2aSThomas Huth if (err < 0) { 814fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG2 (%d)\n", __func__, err); 815fcf5ef2aSThomas Huth ret = err; 816fcf5ef2aSThomas Huth } 817fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3, 818fcf5ef2aSThomas Huth &env->CP0_Config3, 819fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG3_MASK); 820fcf5ef2aSThomas Huth if (err < 0) { 821fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG3 (%d)\n", __func__, err); 822fcf5ef2aSThomas Huth ret = err; 823fcf5ef2aSThomas Huth } 824fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4, 825fcf5ef2aSThomas Huth &env->CP0_Config4, 826fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG4_MASK); 827fcf5ef2aSThomas Huth if (err < 0) { 828fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG4 (%d)\n", __func__, err); 829fcf5ef2aSThomas Huth ret = err; 830fcf5ef2aSThomas Huth } 831fcf5ef2aSThomas Huth err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, 832fcf5ef2aSThomas Huth &env->CP0_Config5, 833fcf5ef2aSThomas Huth KVM_REG_MIPS_CP0_CONFIG5_MASK); 834fcf5ef2aSThomas Huth if (err < 0) { 835fcf5ef2aSThomas Huth DPRINTF("%s: Failed to change CP0_CONFIG5 (%d)\n", __func__, err); 836fcf5ef2aSThomas Huth ret = err; 837fcf5ef2aSThomas Huth } 838fcf5ef2aSThomas Huth err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, 839fcf5ef2aSThomas Huth &env->CP0_ErrorEPC); 840fcf5ef2aSThomas Huth if (err < 0) { 841fcf5ef2aSThomas Huth DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err); 842fcf5ef2aSThomas Huth ret = err; 843fcf5ef2aSThomas Huth } 844fcf5ef2aSThomas Huth 845fcf5ef2aSThomas Huth return ret; 846fcf5ef2aSThomas Huth } 847fcf5ef2aSThomas Huth 848fcf5ef2aSThomas Huth static int kvm_mips_get_cp0_registers(CPUState *cs) 849fcf5ef2aSThomas Huth { 850fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 851fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 852fcf5ef2aSThomas Huth int err, ret = 0; 853fcf5ef2aSThomas Huth 854fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); 855fcf5ef2aSThomas Huth if (err < 0) { 856fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err); 857fcf5ef2aSThomas Huth ret = err; 858fcf5ef2aSThomas Huth } 859fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, 860fcf5ef2aSThomas Huth &env->CP0_Context); 861fcf5ef2aSThomas Huth if (err < 0) { 862fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err); 863fcf5ef2aSThomas Huth ret = err; 864fcf5ef2aSThomas Huth } 865fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL, 866fcf5ef2aSThomas Huth &env->active_tc.CP0_UserLocal); 867fcf5ef2aSThomas Huth if (err < 0) { 868fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err); 869fcf5ef2aSThomas Huth ret = err; 870fcf5ef2aSThomas Huth } 871fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK, 872fcf5ef2aSThomas Huth &env->CP0_PageMask); 873fcf5ef2aSThomas Huth if (err < 0) { 874fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err); 875fcf5ef2aSThomas Huth ret = err; 876fcf5ef2aSThomas Huth } 877fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); 878fcf5ef2aSThomas Huth if (err < 0) { 879fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err); 880fcf5ef2aSThomas Huth ret = err; 881fcf5ef2aSThomas Huth } 882fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); 883fcf5ef2aSThomas Huth if (err < 0) { 884fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err); 885fcf5ef2aSThomas Huth ret = err; 886fcf5ef2aSThomas Huth } 887fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR, 888fcf5ef2aSThomas Huth &env->CP0_BadVAddr); 889fcf5ef2aSThomas Huth if (err < 0) { 890fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err); 891fcf5ef2aSThomas Huth ret = err; 892fcf5ef2aSThomas Huth } 893fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI, 894fcf5ef2aSThomas Huth &env->CP0_EntryHi); 895fcf5ef2aSThomas Huth if (err < 0) { 896fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err); 897fcf5ef2aSThomas Huth ret = err; 898fcf5ef2aSThomas Huth } 899fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE, 900fcf5ef2aSThomas Huth &env->CP0_Compare); 901fcf5ef2aSThomas Huth if (err < 0) { 902fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err); 903fcf5ef2aSThomas Huth ret = err; 904fcf5ef2aSThomas Huth } 905fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status); 906fcf5ef2aSThomas Huth if (err < 0) { 907fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err); 908fcf5ef2aSThomas Huth ret = err; 909fcf5ef2aSThomas Huth } 910fcf5ef2aSThomas Huth 911fcf5ef2aSThomas Huth /* If VM clock stopped then state was already saved when it was stopped */ 912fcf5ef2aSThomas Huth if (runstate_is_running()) { 913fcf5ef2aSThomas Huth err = kvm_mips_save_count(cs); 914fcf5ef2aSThomas Huth if (err < 0) { 915fcf5ef2aSThomas Huth ret = err; 916fcf5ef2aSThomas Huth } 917fcf5ef2aSThomas Huth } 918fcf5ef2aSThomas Huth 919fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC); 920fcf5ef2aSThomas Huth if (err < 0) { 921fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err); 922fcf5ef2aSThomas Huth ret = err; 923fcf5ef2aSThomas Huth } 924fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); 925fcf5ef2aSThomas Huth if (err < 0) { 926fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err); 927fcf5ef2aSThomas Huth ret = err; 928fcf5ef2aSThomas Huth } 929fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, &env->CP0_Config0); 930fcf5ef2aSThomas Huth if (err < 0) { 931fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG (%d)\n", __func__, err); 932fcf5ef2aSThomas Huth ret = err; 933fcf5ef2aSThomas Huth } 934fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, &env->CP0_Config1); 935fcf5ef2aSThomas Huth if (err < 0) { 936fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG1 (%d)\n", __func__, err); 937fcf5ef2aSThomas Huth ret = err; 938fcf5ef2aSThomas Huth } 939fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2, &env->CP0_Config2); 940fcf5ef2aSThomas Huth if (err < 0) { 941fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG2 (%d)\n", __func__, err); 942fcf5ef2aSThomas Huth ret = err; 943fcf5ef2aSThomas Huth } 944fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3, &env->CP0_Config3); 945fcf5ef2aSThomas Huth if (err < 0) { 946fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG3 (%d)\n", __func__, err); 947fcf5ef2aSThomas Huth ret = err; 948fcf5ef2aSThomas Huth } 949fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4, &env->CP0_Config4); 950fcf5ef2aSThomas Huth if (err < 0) { 951fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG4 (%d)\n", __func__, err); 952fcf5ef2aSThomas Huth ret = err; 953fcf5ef2aSThomas Huth } 954fcf5ef2aSThomas Huth err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, &env->CP0_Config5); 955fcf5ef2aSThomas Huth if (err < 0) { 956fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_CONFIG5 (%d)\n", __func__, err); 957fcf5ef2aSThomas Huth ret = err; 958fcf5ef2aSThomas Huth } 959fcf5ef2aSThomas Huth err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, 960fcf5ef2aSThomas Huth &env->CP0_ErrorEPC); 961fcf5ef2aSThomas Huth if (err < 0) { 962fcf5ef2aSThomas Huth DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err); 963fcf5ef2aSThomas Huth ret = err; 964fcf5ef2aSThomas Huth } 965fcf5ef2aSThomas Huth 966fcf5ef2aSThomas Huth return ret; 967fcf5ef2aSThomas Huth } 968fcf5ef2aSThomas Huth 969fcf5ef2aSThomas Huth int kvm_arch_put_registers(CPUState *cs, int level) 970fcf5ef2aSThomas Huth { 971fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 972fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 973fcf5ef2aSThomas Huth struct kvm_regs regs; 974fcf5ef2aSThomas Huth int ret; 975fcf5ef2aSThomas Huth int i; 976fcf5ef2aSThomas Huth 977fcf5ef2aSThomas Huth /* Set the registers based on QEMU's view of things */ 978fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 979fcf5ef2aSThomas Huth regs.gpr[i] = (int64_t)(target_long)env->active_tc.gpr[i]; 980fcf5ef2aSThomas Huth } 981fcf5ef2aSThomas Huth 982fcf5ef2aSThomas Huth regs.hi = (int64_t)(target_long)env->active_tc.HI[0]; 983fcf5ef2aSThomas Huth regs.lo = (int64_t)(target_long)env->active_tc.LO[0]; 984fcf5ef2aSThomas Huth regs.pc = (int64_t)(target_long)env->active_tc.PC; 985fcf5ef2aSThomas Huth 986fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); 987fcf5ef2aSThomas Huth 988fcf5ef2aSThomas Huth if (ret < 0) { 989fcf5ef2aSThomas Huth return ret; 990fcf5ef2aSThomas Huth } 991fcf5ef2aSThomas Huth 992fcf5ef2aSThomas Huth ret = kvm_mips_put_cp0_registers(cs, level); 993fcf5ef2aSThomas Huth if (ret < 0) { 994fcf5ef2aSThomas Huth return ret; 995fcf5ef2aSThomas Huth } 996fcf5ef2aSThomas Huth 997fcf5ef2aSThomas Huth ret = kvm_mips_put_fpu_registers(cs, level); 998fcf5ef2aSThomas Huth if (ret < 0) { 999fcf5ef2aSThomas Huth return ret; 1000fcf5ef2aSThomas Huth } 1001fcf5ef2aSThomas Huth 1002fcf5ef2aSThomas Huth return ret; 1003fcf5ef2aSThomas Huth } 1004fcf5ef2aSThomas Huth 1005fcf5ef2aSThomas Huth int kvm_arch_get_registers(CPUState *cs) 1006fcf5ef2aSThomas Huth { 1007fcf5ef2aSThomas Huth MIPSCPU *cpu = MIPS_CPU(cs); 1008fcf5ef2aSThomas Huth CPUMIPSState *env = &cpu->env; 1009fcf5ef2aSThomas Huth int ret = 0; 1010fcf5ef2aSThomas Huth struct kvm_regs regs; 1011fcf5ef2aSThomas Huth int i; 1012fcf5ef2aSThomas Huth 1013fcf5ef2aSThomas Huth /* Get the current register set as KVM seems it */ 1014fcf5ef2aSThomas Huth ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 1015fcf5ef2aSThomas Huth 1016fcf5ef2aSThomas Huth if (ret < 0) { 1017fcf5ef2aSThomas Huth return ret; 1018fcf5ef2aSThomas Huth } 1019fcf5ef2aSThomas Huth 1020fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 1021fcf5ef2aSThomas Huth env->active_tc.gpr[i] = regs.gpr[i]; 1022fcf5ef2aSThomas Huth } 1023fcf5ef2aSThomas Huth 1024fcf5ef2aSThomas Huth env->active_tc.HI[0] = regs.hi; 1025fcf5ef2aSThomas Huth env->active_tc.LO[0] = regs.lo; 1026fcf5ef2aSThomas Huth env->active_tc.PC = regs.pc; 1027fcf5ef2aSThomas Huth 1028fcf5ef2aSThomas Huth kvm_mips_get_cp0_registers(cs); 1029fcf5ef2aSThomas Huth kvm_mips_get_fpu_registers(cs); 1030fcf5ef2aSThomas Huth 1031fcf5ef2aSThomas Huth return ret; 1032fcf5ef2aSThomas Huth } 1033fcf5ef2aSThomas Huth 1034fcf5ef2aSThomas Huth int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1035fcf5ef2aSThomas Huth uint64_t address, uint32_t data, PCIDevice *dev) 1036fcf5ef2aSThomas Huth { 1037fcf5ef2aSThomas Huth return 0; 1038fcf5ef2aSThomas Huth } 1039fcf5ef2aSThomas Huth 1040fcf5ef2aSThomas Huth int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1041fcf5ef2aSThomas Huth int vector, PCIDevice *dev) 1042fcf5ef2aSThomas Huth { 1043fcf5ef2aSThomas Huth return 0; 1044fcf5ef2aSThomas Huth } 1045fcf5ef2aSThomas Huth 1046fcf5ef2aSThomas Huth int kvm_arch_release_virq_post(int virq) 1047fcf5ef2aSThomas Huth { 1048fcf5ef2aSThomas Huth return 0; 1049fcf5ef2aSThomas Huth } 1050fcf5ef2aSThomas Huth 1051fcf5ef2aSThomas Huth int kvm_arch_msi_data_to_gsi(uint32_t data) 1052fcf5ef2aSThomas Huth { 1053fcf5ef2aSThomas Huth abort(); 1054fcf5ef2aSThomas Huth } 1055