xref: /openbmc/qemu/target/mips/kvm.c (revision 11cb076b)
1fcf5ef2aSThomas Huth /*
2fcf5ef2aSThomas Huth  * This file is subject to the terms and conditions of the GNU General Public
3fcf5ef2aSThomas Huth  * License.  See the file "COPYING" in the main directory of this archive
4fcf5ef2aSThomas Huth  * for more details.
5fcf5ef2aSThomas Huth  *
6fcf5ef2aSThomas Huth  * KVM/MIPS: MIPS specific KVM APIs
7fcf5ef2aSThomas Huth  *
8fcf5ef2aSThomas Huth  * Copyright (C) 2012-2014 Imagination Technologies Ltd.
9fcf5ef2aSThomas Huth  * Authors: Sanjay Lal <sanjayl@kymasys.com>
10fcf5ef2aSThomas Huth */
11fcf5ef2aSThomas Huth 
12fcf5ef2aSThomas Huth #include "qemu/osdep.h"
13fcf5ef2aSThomas Huth #include <sys/ioctl.h>
14fcf5ef2aSThomas Huth 
15fcf5ef2aSThomas Huth #include <linux/kvm.h>
16fcf5ef2aSThomas Huth 
17fcf5ef2aSThomas Huth #include "qemu-common.h"
18fcf5ef2aSThomas Huth #include "cpu.h"
1926aa3d9aSPhilippe Mathieu-Daudé #include "internal.h"
20fcf5ef2aSThomas Huth #include "qemu/error-report.h"
21db725815SMarkus Armbruster #include "qemu/main-loop.h"
22fcf5ef2aSThomas Huth #include "qemu/timer.h"
23fcf5ef2aSThomas Huth #include "sysemu/kvm.h"
24719d109bSHuacai Chen #include "sysemu/kvm_int.h"
2554d31236SMarkus Armbruster #include "sysemu/runstate.h"
26fcf5ef2aSThomas Huth #include "sysemu/cpus.h"
27fcf5ef2aSThomas Huth #include "kvm_mips.h"
28fcf5ef2aSThomas Huth #include "exec/memattrs.h"
29719d109bSHuacai Chen #include "hw/boards.h"
30fcf5ef2aSThomas Huth 
31fcf5ef2aSThomas Huth #define DEBUG_KVM 0
32fcf5ef2aSThomas Huth 
33fcf5ef2aSThomas Huth #define DPRINTF(fmt, ...) \
34fcf5ef2aSThomas Huth     do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0)
35fcf5ef2aSThomas Huth 
36fcf5ef2aSThomas Huth static int kvm_mips_fpu_cap;
37fcf5ef2aSThomas Huth static int kvm_mips_msa_cap;
38fcf5ef2aSThomas Huth 
39fcf5ef2aSThomas Huth const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
40fcf5ef2aSThomas Huth     KVM_CAP_LAST_INFO
41fcf5ef2aSThomas Huth };
42fcf5ef2aSThomas Huth 
43fcf5ef2aSThomas Huth static void kvm_mips_update_state(void *opaque, int running, RunState state);
44fcf5ef2aSThomas Huth 
45fcf5ef2aSThomas Huth unsigned long kvm_arch_vcpu_id(CPUState *cs)
46fcf5ef2aSThomas Huth {
47fcf5ef2aSThomas Huth     return cs->cpu_index;
48fcf5ef2aSThomas Huth }
49fcf5ef2aSThomas Huth 
50fcf5ef2aSThomas Huth int kvm_arch_init(MachineState *ms, KVMState *s)
51fcf5ef2aSThomas Huth {
52fcf5ef2aSThomas Huth     /* MIPS has 128 signals */
53fcf5ef2aSThomas Huth     kvm_set_sigmask_len(s, 16);
54fcf5ef2aSThomas Huth 
55fcf5ef2aSThomas Huth     kvm_mips_fpu_cap = kvm_check_extension(s, KVM_CAP_MIPS_FPU);
56fcf5ef2aSThomas Huth     kvm_mips_msa_cap = kvm_check_extension(s, KVM_CAP_MIPS_MSA);
57fcf5ef2aSThomas Huth 
58fcf5ef2aSThomas Huth     DPRINTF("%s\n", __func__);
59fcf5ef2aSThomas Huth     return 0;
60fcf5ef2aSThomas Huth }
61fcf5ef2aSThomas Huth 
624376c40dSPaolo Bonzini int kvm_arch_irqchip_create(KVMState *s)
63d525ffabSPaolo Bonzini {
64d525ffabSPaolo Bonzini     return 0;
65d525ffabSPaolo Bonzini }
66d525ffabSPaolo Bonzini 
67fcf5ef2aSThomas Huth int kvm_arch_init_vcpu(CPUState *cs)
68fcf5ef2aSThomas Huth {
69fcf5ef2aSThomas Huth     MIPSCPU *cpu = MIPS_CPU(cs);
70fcf5ef2aSThomas Huth     CPUMIPSState *env = &cpu->env;
71fcf5ef2aSThomas Huth     int ret = 0;
72fcf5ef2aSThomas Huth 
73fcf5ef2aSThomas Huth     qemu_add_vm_change_state_handler(kvm_mips_update_state, cs);
74fcf5ef2aSThomas Huth 
75fcf5ef2aSThomas Huth     if (kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) {
76fcf5ef2aSThomas Huth         ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_FPU, 0, 0);
77fcf5ef2aSThomas Huth         if (ret < 0) {
78fcf5ef2aSThomas Huth             /* mark unsupported so it gets disabled on reset */
79fcf5ef2aSThomas Huth             kvm_mips_fpu_cap = 0;
80fcf5ef2aSThomas Huth             ret = 0;
81fcf5ef2aSThomas Huth         }
82fcf5ef2aSThomas Huth     }
83fcf5ef2aSThomas Huth 
84fcf5ef2aSThomas Huth     if (kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) {
85fcf5ef2aSThomas Huth         ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0);
86fcf5ef2aSThomas Huth         if (ret < 0) {
87fcf5ef2aSThomas Huth             /* mark unsupported so it gets disabled on reset */
88fcf5ef2aSThomas Huth             kvm_mips_msa_cap = 0;
89fcf5ef2aSThomas Huth             ret = 0;
90fcf5ef2aSThomas Huth         }
91fcf5ef2aSThomas Huth     }
92fcf5ef2aSThomas Huth 
93fcf5ef2aSThomas Huth     DPRINTF("%s\n", __func__);
94fcf5ef2aSThomas Huth     return ret;
95fcf5ef2aSThomas Huth }
96fcf5ef2aSThomas Huth 
97b1115c99SLiran Alon int kvm_arch_destroy_vcpu(CPUState *cs)
98b1115c99SLiran Alon {
99b1115c99SLiran Alon     return 0;
100b1115c99SLiran Alon }
101b1115c99SLiran Alon 
102fcf5ef2aSThomas Huth void kvm_mips_reset_vcpu(MIPSCPU *cpu)
103fcf5ef2aSThomas Huth {
104fcf5ef2aSThomas Huth     CPUMIPSState *env = &cpu->env;
105fcf5ef2aSThomas Huth 
106fcf5ef2aSThomas Huth     if (!kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) {
1072ab4b135SAlistair Francis         warn_report("KVM does not support FPU, disabling");
108fcf5ef2aSThomas Huth         env->CP0_Config1 &= ~(1 << CP0C1_FP);
109fcf5ef2aSThomas Huth     }
110fcf5ef2aSThomas Huth     if (!kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) {
1112ab4b135SAlistair Francis         warn_report("KVM does not support MSA, disabling");
112fcf5ef2aSThomas Huth         env->CP0_Config3 &= ~(1 << CP0C3_MSAP);
113fcf5ef2aSThomas Huth     }
114fcf5ef2aSThomas Huth 
115fcf5ef2aSThomas Huth     DPRINTF("%s\n", __func__);
116fcf5ef2aSThomas Huth }
117fcf5ef2aSThomas Huth 
118fcf5ef2aSThomas Huth int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
119fcf5ef2aSThomas Huth {
120fcf5ef2aSThomas Huth     DPRINTF("%s\n", __func__);
121fcf5ef2aSThomas Huth     return 0;
122fcf5ef2aSThomas Huth }
123fcf5ef2aSThomas Huth 
124fcf5ef2aSThomas Huth int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
125fcf5ef2aSThomas Huth {
126fcf5ef2aSThomas Huth     DPRINTF("%s\n", __func__);
127fcf5ef2aSThomas Huth     return 0;
128fcf5ef2aSThomas Huth }
129fcf5ef2aSThomas Huth 
130fcf5ef2aSThomas Huth static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu)
131fcf5ef2aSThomas Huth {
132fcf5ef2aSThomas Huth     CPUMIPSState *env = &cpu->env;
133fcf5ef2aSThomas Huth 
134fcf5ef2aSThomas Huth     return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP));
135fcf5ef2aSThomas Huth }
136fcf5ef2aSThomas Huth 
137fcf5ef2aSThomas Huth 
138fcf5ef2aSThomas Huth void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
139fcf5ef2aSThomas Huth {
140fcf5ef2aSThomas Huth     MIPSCPU *cpu = MIPS_CPU(cs);
141fcf5ef2aSThomas Huth     int r;
142fcf5ef2aSThomas Huth     struct kvm_mips_interrupt intr;
143fcf5ef2aSThomas Huth 
144fcf5ef2aSThomas Huth     qemu_mutex_lock_iothread();
145fcf5ef2aSThomas Huth 
146fcf5ef2aSThomas Huth     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
147fcf5ef2aSThomas Huth             cpu_mips_io_interrupts_pending(cpu)) {
148fcf5ef2aSThomas Huth         intr.cpu = -1;
149fcf5ef2aSThomas Huth         intr.irq = 2;
150fcf5ef2aSThomas Huth         r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
151fcf5ef2aSThomas Huth         if (r < 0) {
152fcf5ef2aSThomas Huth             error_report("%s: cpu %d: failed to inject IRQ %x",
153fcf5ef2aSThomas Huth                          __func__, cs->cpu_index, intr.irq);
154fcf5ef2aSThomas Huth         }
155fcf5ef2aSThomas Huth     }
156fcf5ef2aSThomas Huth 
157fcf5ef2aSThomas Huth     qemu_mutex_unlock_iothread();
158fcf5ef2aSThomas Huth }
159fcf5ef2aSThomas Huth 
160fcf5ef2aSThomas Huth MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
161fcf5ef2aSThomas Huth {
162fcf5ef2aSThomas Huth     return MEMTXATTRS_UNSPECIFIED;
163fcf5ef2aSThomas Huth }
164fcf5ef2aSThomas Huth 
165fcf5ef2aSThomas Huth int kvm_arch_process_async_events(CPUState *cs)
166fcf5ef2aSThomas Huth {
167fcf5ef2aSThomas Huth     return cs->halted;
168fcf5ef2aSThomas Huth }
169fcf5ef2aSThomas Huth 
170fcf5ef2aSThomas Huth int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
171fcf5ef2aSThomas Huth {
172fcf5ef2aSThomas Huth     int ret;
173fcf5ef2aSThomas Huth 
174fcf5ef2aSThomas Huth     DPRINTF("%s\n", __func__);
175fcf5ef2aSThomas Huth     switch (run->exit_reason) {
176fcf5ef2aSThomas Huth     default:
177fcf5ef2aSThomas Huth         error_report("%s: unknown exit reason %d",
178fcf5ef2aSThomas Huth                      __func__, run->exit_reason);
179fcf5ef2aSThomas Huth         ret = -1;
180fcf5ef2aSThomas Huth         break;
181fcf5ef2aSThomas Huth     }
182fcf5ef2aSThomas Huth 
183fcf5ef2aSThomas Huth     return ret;
184fcf5ef2aSThomas Huth }
185fcf5ef2aSThomas Huth 
186fcf5ef2aSThomas Huth bool kvm_arch_stop_on_emulation_error(CPUState *cs)
187fcf5ef2aSThomas Huth {
188fcf5ef2aSThomas Huth     DPRINTF("%s\n", __func__);
189fcf5ef2aSThomas Huth     return true;
190fcf5ef2aSThomas Huth }
191fcf5ef2aSThomas Huth 
192fcf5ef2aSThomas Huth void kvm_arch_init_irq_routing(KVMState *s)
193fcf5ef2aSThomas Huth {
194fcf5ef2aSThomas Huth }
195fcf5ef2aSThomas Huth 
196fcf5ef2aSThomas Huth int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level)
197fcf5ef2aSThomas Huth {
198fcf5ef2aSThomas Huth     CPUState *cs = CPU(cpu);
199fcf5ef2aSThomas Huth     struct kvm_mips_interrupt intr;
200fcf5ef2aSThomas Huth 
201*11cb076bSPhilippe Mathieu-Daudé     assert(kvm_enabled());
202fcf5ef2aSThomas Huth 
203fcf5ef2aSThomas Huth     intr.cpu = -1;
204fcf5ef2aSThomas Huth 
205fcf5ef2aSThomas Huth     if (level) {
206fcf5ef2aSThomas Huth         intr.irq = irq;
207fcf5ef2aSThomas Huth     } else {
208fcf5ef2aSThomas Huth         intr.irq = -irq;
209fcf5ef2aSThomas Huth     }
210fcf5ef2aSThomas Huth 
211fcf5ef2aSThomas Huth     kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
212fcf5ef2aSThomas Huth 
213fcf5ef2aSThomas Huth     return 0;
214fcf5ef2aSThomas Huth }
215fcf5ef2aSThomas Huth 
216fcf5ef2aSThomas Huth int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level)
217fcf5ef2aSThomas Huth {
218fcf5ef2aSThomas Huth     CPUState *cs = current_cpu;
219fcf5ef2aSThomas Huth     CPUState *dest_cs = CPU(cpu);
220fcf5ef2aSThomas Huth     struct kvm_mips_interrupt intr;
221fcf5ef2aSThomas Huth 
222*11cb076bSPhilippe Mathieu-Daudé     assert(kvm_enabled());
223fcf5ef2aSThomas Huth 
224fcf5ef2aSThomas Huth     intr.cpu = dest_cs->cpu_index;
225fcf5ef2aSThomas Huth 
226fcf5ef2aSThomas Huth     if (level) {
227fcf5ef2aSThomas Huth         intr.irq = irq;
228fcf5ef2aSThomas Huth     } else {
229fcf5ef2aSThomas Huth         intr.irq = -irq;
230fcf5ef2aSThomas Huth     }
231fcf5ef2aSThomas Huth 
232fcf5ef2aSThomas Huth     DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq);
233fcf5ef2aSThomas Huth 
234fcf5ef2aSThomas Huth     kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
235fcf5ef2aSThomas Huth 
236fcf5ef2aSThomas Huth     return 0;
237fcf5ef2aSThomas Huth }
238fcf5ef2aSThomas Huth 
239fcf5ef2aSThomas Huth #define MIPS_CP0_32(_R, _S)                                     \
240fcf5ef2aSThomas Huth     (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
241fcf5ef2aSThomas Huth 
242fcf5ef2aSThomas Huth #define MIPS_CP0_64(_R, _S)                                     \
243fcf5ef2aSThomas Huth     (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
244fcf5ef2aSThomas Huth 
245fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
2467e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_RANDOM         MIPS_CP0_32(1, 0)
247fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
248fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
249fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
2507e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PAGEGRAIN      MIPS_CP0_32(5, 1)
2517e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PWBASE         MIPS_CP0_64(5, 5)
2527e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PWFIELD        MIPS_CP0_64(5, 6)
2537e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PWSIZE         MIPS_CP0_64(5, 7)
254fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
2557e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_PWCTL          MIPS_CP0_32(6, 6)
256fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
257fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
258fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
259fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
260fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
261fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
262fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
263fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
264fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_PRID           MIPS_CP0_32(15, 0)
2657e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_EBASE          MIPS_CP0_64(15, 1)
266fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG         MIPS_CP0_32(16, 0)
267fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG1        MIPS_CP0_32(16, 1)
268fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG2        MIPS_CP0_32(16, 2)
269fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG3        MIPS_CP0_32(16, 3)
270fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG4        MIPS_CP0_32(16, 4)
271fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG5        MIPS_CP0_32(16, 5)
2727e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_CONFIG6        MIPS_CP0_32(16, 6)
2737e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_XCONTEXT       MIPS_CP0_64(20, 0)
274fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
2757e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH1      MIPS_CP0_64(31, 2)
2767e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH2      MIPS_CP0_64(31, 3)
2777e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH3      MIPS_CP0_64(31, 4)
2787e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH4      MIPS_CP0_64(31, 5)
2797e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH5      MIPS_CP0_64(31, 6)
2807e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_KSCRATCH6      MIPS_CP0_64(31, 7)
281fcf5ef2aSThomas Huth 
282fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id,
283fcf5ef2aSThomas Huth                                        int32_t *addr)
284fcf5ef2aSThomas Huth {
285fcf5ef2aSThomas Huth     struct kvm_one_reg cp0reg = {
286fcf5ef2aSThomas Huth         .id = reg_id,
287fcf5ef2aSThomas Huth         .addr = (uintptr_t)addr
288fcf5ef2aSThomas Huth     };
289fcf5ef2aSThomas Huth 
290fcf5ef2aSThomas Huth     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
291fcf5ef2aSThomas Huth }
292fcf5ef2aSThomas Huth 
293fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ureg(CPUState *cs, uint64_t reg_id,
294fcf5ef2aSThomas Huth                                         uint32_t *addr)
295fcf5ef2aSThomas Huth {
296fcf5ef2aSThomas Huth     struct kvm_one_reg cp0reg = {
297fcf5ef2aSThomas Huth         .id = reg_id,
298fcf5ef2aSThomas Huth         .addr = (uintptr_t)addr
299fcf5ef2aSThomas Huth     };
300fcf5ef2aSThomas Huth 
301fcf5ef2aSThomas Huth     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
302fcf5ef2aSThomas Huth }
303fcf5ef2aSThomas Huth 
304fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id,
305fcf5ef2aSThomas Huth                                          target_ulong *addr)
306fcf5ef2aSThomas Huth {
307fcf5ef2aSThomas Huth     uint64_t val64 = *addr;
308fcf5ef2aSThomas Huth     struct kvm_one_reg cp0reg = {
309fcf5ef2aSThomas Huth         .id = reg_id,
310fcf5ef2aSThomas Huth         .addr = (uintptr_t)&val64
311fcf5ef2aSThomas Huth     };
312fcf5ef2aSThomas Huth 
313fcf5ef2aSThomas Huth     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
314fcf5ef2aSThomas Huth }
315fcf5ef2aSThomas Huth 
316fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id,
317fcf5ef2aSThomas Huth                                          int64_t *addr)
318fcf5ef2aSThomas Huth {
319fcf5ef2aSThomas Huth     struct kvm_one_reg cp0reg = {
320fcf5ef2aSThomas Huth         .id = reg_id,
321fcf5ef2aSThomas Huth         .addr = (uintptr_t)addr
322fcf5ef2aSThomas Huth     };
323fcf5ef2aSThomas Huth 
324fcf5ef2aSThomas Huth     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
325fcf5ef2aSThomas Huth }
326fcf5ef2aSThomas Huth 
327fcf5ef2aSThomas Huth static inline int kvm_mips_put_one_ureg64(CPUState *cs, uint64_t reg_id,
328fcf5ef2aSThomas Huth                                           uint64_t *addr)
329fcf5ef2aSThomas Huth {
330fcf5ef2aSThomas Huth     struct kvm_one_reg cp0reg = {
331fcf5ef2aSThomas Huth         .id = reg_id,
332fcf5ef2aSThomas Huth         .addr = (uintptr_t)addr
333fcf5ef2aSThomas Huth     };
334fcf5ef2aSThomas Huth 
335fcf5ef2aSThomas Huth     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
336fcf5ef2aSThomas Huth }
337fcf5ef2aSThomas Huth 
338fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id,
339fcf5ef2aSThomas Huth                                        int32_t *addr)
340fcf5ef2aSThomas Huth {
341fcf5ef2aSThomas Huth     struct kvm_one_reg cp0reg = {
342fcf5ef2aSThomas Huth         .id = reg_id,
343fcf5ef2aSThomas Huth         .addr = (uintptr_t)addr
344fcf5ef2aSThomas Huth     };
345fcf5ef2aSThomas Huth 
346fcf5ef2aSThomas Huth     return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
347fcf5ef2aSThomas Huth }
348fcf5ef2aSThomas Huth 
349fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ureg(CPUState *cs, uint64_t reg_id,
350fcf5ef2aSThomas Huth                                         uint32_t *addr)
351fcf5ef2aSThomas Huth {
352fcf5ef2aSThomas Huth     struct kvm_one_reg cp0reg = {
353fcf5ef2aSThomas Huth         .id = reg_id,
354fcf5ef2aSThomas Huth         .addr = (uintptr_t)addr
355fcf5ef2aSThomas Huth     };
356fcf5ef2aSThomas Huth 
357fcf5ef2aSThomas Huth     return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
358fcf5ef2aSThomas Huth }
359fcf5ef2aSThomas Huth 
360fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64_t reg_id,
361fcf5ef2aSThomas Huth                                          target_ulong *addr)
362fcf5ef2aSThomas Huth {
363fcf5ef2aSThomas Huth     int ret;
364fcf5ef2aSThomas Huth     uint64_t val64 = 0;
365fcf5ef2aSThomas Huth     struct kvm_one_reg cp0reg = {
366fcf5ef2aSThomas Huth         .id = reg_id,
367fcf5ef2aSThomas Huth         .addr = (uintptr_t)&val64
368fcf5ef2aSThomas Huth     };
369fcf5ef2aSThomas Huth 
370fcf5ef2aSThomas Huth     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
371fcf5ef2aSThomas Huth     if (ret >= 0) {
372fcf5ef2aSThomas Huth         *addr = val64;
373fcf5ef2aSThomas Huth     }
374fcf5ef2aSThomas Huth     return ret;
375fcf5ef2aSThomas Huth }
376fcf5ef2aSThomas Huth 
377fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64_t reg_id,
378fcf5ef2aSThomas Huth                                          int64_t *addr)
379fcf5ef2aSThomas Huth {
380fcf5ef2aSThomas Huth     struct kvm_one_reg cp0reg = {
381fcf5ef2aSThomas Huth         .id = reg_id,
382fcf5ef2aSThomas Huth         .addr = (uintptr_t)addr
383fcf5ef2aSThomas Huth     };
384fcf5ef2aSThomas Huth 
385fcf5ef2aSThomas Huth     return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
386fcf5ef2aSThomas Huth }
387fcf5ef2aSThomas Huth 
388fcf5ef2aSThomas Huth static inline int kvm_mips_get_one_ureg64(CPUState *cs, uint64_t reg_id,
389fcf5ef2aSThomas Huth                                           uint64_t *addr)
390fcf5ef2aSThomas Huth {
391fcf5ef2aSThomas Huth     struct kvm_one_reg cp0reg = {
392fcf5ef2aSThomas Huth         .id = reg_id,
393fcf5ef2aSThomas Huth         .addr = (uintptr_t)addr
394fcf5ef2aSThomas Huth     };
395fcf5ef2aSThomas Huth 
396fcf5ef2aSThomas Huth     return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
397fcf5ef2aSThomas Huth }
398fcf5ef2aSThomas Huth 
399fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG_MASK    (1U << CP0C0_M)
400fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG1_MASK   ((1U << CP0C1_M) | \
401fcf5ef2aSThomas Huth                                          (1U << CP0C1_FP))
402fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG2_MASK   (1U << CP0C2_M)
403fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG3_MASK   ((1U << CP0C3_M) | \
404fcf5ef2aSThomas Huth                                          (1U << CP0C3_MSAP))
405fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG4_MASK   (1U << CP0C4_M)
406fcf5ef2aSThomas Huth #define KVM_REG_MIPS_CP0_CONFIG5_MASK   ((1U << CP0C5_MSAEn) | \
407fcf5ef2aSThomas Huth                                          (1U << CP0C5_UFE) | \
408fcf5ef2aSThomas Huth                                          (1U << CP0C5_FRE) | \
409fcf5ef2aSThomas Huth                                          (1U << CP0C5_UFR))
4107e0896b0SHuacai Chen #define KVM_REG_MIPS_CP0_CONFIG6_MASK   ((1U << CP0C6_BPPASS) | \
4117e0896b0SHuacai Chen                                          (0x3fU << CP0C6_KPOS) | \
4127e0896b0SHuacai Chen                                          (1U << CP0C6_KE) | \
4137e0896b0SHuacai Chen                                          (1U << CP0C6_VTLBONLY) | \
4147e0896b0SHuacai Chen                                          (1U << CP0C6_LASX) | \
4157e0896b0SHuacai Chen                                          (1U << CP0C6_SSEN) | \
4167e0896b0SHuacai Chen                                          (1U << CP0C6_DISDRTIME) | \
4177e0896b0SHuacai Chen                                          (1U << CP0C6_PIXNUEN) | \
4187e0896b0SHuacai Chen                                          (1U << CP0C6_SCRAND) | \
4197e0896b0SHuacai Chen                                          (1U << CP0C6_LLEXCEN) | \
4207e0896b0SHuacai Chen                                          (1U << CP0C6_DISVC) | \
4217e0896b0SHuacai Chen                                          (1U << CP0C6_VCLRU) | \
4227e0896b0SHuacai Chen                                          (1U << CP0C6_DCLRU) | \
4237e0896b0SHuacai Chen                                          (1U << CP0C6_PIXUEN) | \
4247e0896b0SHuacai Chen                                          (1U << CP0C6_DISBLKLYEN) | \
4257e0896b0SHuacai Chen                                          (1U << CP0C6_UMEMUALEN) | \
4267e0896b0SHuacai Chen                                          (1U << CP0C6_SFBEN) | \
4277e0896b0SHuacai Chen                                          (1U << CP0C6_FLTINT) | \
4287e0896b0SHuacai Chen                                          (1U << CP0C6_VLTINT) | \
4297e0896b0SHuacai Chen                                          (1U << CP0C6_DISBTB) | \
4307e0896b0SHuacai Chen                                          (3U << CP0C6_STPREFCTL) | \
4317e0896b0SHuacai Chen                                          (1U << CP0C6_INSTPREF) | \
4327e0896b0SHuacai Chen                                          (1U << CP0C6_DATAPREF))
433fcf5ef2aSThomas Huth 
434fcf5ef2aSThomas Huth static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id,
435fcf5ef2aSThomas Huth                                           int32_t *addr, int32_t mask)
436fcf5ef2aSThomas Huth {
437fcf5ef2aSThomas Huth     int err;
438fcf5ef2aSThomas Huth     int32_t tmp, change;
439fcf5ef2aSThomas Huth 
440fcf5ef2aSThomas Huth     err = kvm_mips_get_one_reg(cs, reg_id, &tmp);
441fcf5ef2aSThomas Huth     if (err < 0) {
442fcf5ef2aSThomas Huth         return err;
443fcf5ef2aSThomas Huth     }
444fcf5ef2aSThomas Huth 
445fcf5ef2aSThomas Huth     /* only change bits in mask */
446fcf5ef2aSThomas Huth     change = (*addr ^ tmp) & mask;
447fcf5ef2aSThomas Huth     if (!change) {
448fcf5ef2aSThomas Huth         return 0;
449fcf5ef2aSThomas Huth     }
450fcf5ef2aSThomas Huth 
451fcf5ef2aSThomas Huth     tmp = tmp ^ change;
452fcf5ef2aSThomas Huth     return kvm_mips_put_one_reg(cs, reg_id, &tmp);
453fcf5ef2aSThomas Huth }
454fcf5ef2aSThomas Huth 
455fcf5ef2aSThomas Huth /*
456fcf5ef2aSThomas Huth  * We freeze the KVM timer when either the VM clock is stopped or the state is
457fcf5ef2aSThomas Huth  * saved (the state is dirty).
458fcf5ef2aSThomas Huth  */
459fcf5ef2aSThomas Huth 
460fcf5ef2aSThomas Huth /*
461fcf5ef2aSThomas Huth  * Save the state of the KVM timer when VM clock is stopped or state is synced
462fcf5ef2aSThomas Huth  * to QEMU.
463fcf5ef2aSThomas Huth  */
464fcf5ef2aSThomas Huth static int kvm_mips_save_count(CPUState *cs)
465fcf5ef2aSThomas Huth {
466fcf5ef2aSThomas Huth     MIPSCPU *cpu = MIPS_CPU(cs);
467fcf5ef2aSThomas Huth     CPUMIPSState *env = &cpu->env;
468fcf5ef2aSThomas Huth     uint64_t count_ctl;
469fcf5ef2aSThomas Huth     int err, ret = 0;
470fcf5ef2aSThomas Huth 
471fcf5ef2aSThomas Huth     /* freeze KVM timer */
472fcf5ef2aSThomas Huth     err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
473fcf5ef2aSThomas Huth     if (err < 0) {
474fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err);
475fcf5ef2aSThomas Huth         ret = err;
476fcf5ef2aSThomas Huth     } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
477fcf5ef2aSThomas Huth         count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
478fcf5ef2aSThomas Huth         err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
479fcf5ef2aSThomas Huth         if (err < 0) {
480fcf5ef2aSThomas Huth             DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
481fcf5ef2aSThomas Huth             ret = err;
482fcf5ef2aSThomas Huth         }
483fcf5ef2aSThomas Huth     }
484fcf5ef2aSThomas Huth 
485fcf5ef2aSThomas Huth     /* read CP0_Cause */
486fcf5ef2aSThomas Huth     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
487fcf5ef2aSThomas Huth     if (err < 0) {
488fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err);
489fcf5ef2aSThomas Huth         ret = err;
490fcf5ef2aSThomas Huth     }
491fcf5ef2aSThomas Huth 
492fcf5ef2aSThomas Huth     /* read CP0_Count */
493fcf5ef2aSThomas Huth     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
494fcf5ef2aSThomas Huth     if (err < 0) {
495fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err);
496fcf5ef2aSThomas Huth         ret = err;
497fcf5ef2aSThomas Huth     }
498fcf5ef2aSThomas Huth 
499fcf5ef2aSThomas Huth     return ret;
500fcf5ef2aSThomas Huth }
501fcf5ef2aSThomas Huth 
502fcf5ef2aSThomas Huth /*
503fcf5ef2aSThomas Huth  * Restore the state of the KVM timer when VM clock is restarted or state is
504fcf5ef2aSThomas Huth  * synced to KVM.
505fcf5ef2aSThomas Huth  */
506fcf5ef2aSThomas Huth static int kvm_mips_restore_count(CPUState *cs)
507fcf5ef2aSThomas Huth {
508fcf5ef2aSThomas Huth     MIPSCPU *cpu = MIPS_CPU(cs);
509fcf5ef2aSThomas Huth     CPUMIPSState *env = &cpu->env;
510fcf5ef2aSThomas Huth     uint64_t count_ctl;
511fcf5ef2aSThomas Huth     int err_dc, err, ret = 0;
512fcf5ef2aSThomas Huth 
513fcf5ef2aSThomas Huth     /* check the timer is frozen */
514fcf5ef2aSThomas Huth     err_dc = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
515fcf5ef2aSThomas Huth     if (err_dc < 0) {
516fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc);
517fcf5ef2aSThomas Huth         ret = err_dc;
518fcf5ef2aSThomas Huth     } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
519fcf5ef2aSThomas Huth         /* freeze timer (sets COUNT_RESUME for us) */
520fcf5ef2aSThomas Huth         count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
521fcf5ef2aSThomas Huth         err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
522fcf5ef2aSThomas Huth         if (err < 0) {
523fcf5ef2aSThomas Huth             DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
524fcf5ef2aSThomas Huth             ret = err;
525fcf5ef2aSThomas Huth         }
526fcf5ef2aSThomas Huth     }
527fcf5ef2aSThomas Huth 
528fcf5ef2aSThomas Huth     /* load CP0_Cause */
529fcf5ef2aSThomas Huth     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
530fcf5ef2aSThomas Huth     if (err < 0) {
531fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err);
532fcf5ef2aSThomas Huth         ret = err;
533fcf5ef2aSThomas Huth     }
534fcf5ef2aSThomas Huth 
535fcf5ef2aSThomas Huth     /* load CP0_Count */
536fcf5ef2aSThomas Huth     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
537fcf5ef2aSThomas Huth     if (err < 0) {
538fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err);
539fcf5ef2aSThomas Huth         ret = err;
540fcf5ef2aSThomas Huth     }
541fcf5ef2aSThomas Huth 
542fcf5ef2aSThomas Huth     /* resume KVM timer */
543fcf5ef2aSThomas Huth     if (err_dc >= 0) {
544fcf5ef2aSThomas Huth         count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC;
545fcf5ef2aSThomas Huth         err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
546fcf5ef2aSThomas Huth         if (err < 0) {
547fcf5ef2aSThomas Huth             DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err);
548fcf5ef2aSThomas Huth             ret = err;
549fcf5ef2aSThomas Huth         }
550fcf5ef2aSThomas Huth     }
551fcf5ef2aSThomas Huth 
552fcf5ef2aSThomas Huth     return ret;
553fcf5ef2aSThomas Huth }
554fcf5ef2aSThomas Huth 
555fcf5ef2aSThomas Huth /*
556fcf5ef2aSThomas Huth  * Handle the VM clock being started or stopped
557fcf5ef2aSThomas Huth  */
558fcf5ef2aSThomas Huth static void kvm_mips_update_state(void *opaque, int running, RunState state)
559fcf5ef2aSThomas Huth {
560fcf5ef2aSThomas Huth     CPUState *cs = opaque;
561fcf5ef2aSThomas Huth     int ret;
562fcf5ef2aSThomas Huth     uint64_t count_resume;
563fcf5ef2aSThomas Huth 
564fcf5ef2aSThomas Huth     /*
565fcf5ef2aSThomas Huth      * If state is already dirty (synced to QEMU) then the KVM timer state is
566fcf5ef2aSThomas Huth      * already saved and can be restored when it is synced back to KVM.
567fcf5ef2aSThomas Huth      */
568fcf5ef2aSThomas Huth     if (!running) {
56999f31832SSergio Andres Gomez Del Real         if (!cs->vcpu_dirty) {
570fcf5ef2aSThomas Huth             ret = kvm_mips_save_count(cs);
571fcf5ef2aSThomas Huth             if (ret < 0) {
572288cb949SAlistair Francis                 warn_report("Failed saving count");
573fcf5ef2aSThomas Huth             }
574fcf5ef2aSThomas Huth         }
575fcf5ef2aSThomas Huth     } else {
576fcf5ef2aSThomas Huth         /* Set clock restore time to now */
577fcf5ef2aSThomas Huth         count_resume = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
578fcf5ef2aSThomas Huth         ret = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_COUNT_RESUME,
579fcf5ef2aSThomas Huth                                       &count_resume);
580fcf5ef2aSThomas Huth         if (ret < 0) {
581288cb949SAlistair Francis             warn_report("Failed setting COUNT_RESUME");
582fcf5ef2aSThomas Huth             return;
583fcf5ef2aSThomas Huth         }
584fcf5ef2aSThomas Huth 
58599f31832SSergio Andres Gomez Del Real         if (!cs->vcpu_dirty) {
586fcf5ef2aSThomas Huth             ret = kvm_mips_restore_count(cs);
587fcf5ef2aSThomas Huth             if (ret < 0) {
588288cb949SAlistair Francis                 warn_report("Failed restoring count");
589fcf5ef2aSThomas Huth             }
590fcf5ef2aSThomas Huth         }
591fcf5ef2aSThomas Huth     }
592fcf5ef2aSThomas Huth }
593fcf5ef2aSThomas Huth 
594fcf5ef2aSThomas Huth static int kvm_mips_put_fpu_registers(CPUState *cs, int level)
595fcf5ef2aSThomas Huth {
596fcf5ef2aSThomas Huth     MIPSCPU *cpu = MIPS_CPU(cs);
597fcf5ef2aSThomas Huth     CPUMIPSState *env = &cpu->env;
598fcf5ef2aSThomas Huth     int err, ret = 0;
599fcf5ef2aSThomas Huth     unsigned int i;
600fcf5ef2aSThomas Huth 
601fcf5ef2aSThomas Huth     /* Only put FPU state if we're emulating a CPU with an FPU */
602fcf5ef2aSThomas Huth     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
603fcf5ef2aSThomas Huth         /* FPU Control Registers */
604fcf5ef2aSThomas Huth         if (level == KVM_PUT_FULL_STATE) {
605fcf5ef2aSThomas Huth             err = kvm_mips_put_one_ureg(cs, KVM_REG_MIPS_FCR_IR,
606fcf5ef2aSThomas Huth                                         &env->active_fpu.fcr0);
607fcf5ef2aSThomas Huth             if (err < 0) {
608fcf5ef2aSThomas Huth                 DPRINTF("%s: Failed to put FCR_IR (%d)\n", __func__, err);
609fcf5ef2aSThomas Huth                 ret = err;
610fcf5ef2aSThomas Huth             }
611fcf5ef2aSThomas Huth         }
612fcf5ef2aSThomas Huth         err = kvm_mips_put_one_ureg(cs, KVM_REG_MIPS_FCR_CSR,
613fcf5ef2aSThomas Huth                                     &env->active_fpu.fcr31);
614fcf5ef2aSThomas Huth         if (err < 0) {
615fcf5ef2aSThomas Huth             DPRINTF("%s: Failed to put FCR_CSR (%d)\n", __func__, err);
616fcf5ef2aSThomas Huth             ret = err;
617fcf5ef2aSThomas Huth         }
618fcf5ef2aSThomas Huth 
619fcf5ef2aSThomas Huth         /*
620fcf5ef2aSThomas Huth          * FPU register state is a subset of MSA vector state, so don't put FPU
621fcf5ef2aSThomas Huth          * registers if we're emulating a CPU with MSA.
622fcf5ef2aSThomas Huth          */
623fcf5ef2aSThomas Huth         if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
624fcf5ef2aSThomas Huth             /* Floating point registers */
625fcf5ef2aSThomas Huth             for (i = 0; i < 32; ++i) {
626fcf5ef2aSThomas Huth                 if (env->CP0_Status & (1 << CP0St_FR)) {
627fcf5ef2aSThomas Huth                     err = kvm_mips_put_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i),
628fcf5ef2aSThomas Huth                                                   &env->active_fpu.fpr[i].d);
629fcf5ef2aSThomas Huth                 } else {
630fcf5ef2aSThomas Huth                     err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i),
631fcf5ef2aSThomas Huth                                     &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]);
632fcf5ef2aSThomas Huth                 }
633fcf5ef2aSThomas Huth                 if (err < 0) {
634fcf5ef2aSThomas Huth                     DPRINTF("%s: Failed to put FPR%u (%d)\n", __func__, i, err);
635fcf5ef2aSThomas Huth                     ret = err;
636fcf5ef2aSThomas Huth                 }
637fcf5ef2aSThomas Huth             }
638fcf5ef2aSThomas Huth         }
639fcf5ef2aSThomas Huth     }
640fcf5ef2aSThomas Huth 
641fcf5ef2aSThomas Huth     /* Only put MSA state if we're emulating a CPU with MSA */
642fcf5ef2aSThomas Huth     if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
643fcf5ef2aSThomas Huth         /* MSA Control Registers */
644fcf5ef2aSThomas Huth         if (level == KVM_PUT_FULL_STATE) {
645fcf5ef2aSThomas Huth             err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_IR,
646fcf5ef2aSThomas Huth                                        &env->msair);
647fcf5ef2aSThomas Huth             if (err < 0) {
648fcf5ef2aSThomas Huth                 DPRINTF("%s: Failed to put MSA_IR (%d)\n", __func__, err);
649fcf5ef2aSThomas Huth                 ret = err;
650fcf5ef2aSThomas Huth             }
651fcf5ef2aSThomas Huth         }
652fcf5ef2aSThomas Huth         err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_CSR,
653fcf5ef2aSThomas Huth                                    &env->active_tc.msacsr);
654fcf5ef2aSThomas Huth         if (err < 0) {
655fcf5ef2aSThomas Huth             DPRINTF("%s: Failed to put MSA_CSR (%d)\n", __func__, err);
656fcf5ef2aSThomas Huth             ret = err;
657fcf5ef2aSThomas Huth         }
658fcf5ef2aSThomas Huth 
659fcf5ef2aSThomas Huth         /* Vector registers (includes FP registers) */
660fcf5ef2aSThomas Huth         for (i = 0; i < 32; ++i) {
661fcf5ef2aSThomas Huth             /* Big endian MSA not supported by QEMU yet anyway */
662fcf5ef2aSThomas Huth             err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_VEC_128(i),
663fcf5ef2aSThomas Huth                                          env->active_fpu.fpr[i].wr.d);
664fcf5ef2aSThomas Huth             if (err < 0) {
665fcf5ef2aSThomas Huth                 DPRINTF("%s: Failed to put VEC%u (%d)\n", __func__, i, err);
666fcf5ef2aSThomas Huth                 ret = err;
667fcf5ef2aSThomas Huth             }
668fcf5ef2aSThomas Huth         }
669fcf5ef2aSThomas Huth     }
670fcf5ef2aSThomas Huth 
671fcf5ef2aSThomas Huth     return ret;
672fcf5ef2aSThomas Huth }
673fcf5ef2aSThomas Huth 
674fcf5ef2aSThomas Huth static int kvm_mips_get_fpu_registers(CPUState *cs)
675fcf5ef2aSThomas Huth {
676fcf5ef2aSThomas Huth     MIPSCPU *cpu = MIPS_CPU(cs);
677fcf5ef2aSThomas Huth     CPUMIPSState *env = &cpu->env;
678fcf5ef2aSThomas Huth     int err, ret = 0;
679fcf5ef2aSThomas Huth     unsigned int i;
680fcf5ef2aSThomas Huth 
681fcf5ef2aSThomas Huth     /* Only get FPU state if we're emulating a CPU with an FPU */
682fcf5ef2aSThomas Huth     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
683fcf5ef2aSThomas Huth         /* FPU Control Registers */
684fcf5ef2aSThomas Huth         err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_IR,
685fcf5ef2aSThomas Huth                                     &env->active_fpu.fcr0);
686fcf5ef2aSThomas Huth         if (err < 0) {
687fcf5ef2aSThomas Huth             DPRINTF("%s: Failed to get FCR_IR (%d)\n", __func__, err);
688fcf5ef2aSThomas Huth             ret = err;
689fcf5ef2aSThomas Huth         }
690fcf5ef2aSThomas Huth         err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_CSR,
691fcf5ef2aSThomas Huth                                     &env->active_fpu.fcr31);
692fcf5ef2aSThomas Huth         if (err < 0) {
693fcf5ef2aSThomas Huth             DPRINTF("%s: Failed to get FCR_CSR (%d)\n", __func__, err);
694fcf5ef2aSThomas Huth             ret = err;
695fcf5ef2aSThomas Huth         } else {
696fcf5ef2aSThomas Huth             restore_fp_status(env);
697fcf5ef2aSThomas Huth         }
698fcf5ef2aSThomas Huth 
699fcf5ef2aSThomas Huth         /*
700fcf5ef2aSThomas Huth          * FPU register state is a subset of MSA vector state, so don't save FPU
701fcf5ef2aSThomas Huth          * registers if we're emulating a CPU with MSA.
702fcf5ef2aSThomas Huth          */
703fcf5ef2aSThomas Huth         if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
704fcf5ef2aSThomas Huth             /* Floating point registers */
705fcf5ef2aSThomas Huth             for (i = 0; i < 32; ++i) {
706fcf5ef2aSThomas Huth                 if (env->CP0_Status & (1 << CP0St_FR)) {
707fcf5ef2aSThomas Huth                     err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i),
708fcf5ef2aSThomas Huth                                                   &env->active_fpu.fpr[i].d);
709fcf5ef2aSThomas Huth                 } else {
710fcf5ef2aSThomas Huth                     err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i),
711fcf5ef2aSThomas Huth                                     &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]);
712fcf5ef2aSThomas Huth                 }
713fcf5ef2aSThomas Huth                 if (err < 0) {
714fcf5ef2aSThomas Huth                     DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__, i, err);
715fcf5ef2aSThomas Huth                     ret = err;
716fcf5ef2aSThomas Huth                 }
717fcf5ef2aSThomas Huth             }
718fcf5ef2aSThomas Huth         }
719fcf5ef2aSThomas Huth     }
720fcf5ef2aSThomas Huth 
721fcf5ef2aSThomas Huth     /* Only get MSA state if we're emulating a CPU with MSA */
722fcf5ef2aSThomas Huth     if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
723fcf5ef2aSThomas Huth         /* MSA Control Registers */
724fcf5ef2aSThomas Huth         err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR,
725fcf5ef2aSThomas Huth                                    &env->msair);
726fcf5ef2aSThomas Huth         if (err < 0) {
727fcf5ef2aSThomas Huth             DPRINTF("%s: Failed to get MSA_IR (%d)\n", __func__, err);
728fcf5ef2aSThomas Huth             ret = err;
729fcf5ef2aSThomas Huth         }
730fcf5ef2aSThomas Huth         err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_CSR,
731fcf5ef2aSThomas Huth                                    &env->active_tc.msacsr);
732fcf5ef2aSThomas Huth         if (err < 0) {
733fcf5ef2aSThomas Huth             DPRINTF("%s: Failed to get MSA_CSR (%d)\n", __func__, err);
734fcf5ef2aSThomas Huth             ret = err;
735fcf5ef2aSThomas Huth         } else {
736fcf5ef2aSThomas Huth             restore_msa_fp_status(env);
737fcf5ef2aSThomas Huth         }
738fcf5ef2aSThomas Huth 
739fcf5ef2aSThomas Huth         /* Vector registers (includes FP registers) */
740fcf5ef2aSThomas Huth         for (i = 0; i < 32; ++i) {
741fcf5ef2aSThomas Huth             /* Big endian MSA not supported by QEMU yet anyway */
742fcf5ef2aSThomas Huth             err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_VEC_128(i),
743fcf5ef2aSThomas Huth                                          env->active_fpu.fpr[i].wr.d);
744fcf5ef2aSThomas Huth             if (err < 0) {
745fcf5ef2aSThomas Huth                 DPRINTF("%s: Failed to get VEC%u (%d)\n", __func__, i, err);
746fcf5ef2aSThomas Huth                 ret = err;
747fcf5ef2aSThomas Huth             }
748fcf5ef2aSThomas Huth         }
749fcf5ef2aSThomas Huth     }
750fcf5ef2aSThomas Huth 
751fcf5ef2aSThomas Huth     return ret;
752fcf5ef2aSThomas Huth }
753fcf5ef2aSThomas Huth 
754fcf5ef2aSThomas Huth 
755fcf5ef2aSThomas Huth static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
756fcf5ef2aSThomas Huth {
757fcf5ef2aSThomas Huth     MIPSCPU *cpu = MIPS_CPU(cs);
758fcf5ef2aSThomas Huth     CPUMIPSState *env = &cpu->env;
759fcf5ef2aSThomas Huth     int err, ret = 0;
760fcf5ef2aSThomas Huth 
761fcf5ef2aSThomas Huth     (void)level;
762fcf5ef2aSThomas Huth 
763fcf5ef2aSThomas Huth     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
764fcf5ef2aSThomas Huth     if (err < 0) {
765fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err);
766fcf5ef2aSThomas Huth         ret = err;
767fcf5ef2aSThomas Huth     }
7687e0896b0SHuacai Chen     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_RANDOM, &env->CP0_Random);
7697e0896b0SHuacai Chen     if (err < 0) {
7707e0896b0SHuacai Chen         DPRINTF("%s: Failed to put CP0_RANDOM (%d)\n", __func__, err);
7717e0896b0SHuacai Chen         ret = err;
7727e0896b0SHuacai Chen     }
773fcf5ef2aSThomas Huth     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
774fcf5ef2aSThomas Huth                                  &env->CP0_Context);
775fcf5ef2aSThomas Huth     if (err < 0) {
776fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err);
777fcf5ef2aSThomas Huth         ret = err;
778fcf5ef2aSThomas Huth     }
779fcf5ef2aSThomas Huth     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
780fcf5ef2aSThomas Huth                                  &env->active_tc.CP0_UserLocal);
781fcf5ef2aSThomas Huth     if (err < 0) {
782fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err);
783fcf5ef2aSThomas Huth         ret = err;
784fcf5ef2aSThomas Huth     }
785fcf5ef2aSThomas Huth     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
786fcf5ef2aSThomas Huth                                &env->CP0_PageMask);
787fcf5ef2aSThomas Huth     if (err < 0) {
788fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err);
789fcf5ef2aSThomas Huth         ret = err;
790fcf5ef2aSThomas Huth     }
7917e0896b0SHuacai Chen     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEGRAIN,
7927e0896b0SHuacai Chen                                &env->CP0_PageGrain);
7937e0896b0SHuacai Chen     if (err < 0) {
7947e0896b0SHuacai Chen         DPRINTF("%s: Failed to put CP0_PAGEGRAIN (%d)\n", __func__, err);
7957e0896b0SHuacai Chen         ret = err;
7967e0896b0SHuacai Chen     }
7977e0896b0SHuacai Chen     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWBASE,
7987e0896b0SHuacai Chen                                &env->CP0_PWBase);
7997e0896b0SHuacai Chen     if (err < 0) {
8007e0896b0SHuacai Chen         DPRINTF("%s: Failed to put CP0_PWBASE (%d)\n", __func__, err);
8017e0896b0SHuacai Chen         ret = err;
8027e0896b0SHuacai Chen     }
8037e0896b0SHuacai Chen     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWFIELD,
8047e0896b0SHuacai Chen                                &env->CP0_PWField);
8057e0896b0SHuacai Chen     if (err < 0) {
8067e0896b0SHuacai Chen         DPRINTF("%s: Failed to put CP0_PWField (%d)\n", __func__, err);
8077e0896b0SHuacai Chen         ret = err;
8087e0896b0SHuacai Chen     }
8097e0896b0SHuacai Chen     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWSIZE,
8107e0896b0SHuacai Chen                                &env->CP0_PWSize);
8117e0896b0SHuacai Chen     if (err < 0) {
8127e0896b0SHuacai Chen         DPRINTF("%s: Failed to put CP0_PWSIZE (%d)\n", __func__, err);
8137e0896b0SHuacai Chen         ret = err;
8147e0896b0SHuacai Chen     }
815fcf5ef2aSThomas Huth     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
816fcf5ef2aSThomas Huth     if (err < 0) {
817fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err);
818fcf5ef2aSThomas Huth         ret = err;
819fcf5ef2aSThomas Huth     }
8207e0896b0SHuacai Chen     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PWCTL, &env->CP0_PWCtl);
8217e0896b0SHuacai Chen     if (err < 0) {
8227e0896b0SHuacai Chen         DPRINTF("%s: Failed to put CP0_PWCTL (%d)\n", __func__, err);
8237e0896b0SHuacai Chen         ret = err;
8247e0896b0SHuacai Chen     }
825fcf5ef2aSThomas Huth     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
826fcf5ef2aSThomas Huth     if (err < 0) {
827fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err);
828fcf5ef2aSThomas Huth         ret = err;
829fcf5ef2aSThomas Huth     }
830fcf5ef2aSThomas Huth     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
831fcf5ef2aSThomas Huth                                  &env->CP0_BadVAddr);
832fcf5ef2aSThomas Huth     if (err < 0) {
833fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err);
834fcf5ef2aSThomas Huth         ret = err;
835fcf5ef2aSThomas Huth     }
836fcf5ef2aSThomas Huth 
837fcf5ef2aSThomas Huth     /* If VM clock stopped then state will be restored when it is restarted */
838fcf5ef2aSThomas Huth     if (runstate_is_running()) {
839fcf5ef2aSThomas Huth         err = kvm_mips_restore_count(cs);
840fcf5ef2aSThomas Huth         if (err < 0) {
841fcf5ef2aSThomas Huth             ret = err;
842fcf5ef2aSThomas Huth         }
843fcf5ef2aSThomas Huth     }
844fcf5ef2aSThomas Huth 
845fcf5ef2aSThomas Huth     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
846fcf5ef2aSThomas Huth                                  &env->CP0_EntryHi);
847fcf5ef2aSThomas Huth     if (err < 0) {
848fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err);
849fcf5ef2aSThomas Huth         ret = err;
850fcf5ef2aSThomas Huth     }
851fcf5ef2aSThomas Huth     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
852fcf5ef2aSThomas Huth                                &env->CP0_Compare);
853fcf5ef2aSThomas Huth     if (err < 0) {
854fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err);
855fcf5ef2aSThomas Huth         ret = err;
856fcf5ef2aSThomas Huth     }
857fcf5ef2aSThomas Huth     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
858fcf5ef2aSThomas Huth     if (err < 0) {
859fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err);
860fcf5ef2aSThomas Huth         ret = err;
861fcf5ef2aSThomas Huth     }
862fcf5ef2aSThomas Huth     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
863fcf5ef2aSThomas Huth     if (err < 0) {
864fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err);
865fcf5ef2aSThomas Huth         ret = err;
866fcf5ef2aSThomas Huth     }
867fcf5ef2aSThomas Huth     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid);
868fcf5ef2aSThomas Huth     if (err < 0) {
869fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err);
870fcf5ef2aSThomas Huth         ret = err;
871fcf5ef2aSThomas Huth     }
8727e0896b0SHuacai Chen     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EBASE, &env->CP0_EBase);
8737e0896b0SHuacai Chen     if (err < 0) {
8747e0896b0SHuacai Chen         DPRINTF("%s: Failed to put CP0_EBASE (%d)\n", __func__, err);
8757e0896b0SHuacai Chen         ret = err;
8767e0896b0SHuacai Chen     }
877fcf5ef2aSThomas Huth     err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG,
878fcf5ef2aSThomas Huth                                   &env->CP0_Config0,
879fcf5ef2aSThomas Huth                                   KVM_REG_MIPS_CP0_CONFIG_MASK);
880fcf5ef2aSThomas Huth     if (err < 0) {
881fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to change CP0_CONFIG (%d)\n", __func__, err);
882fcf5ef2aSThomas Huth         ret = err;
883fcf5ef2aSThomas Huth     }
884fcf5ef2aSThomas Huth     err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1,
885fcf5ef2aSThomas Huth                                   &env->CP0_Config1,
886fcf5ef2aSThomas Huth                                   KVM_REG_MIPS_CP0_CONFIG1_MASK);
887fcf5ef2aSThomas Huth     if (err < 0) {
888fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to change CP0_CONFIG1 (%d)\n", __func__, err);
889fcf5ef2aSThomas Huth         ret = err;
890fcf5ef2aSThomas Huth     }
891fcf5ef2aSThomas Huth     err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2,
892fcf5ef2aSThomas Huth                                   &env->CP0_Config2,
893fcf5ef2aSThomas Huth                                   KVM_REG_MIPS_CP0_CONFIG2_MASK);
894fcf5ef2aSThomas Huth     if (err < 0) {
895fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to change CP0_CONFIG2 (%d)\n", __func__, err);
896fcf5ef2aSThomas Huth         ret = err;
897fcf5ef2aSThomas Huth     }
898fcf5ef2aSThomas Huth     err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3,
899fcf5ef2aSThomas Huth                                   &env->CP0_Config3,
900fcf5ef2aSThomas Huth                                   KVM_REG_MIPS_CP0_CONFIG3_MASK);
901fcf5ef2aSThomas Huth     if (err < 0) {
902fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to change CP0_CONFIG3 (%d)\n", __func__, err);
903fcf5ef2aSThomas Huth         ret = err;
904fcf5ef2aSThomas Huth     }
905fcf5ef2aSThomas Huth     err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4,
906fcf5ef2aSThomas Huth                                   &env->CP0_Config4,
907fcf5ef2aSThomas Huth                                   KVM_REG_MIPS_CP0_CONFIG4_MASK);
908fcf5ef2aSThomas Huth     if (err < 0) {
909fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to change CP0_CONFIG4 (%d)\n", __func__, err);
910fcf5ef2aSThomas Huth         ret = err;
911fcf5ef2aSThomas Huth     }
912fcf5ef2aSThomas Huth     err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5,
913fcf5ef2aSThomas Huth                                   &env->CP0_Config5,
914fcf5ef2aSThomas Huth                                   KVM_REG_MIPS_CP0_CONFIG5_MASK);
915fcf5ef2aSThomas Huth     if (err < 0) {
916fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to change CP0_CONFIG5 (%d)\n", __func__, err);
917fcf5ef2aSThomas Huth         ret = err;
918fcf5ef2aSThomas Huth     }
9197e0896b0SHuacai Chen     err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG6,
9207e0896b0SHuacai Chen                                   &env->CP0_Config6,
9217e0896b0SHuacai Chen                                   KVM_REG_MIPS_CP0_CONFIG6_MASK);
9227e0896b0SHuacai Chen     if (err < 0) {
9237e0896b0SHuacai Chen         DPRINTF("%s: Failed to change CP0_CONFIG6 (%d)\n", __func__, err);
9247e0896b0SHuacai Chen         ret = err;
9257e0896b0SHuacai Chen     }
9267e0896b0SHuacai Chen     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_XCONTEXT,
9277e0896b0SHuacai Chen                                  &env->CP0_XContext);
9287e0896b0SHuacai Chen     if (err < 0) {
9297e0896b0SHuacai Chen         DPRINTF("%s: Failed to put CP0_XCONTEXT (%d)\n", __func__, err);
9307e0896b0SHuacai Chen         ret = err;
9317e0896b0SHuacai Chen     }
932fcf5ef2aSThomas Huth     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
933fcf5ef2aSThomas Huth                                  &env->CP0_ErrorEPC);
934fcf5ef2aSThomas Huth     if (err < 0) {
935fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err);
936fcf5ef2aSThomas Huth         ret = err;
937fcf5ef2aSThomas Huth     }
9387e0896b0SHuacai Chen     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH1,
9397e0896b0SHuacai Chen                                  &env->CP0_KScratch[0]);
9407e0896b0SHuacai Chen     if (err < 0) {
9417e0896b0SHuacai Chen         DPRINTF("%s: Failed to put CP0_KSCRATCH1 (%d)\n", __func__, err);
9427e0896b0SHuacai Chen         ret = err;
9437e0896b0SHuacai Chen     }
9447e0896b0SHuacai Chen     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH2,
9457e0896b0SHuacai Chen                                  &env->CP0_KScratch[1]);
9467e0896b0SHuacai Chen     if (err < 0) {
9477e0896b0SHuacai Chen         DPRINTF("%s: Failed to put CP0_KSCRATCH2 (%d)\n", __func__, err);
9487e0896b0SHuacai Chen         ret = err;
9497e0896b0SHuacai Chen     }
9507e0896b0SHuacai Chen     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH3,
9517e0896b0SHuacai Chen                                  &env->CP0_KScratch[2]);
9527e0896b0SHuacai Chen     if (err < 0) {
9537e0896b0SHuacai Chen         DPRINTF("%s: Failed to put CP0_KSCRATCH3 (%d)\n", __func__, err);
9547e0896b0SHuacai Chen         ret = err;
9557e0896b0SHuacai Chen     }
9567e0896b0SHuacai Chen     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH4,
9577e0896b0SHuacai Chen                                  &env->CP0_KScratch[3]);
9587e0896b0SHuacai Chen     if (err < 0) {
9597e0896b0SHuacai Chen         DPRINTF("%s: Failed to put CP0_KSCRATCH4 (%d)\n", __func__, err);
9607e0896b0SHuacai Chen         ret = err;
9617e0896b0SHuacai Chen     }
9627e0896b0SHuacai Chen     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH5,
9637e0896b0SHuacai Chen                                  &env->CP0_KScratch[4]);
9647e0896b0SHuacai Chen     if (err < 0) {
9657e0896b0SHuacai Chen         DPRINTF("%s: Failed to put CP0_KSCRATCH5 (%d)\n", __func__, err);
9667e0896b0SHuacai Chen         ret = err;
9677e0896b0SHuacai Chen     }
9687e0896b0SHuacai Chen     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH6,
9697e0896b0SHuacai Chen                                  &env->CP0_KScratch[5]);
9707e0896b0SHuacai Chen     if (err < 0) {
9717e0896b0SHuacai Chen         DPRINTF("%s: Failed to put CP0_KSCRATCH6 (%d)\n", __func__, err);
9727e0896b0SHuacai Chen         ret = err;
9737e0896b0SHuacai Chen     }
974fcf5ef2aSThomas Huth 
975fcf5ef2aSThomas Huth     return ret;
976fcf5ef2aSThomas Huth }
977fcf5ef2aSThomas Huth 
978fcf5ef2aSThomas Huth static int kvm_mips_get_cp0_registers(CPUState *cs)
979fcf5ef2aSThomas Huth {
980fcf5ef2aSThomas Huth     MIPSCPU *cpu = MIPS_CPU(cs);
981fcf5ef2aSThomas Huth     CPUMIPSState *env = &cpu->env;
982fcf5ef2aSThomas Huth     int err, ret = 0;
983fcf5ef2aSThomas Huth 
984fcf5ef2aSThomas Huth     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
985fcf5ef2aSThomas Huth     if (err < 0) {
986fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err);
987fcf5ef2aSThomas Huth         ret = err;
988fcf5ef2aSThomas Huth     }
9897e0896b0SHuacai Chen     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_RANDOM, &env->CP0_Random);
9907e0896b0SHuacai Chen     if (err < 0) {
9917e0896b0SHuacai Chen         DPRINTF("%s: Failed to get CP0_RANDOM (%d)\n", __func__, err);
9927e0896b0SHuacai Chen         ret = err;
9937e0896b0SHuacai Chen     }
994fcf5ef2aSThomas Huth     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
995fcf5ef2aSThomas Huth                                  &env->CP0_Context);
996fcf5ef2aSThomas Huth     if (err < 0) {
997fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err);
998fcf5ef2aSThomas Huth         ret = err;
999fcf5ef2aSThomas Huth     }
1000fcf5ef2aSThomas Huth     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
1001fcf5ef2aSThomas Huth                                  &env->active_tc.CP0_UserLocal);
1002fcf5ef2aSThomas Huth     if (err < 0) {
1003fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err);
1004fcf5ef2aSThomas Huth         ret = err;
1005fcf5ef2aSThomas Huth     }
1006fcf5ef2aSThomas Huth     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
1007fcf5ef2aSThomas Huth                                &env->CP0_PageMask);
1008fcf5ef2aSThomas Huth     if (err < 0) {
1009fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err);
1010fcf5ef2aSThomas Huth         ret = err;
1011fcf5ef2aSThomas Huth     }
10127e0896b0SHuacai Chen     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEGRAIN,
10137e0896b0SHuacai Chen                                &env->CP0_PageGrain);
10147e0896b0SHuacai Chen     if (err < 0) {
10157e0896b0SHuacai Chen         DPRINTF("%s: Failed to get CP0_PAGEGRAIN (%d)\n", __func__, err);
10167e0896b0SHuacai Chen         ret = err;
10177e0896b0SHuacai Chen     }
10187e0896b0SHuacai Chen     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWBASE,
10197e0896b0SHuacai Chen                                &env->CP0_PWBase);
10207e0896b0SHuacai Chen     if (err < 0) {
10217e0896b0SHuacai Chen         DPRINTF("%s: Failed to get CP0_PWBASE (%d)\n", __func__, err);
10227e0896b0SHuacai Chen         ret = err;
10237e0896b0SHuacai Chen     }
10247e0896b0SHuacai Chen     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWFIELD,
10257e0896b0SHuacai Chen                                &env->CP0_PWField);
10267e0896b0SHuacai Chen     if (err < 0) {
10277e0896b0SHuacai Chen         DPRINTF("%s: Failed to get CP0_PWFIELD (%d)\n", __func__, err);
10287e0896b0SHuacai Chen         ret = err;
10297e0896b0SHuacai Chen     }
10307e0896b0SHuacai Chen     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWSIZE,
10317e0896b0SHuacai Chen                                &env->CP0_PWSize);
10327e0896b0SHuacai Chen     if (err < 0) {
10337e0896b0SHuacai Chen         DPRINTF("%s: Failed to get CP0_PWSIZE (%d)\n", __func__, err);
10347e0896b0SHuacai Chen         ret = err;
10357e0896b0SHuacai Chen     }
1036fcf5ef2aSThomas Huth     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
1037fcf5ef2aSThomas Huth     if (err < 0) {
1038fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err);
1039fcf5ef2aSThomas Huth         ret = err;
1040fcf5ef2aSThomas Huth     }
10417e0896b0SHuacai Chen     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PWCTL, &env->CP0_PWCtl);
10427e0896b0SHuacai Chen     if (err < 0) {
10437e0896b0SHuacai Chen         DPRINTF("%s: Failed to get CP0_PWCtl (%d)\n", __func__, err);
10447e0896b0SHuacai Chen         ret = err;
10457e0896b0SHuacai Chen     }
1046fcf5ef2aSThomas Huth     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
1047fcf5ef2aSThomas Huth     if (err < 0) {
1048fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err);
1049fcf5ef2aSThomas Huth         ret = err;
1050fcf5ef2aSThomas Huth     }
1051fcf5ef2aSThomas Huth     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
1052fcf5ef2aSThomas Huth                                  &env->CP0_BadVAddr);
1053fcf5ef2aSThomas Huth     if (err < 0) {
1054fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err);
1055fcf5ef2aSThomas Huth         ret = err;
1056fcf5ef2aSThomas Huth     }
1057fcf5ef2aSThomas Huth     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
1058fcf5ef2aSThomas Huth                                  &env->CP0_EntryHi);
1059fcf5ef2aSThomas Huth     if (err < 0) {
1060fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err);
1061fcf5ef2aSThomas Huth         ret = err;
1062fcf5ef2aSThomas Huth     }
1063fcf5ef2aSThomas Huth     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
1064fcf5ef2aSThomas Huth                                &env->CP0_Compare);
1065fcf5ef2aSThomas Huth     if (err < 0) {
1066fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err);
1067fcf5ef2aSThomas Huth         ret = err;
1068fcf5ef2aSThomas Huth     }
1069fcf5ef2aSThomas Huth     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
1070fcf5ef2aSThomas Huth     if (err < 0) {
1071fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err);
1072fcf5ef2aSThomas Huth         ret = err;
1073fcf5ef2aSThomas Huth     }
1074fcf5ef2aSThomas Huth 
1075fcf5ef2aSThomas Huth     /* If VM clock stopped then state was already saved when it was stopped */
1076fcf5ef2aSThomas Huth     if (runstate_is_running()) {
1077fcf5ef2aSThomas Huth         err = kvm_mips_save_count(cs);
1078fcf5ef2aSThomas Huth         if (err < 0) {
1079fcf5ef2aSThomas Huth             ret = err;
1080fcf5ef2aSThomas Huth         }
1081fcf5ef2aSThomas Huth     }
1082fcf5ef2aSThomas Huth 
1083fcf5ef2aSThomas Huth     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
1084fcf5ef2aSThomas Huth     if (err < 0) {
1085fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err);
1086fcf5ef2aSThomas Huth         ret = err;
1087fcf5ef2aSThomas Huth     }
1088fcf5ef2aSThomas Huth     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid);
1089fcf5ef2aSThomas Huth     if (err < 0) {
1090fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err);
1091fcf5ef2aSThomas Huth         ret = err;
1092fcf5ef2aSThomas Huth     }
10937e0896b0SHuacai Chen     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EBASE, &env->CP0_EBase);
10947e0896b0SHuacai Chen     if (err < 0) {
10957e0896b0SHuacai Chen         DPRINTF("%s: Failed to get CP0_EBASE (%d)\n", __func__, err);
10967e0896b0SHuacai Chen         ret = err;
10977e0896b0SHuacai Chen     }
1098fcf5ef2aSThomas Huth     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, &env->CP0_Config0);
1099fcf5ef2aSThomas Huth     if (err < 0) {
1100fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_CONFIG (%d)\n", __func__, err);
1101fcf5ef2aSThomas Huth         ret = err;
1102fcf5ef2aSThomas Huth     }
1103fcf5ef2aSThomas Huth     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, &env->CP0_Config1);
1104fcf5ef2aSThomas Huth     if (err < 0) {
1105fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_CONFIG1 (%d)\n", __func__, err);
1106fcf5ef2aSThomas Huth         ret = err;
1107fcf5ef2aSThomas Huth     }
1108fcf5ef2aSThomas Huth     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG2, &env->CP0_Config2);
1109fcf5ef2aSThomas Huth     if (err < 0) {
1110fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_CONFIG2 (%d)\n", __func__, err);
1111fcf5ef2aSThomas Huth         ret = err;
1112fcf5ef2aSThomas Huth     }
1113fcf5ef2aSThomas Huth     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG3, &env->CP0_Config3);
1114fcf5ef2aSThomas Huth     if (err < 0) {
1115fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_CONFIG3 (%d)\n", __func__, err);
1116fcf5ef2aSThomas Huth         ret = err;
1117fcf5ef2aSThomas Huth     }
1118fcf5ef2aSThomas Huth     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG4, &env->CP0_Config4);
1119fcf5ef2aSThomas Huth     if (err < 0) {
1120fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_CONFIG4 (%d)\n", __func__, err);
1121fcf5ef2aSThomas Huth         ret = err;
1122fcf5ef2aSThomas Huth     }
1123fcf5ef2aSThomas Huth     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, &env->CP0_Config5);
1124fcf5ef2aSThomas Huth     if (err < 0) {
1125fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_CONFIG5 (%d)\n", __func__, err);
1126fcf5ef2aSThomas Huth         ret = err;
1127fcf5ef2aSThomas Huth     }
11287e0896b0SHuacai Chen     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG6, &env->CP0_Config6);
11297e0896b0SHuacai Chen     if (err < 0) {
11307e0896b0SHuacai Chen         DPRINTF("%s: Failed to get CP0_CONFIG6 (%d)\n", __func__, err);
11317e0896b0SHuacai Chen         ret = err;
11327e0896b0SHuacai Chen     }
11337e0896b0SHuacai Chen     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_XCONTEXT,
11347e0896b0SHuacai Chen                                  &env->CP0_XContext);
11357e0896b0SHuacai Chen     if (err < 0) {
11367e0896b0SHuacai Chen         DPRINTF("%s: Failed to get CP0_XCONTEXT (%d)\n", __func__, err);
11377e0896b0SHuacai Chen         ret = err;
11387e0896b0SHuacai Chen     }
1139fcf5ef2aSThomas Huth     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
1140fcf5ef2aSThomas Huth                                  &env->CP0_ErrorEPC);
1141fcf5ef2aSThomas Huth     if (err < 0) {
1142fcf5ef2aSThomas Huth         DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err);
1143fcf5ef2aSThomas Huth         ret = err;
1144fcf5ef2aSThomas Huth     }
11457e0896b0SHuacai Chen     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH1,
11467e0896b0SHuacai Chen                                  &env->CP0_KScratch[0]);
11477e0896b0SHuacai Chen     if (err < 0) {
11487e0896b0SHuacai Chen         DPRINTF("%s: Failed to get CP0_KSCRATCH1 (%d)\n", __func__, err);
11497e0896b0SHuacai Chen         ret = err;
11507e0896b0SHuacai Chen     }
11517e0896b0SHuacai Chen     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH2,
11527e0896b0SHuacai Chen                                  &env->CP0_KScratch[1]);
11537e0896b0SHuacai Chen     if (err < 0) {
11547e0896b0SHuacai Chen         DPRINTF("%s: Failed to get CP0_KSCRATCH2 (%d)\n", __func__, err);
11557e0896b0SHuacai Chen         ret = err;
11567e0896b0SHuacai Chen     }
11577e0896b0SHuacai Chen     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH3,
11587e0896b0SHuacai Chen                                  &env->CP0_KScratch[2]);
11597e0896b0SHuacai Chen     if (err < 0) {
11607e0896b0SHuacai Chen         DPRINTF("%s: Failed to get CP0_KSCRATCH3 (%d)\n", __func__, err);
11617e0896b0SHuacai Chen         ret = err;
11627e0896b0SHuacai Chen     }
11637e0896b0SHuacai Chen     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH4,
11647e0896b0SHuacai Chen                                  &env->CP0_KScratch[3]);
11657e0896b0SHuacai Chen     if (err < 0) {
11667e0896b0SHuacai Chen         DPRINTF("%s: Failed to get CP0_KSCRATCH4 (%d)\n", __func__, err);
11677e0896b0SHuacai Chen         ret = err;
11687e0896b0SHuacai Chen     }
11697e0896b0SHuacai Chen     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH5,
11707e0896b0SHuacai Chen                                  &env->CP0_KScratch[4]);
11717e0896b0SHuacai Chen     if (err < 0) {
11727e0896b0SHuacai Chen         DPRINTF("%s: Failed to get CP0_KSCRATCH5 (%d)\n", __func__, err);
11737e0896b0SHuacai Chen         ret = err;
11747e0896b0SHuacai Chen     }
11757e0896b0SHuacai Chen     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH6,
11767e0896b0SHuacai Chen                                  &env->CP0_KScratch[5]);
11777e0896b0SHuacai Chen     if (err < 0) {
11787e0896b0SHuacai Chen         DPRINTF("%s: Failed to get CP0_KSCRATCH6 (%d)\n", __func__, err);
11797e0896b0SHuacai Chen         ret = err;
11807e0896b0SHuacai Chen     }
1181fcf5ef2aSThomas Huth 
1182fcf5ef2aSThomas Huth     return ret;
1183fcf5ef2aSThomas Huth }
1184fcf5ef2aSThomas Huth 
1185fcf5ef2aSThomas Huth int kvm_arch_put_registers(CPUState *cs, int level)
1186fcf5ef2aSThomas Huth {
1187fcf5ef2aSThomas Huth     MIPSCPU *cpu = MIPS_CPU(cs);
1188fcf5ef2aSThomas Huth     CPUMIPSState *env = &cpu->env;
1189fcf5ef2aSThomas Huth     struct kvm_regs regs;
1190fcf5ef2aSThomas Huth     int ret;
1191fcf5ef2aSThomas Huth     int i;
1192fcf5ef2aSThomas Huth 
1193fcf5ef2aSThomas Huth     /* Set the registers based on QEMU's view of things */
1194fcf5ef2aSThomas Huth     for (i = 0; i < 32; i++) {
1195fcf5ef2aSThomas Huth         regs.gpr[i] = (int64_t)(target_long)env->active_tc.gpr[i];
1196fcf5ef2aSThomas Huth     }
1197fcf5ef2aSThomas Huth 
1198fcf5ef2aSThomas Huth     regs.hi = (int64_t)(target_long)env->active_tc.HI[0];
1199fcf5ef2aSThomas Huth     regs.lo = (int64_t)(target_long)env->active_tc.LO[0];
1200fcf5ef2aSThomas Huth     regs.pc = (int64_t)(target_long)env->active_tc.PC;
1201fcf5ef2aSThomas Huth 
1202fcf5ef2aSThomas Huth     ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
1203fcf5ef2aSThomas Huth 
1204fcf5ef2aSThomas Huth     if (ret < 0) {
1205fcf5ef2aSThomas Huth         return ret;
1206fcf5ef2aSThomas Huth     }
1207fcf5ef2aSThomas Huth 
1208fcf5ef2aSThomas Huth     ret = kvm_mips_put_cp0_registers(cs, level);
1209fcf5ef2aSThomas Huth     if (ret < 0) {
1210fcf5ef2aSThomas Huth         return ret;
1211fcf5ef2aSThomas Huth     }
1212fcf5ef2aSThomas Huth 
1213fcf5ef2aSThomas Huth     ret = kvm_mips_put_fpu_registers(cs, level);
1214fcf5ef2aSThomas Huth     if (ret < 0) {
1215fcf5ef2aSThomas Huth         return ret;
1216fcf5ef2aSThomas Huth     }
1217fcf5ef2aSThomas Huth 
1218fcf5ef2aSThomas Huth     return ret;
1219fcf5ef2aSThomas Huth }
1220fcf5ef2aSThomas Huth 
1221fcf5ef2aSThomas Huth int kvm_arch_get_registers(CPUState *cs)
1222fcf5ef2aSThomas Huth {
1223fcf5ef2aSThomas Huth     MIPSCPU *cpu = MIPS_CPU(cs);
1224fcf5ef2aSThomas Huth     CPUMIPSState *env = &cpu->env;
1225fcf5ef2aSThomas Huth     int ret = 0;
1226fcf5ef2aSThomas Huth     struct kvm_regs regs;
1227fcf5ef2aSThomas Huth     int i;
1228fcf5ef2aSThomas Huth 
1229fcf5ef2aSThomas Huth     /* Get the current register set as KVM seems it */
1230fcf5ef2aSThomas Huth     ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
1231fcf5ef2aSThomas Huth 
1232fcf5ef2aSThomas Huth     if (ret < 0) {
1233fcf5ef2aSThomas Huth         return ret;
1234fcf5ef2aSThomas Huth     }
1235fcf5ef2aSThomas Huth 
1236fcf5ef2aSThomas Huth     for (i = 0; i < 32; i++) {
1237fcf5ef2aSThomas Huth         env->active_tc.gpr[i] = regs.gpr[i];
1238fcf5ef2aSThomas Huth     }
1239fcf5ef2aSThomas Huth 
1240fcf5ef2aSThomas Huth     env->active_tc.HI[0] = regs.hi;
1241fcf5ef2aSThomas Huth     env->active_tc.LO[0] = regs.lo;
1242fcf5ef2aSThomas Huth     env->active_tc.PC = regs.pc;
1243fcf5ef2aSThomas Huth 
1244fcf5ef2aSThomas Huth     kvm_mips_get_cp0_registers(cs);
1245fcf5ef2aSThomas Huth     kvm_mips_get_fpu_registers(cs);
1246fcf5ef2aSThomas Huth 
1247fcf5ef2aSThomas Huth     return ret;
1248fcf5ef2aSThomas Huth }
1249fcf5ef2aSThomas Huth 
1250fcf5ef2aSThomas Huth int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
1251fcf5ef2aSThomas Huth                              uint64_t address, uint32_t data, PCIDevice *dev)
1252fcf5ef2aSThomas Huth {
1253fcf5ef2aSThomas Huth     return 0;
1254fcf5ef2aSThomas Huth }
1255fcf5ef2aSThomas Huth 
1256fcf5ef2aSThomas Huth int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
1257fcf5ef2aSThomas Huth                                 int vector, PCIDevice *dev)
1258fcf5ef2aSThomas Huth {
1259fcf5ef2aSThomas Huth     return 0;
1260fcf5ef2aSThomas Huth }
1261fcf5ef2aSThomas Huth 
1262fcf5ef2aSThomas Huth int kvm_arch_release_virq_post(int virq)
1263fcf5ef2aSThomas Huth {
1264fcf5ef2aSThomas Huth     return 0;
1265fcf5ef2aSThomas Huth }
1266fcf5ef2aSThomas Huth 
1267fcf5ef2aSThomas Huth int kvm_arch_msi_data_to_gsi(uint32_t data)
1268fcf5ef2aSThomas Huth {
1269fcf5ef2aSThomas Huth     abort();
1270fcf5ef2aSThomas Huth }
1271719d109bSHuacai Chen 
1272719d109bSHuacai Chen int mips_kvm_type(MachineState *machine, const char *vm_type)
1273719d109bSHuacai Chen {
1274719d109bSHuacai Chen #if defined(KVM_CAP_MIPS_VZ) || defined(KVM_CAP_MIPS_TE)
1275719d109bSHuacai Chen     int r;
1276719d109bSHuacai Chen     KVMState *s = KVM_STATE(machine->accelerator);
1277719d109bSHuacai Chen #endif
1278719d109bSHuacai Chen 
1279719d109bSHuacai Chen #if defined(KVM_CAP_MIPS_VZ)
1280719d109bSHuacai Chen     r = kvm_check_extension(s, KVM_CAP_MIPS_VZ);
1281719d109bSHuacai Chen     if (r > 0) {
1282719d109bSHuacai Chen         return KVM_VM_MIPS_VZ;
1283719d109bSHuacai Chen     }
1284719d109bSHuacai Chen #endif
1285719d109bSHuacai Chen 
1286719d109bSHuacai Chen #if defined(KVM_CAP_MIPS_TE)
1287719d109bSHuacai Chen     r = kvm_check_extension(s, KVM_CAP_MIPS_TE);
1288719d109bSHuacai Chen     if (r > 0) {
1289719d109bSHuacai Chen         return KVM_VM_MIPS_TE;
1290719d109bSHuacai Chen     }
1291719d109bSHuacai Chen #endif
1292719d109bSHuacai Chen 
1293719d109bSHuacai Chen     return -1;
1294719d109bSHuacai Chen }
1295