1 /* 2 * MIPS internal definitions and helpers 3 * 4 * This work is licensed under the terms of the GNU GPL, version 2 or later. 5 * See the COPYING file in the top-level directory. 6 */ 7 8 #ifndef MIPS_INTERNAL_H 9 #define MIPS_INTERNAL_H 10 11 #include "fpu/softfloat-helpers.h" 12 13 /* 14 * MMU types, the first four entries have the same layout as the 15 * CP0C0_MT field. 16 */ 17 enum mips_mmu_types { 18 MMU_TYPE_NONE, 19 MMU_TYPE_R4000, 20 MMU_TYPE_RESERVED, 21 MMU_TYPE_FMT, 22 MMU_TYPE_R3000, 23 MMU_TYPE_R6000, 24 MMU_TYPE_R8000 25 }; 26 27 struct mips_def_t { 28 const char *name; 29 int32_t CP0_PRid; 30 int32_t CP0_Config0; 31 int32_t CP0_Config1; 32 int32_t CP0_Config2; 33 int32_t CP0_Config3; 34 int32_t CP0_Config4; 35 int32_t CP0_Config4_rw_bitmask; 36 int32_t CP0_Config5; 37 int32_t CP0_Config5_rw_bitmask; 38 int32_t CP0_Config6; 39 int32_t CP0_Config7; 40 target_ulong CP0_LLAddr_rw_bitmask; 41 int CP0_LLAddr_shift; 42 int32_t SYNCI_Step; 43 int32_t CCRes; 44 int32_t CP0_Status_rw_bitmask; 45 int32_t CP0_TCStatus_rw_bitmask; 46 int32_t CP0_SRSCtl; 47 int32_t CP1_fcr0; 48 int32_t CP1_fcr31_rw_bitmask; 49 int32_t CP1_fcr31; 50 int32_t MSAIR; 51 int32_t SEGBITS; 52 int32_t PABITS; 53 int32_t CP0_SRSConf0_rw_bitmask; 54 int32_t CP0_SRSConf0; 55 int32_t CP0_SRSConf1_rw_bitmask; 56 int32_t CP0_SRSConf1; 57 int32_t CP0_SRSConf2_rw_bitmask; 58 int32_t CP0_SRSConf2; 59 int32_t CP0_SRSConf3_rw_bitmask; 60 int32_t CP0_SRSConf3; 61 int32_t CP0_SRSConf4_rw_bitmask; 62 int32_t CP0_SRSConf4; 63 int32_t CP0_PageGrain_rw_bitmask; 64 int32_t CP0_PageGrain; 65 target_ulong CP0_EBaseWG_rw_bitmask; 66 uint64_t insn_flags; 67 enum mips_mmu_types mmu_type; 68 int32_t SAARP; 69 }; 70 71 extern const struct mips_def_t mips_defs[]; 72 extern const int mips_defs_number; 73 74 enum CPUMIPSMSADataFormat { 75 DF_BYTE = 0, 76 DF_HALF, 77 DF_WORD, 78 DF_DOUBLE 79 }; 80 81 void mips_cpu_do_interrupt(CPUState *cpu); 82 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); 83 void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 84 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 85 int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 86 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 87 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 88 MMUAccessType access_type, 89 int mmu_idx, uintptr_t retaddr); 90 91 #if !defined(CONFIG_USER_ONLY) 92 93 typedef struct r4k_tlb_t r4k_tlb_t; 94 struct r4k_tlb_t { 95 target_ulong VPN; 96 uint32_t PageMask; 97 uint16_t ASID; 98 unsigned int G:1; 99 unsigned int C0:3; 100 unsigned int C1:3; 101 unsigned int V0:1; 102 unsigned int V1:1; 103 unsigned int D0:1; 104 unsigned int D1:1; 105 unsigned int XI0:1; 106 unsigned int XI1:1; 107 unsigned int RI0:1; 108 unsigned int RI1:1; 109 unsigned int EHINV:1; 110 uint64_t PFN[2]; 111 }; 112 113 struct CPUMIPSTLBContext { 114 uint32_t nb_tlb; 115 uint32_t tlb_in_use; 116 int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot, 117 target_ulong address, int rw, int access_type); 118 void (*helper_tlbwi)(struct CPUMIPSState *env); 119 void (*helper_tlbwr)(struct CPUMIPSState *env); 120 void (*helper_tlbp)(struct CPUMIPSState *env); 121 void (*helper_tlbr)(struct CPUMIPSState *env); 122 void (*helper_tlbinv)(struct CPUMIPSState *env); 123 void (*helper_tlbinvf)(struct CPUMIPSState *env); 124 union { 125 struct { 126 r4k_tlb_t tlb[MIPS_TLB_MAX]; 127 } r4k; 128 } mmu; 129 }; 130 131 int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, 132 target_ulong address, int rw, int access_type); 133 int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, 134 target_ulong address, int rw, int access_type); 135 int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, 136 target_ulong address, int rw, int access_type); 137 void r4k_helper_tlbwi(CPUMIPSState *env); 138 void r4k_helper_tlbwr(CPUMIPSState *env); 139 void r4k_helper_tlbp(CPUMIPSState *env); 140 void r4k_helper_tlbr(CPUMIPSState *env); 141 void r4k_helper_tlbinv(CPUMIPSState *env); 142 void r4k_helper_tlbinvf(CPUMIPSState *env); 143 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); 144 145 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 146 vaddr addr, unsigned size, 147 MMUAccessType access_type, 148 int mmu_idx, MemTxAttrs attrs, 149 MemTxResult response, uintptr_t retaddr); 150 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, 151 int rw); 152 #endif 153 154 #define cpu_signal_handler cpu_mips_signal_handler 155 156 #ifndef CONFIG_USER_ONLY 157 extern const VMStateDescription vmstate_mips_cpu; 158 #endif 159 160 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) 161 { 162 return (env->CP0_Status & (1 << CP0St_IE)) && 163 !(env->CP0_Status & (1 << CP0St_EXL)) && 164 !(env->CP0_Status & (1 << CP0St_ERL)) && 165 !(env->hflags & MIPS_HFLAG_DM) && 166 /* 167 * Note that the TCStatus IXMT field is initialized to zero, 168 * and only MT capable cores can set it to one. So we don't 169 * need to check for MT capabilities here. 170 */ 171 !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); 172 } 173 174 /* Check if there is pending and not masked out interrupt */ 175 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) 176 { 177 int32_t pending; 178 int32_t status; 179 bool r; 180 181 pending = env->CP0_Cause & CP0Ca_IP_mask; 182 status = env->CP0_Status & CP0Ca_IP_mask; 183 184 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { 185 /* 186 * A MIPS configured with a vectorizing external interrupt controller 187 * will feed a vector into the Cause pending lines. The core treats 188 * the status lines as a vector level, not as indiviual masks. 189 */ 190 r = pending > status; 191 } else { 192 /* 193 * A MIPS configured with compatibility or VInt (Vectored Interrupts) 194 * treats the pending lines as individual interrupt lines, the status 195 * lines are individual masks. 196 */ 197 r = (pending & status) != 0; 198 } 199 return r; 200 } 201 202 void mips_tcg_init(void); 203 204 /* TODO QOM'ify CPU reset and remove */ 205 void cpu_state_reset(CPUMIPSState *s); 206 void cpu_mips_realize_env(CPUMIPSState *env); 207 208 /* cp0_timer.c */ 209 uint32_t cpu_mips_get_random(CPUMIPSState *env); 210 uint32_t cpu_mips_get_count(CPUMIPSState *env); 211 void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); 212 void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); 213 void cpu_mips_start_count(CPUMIPSState *env); 214 void cpu_mips_stop_count(CPUMIPSState *env); 215 216 /* helper.c */ 217 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 218 MMUAccessType access_type, int mmu_idx, 219 bool probe, uintptr_t retaddr); 220 221 /* op_helper.c */ 222 uint32_t float_class_s(uint32_t arg, float_status *fst); 223 uint64_t float_class_d(uint64_t arg, float_status *fst); 224 225 extern unsigned int ieee_rm[]; 226 int ieee_ex_to_mips(int xcpt); 227 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask); 228 229 static inline void restore_rounding_mode(CPUMIPSState *env) 230 { 231 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], 232 &env->active_fpu.fp_status); 233 } 234 235 static inline void restore_flush_mode(CPUMIPSState *env) 236 { 237 set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0, 238 &env->active_fpu.fp_status); 239 } 240 241 static inline void restore_snan_bit_mode(CPUMIPSState *env) 242 { 243 set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, 244 &env->active_fpu.fp_status); 245 } 246 247 static inline void restore_fp_status(CPUMIPSState *env) 248 { 249 restore_rounding_mode(env); 250 restore_flush_mode(env); 251 restore_snan_bit_mode(env); 252 } 253 254 static inline void restore_msa_fp_status(CPUMIPSState *env) 255 { 256 float_status *status = &env->active_tc.msa_fp_status; 257 int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM; 258 bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0; 259 260 set_float_rounding_mode(ieee_rm[rounding_mode], status); 261 set_flush_to_zero(flush_to_zero, status); 262 set_flush_inputs_to_zero(flush_to_zero, status); 263 } 264 265 static inline void restore_pamask(CPUMIPSState *env) 266 { 267 if (env->hflags & MIPS_HFLAG_ELPA) { 268 env->PAMask = (1ULL << env->PABITS) - 1; 269 } else { 270 env->PAMask = PAMASK_BASE; 271 } 272 } 273 274 static inline int mips_vpe_active(CPUMIPSState *env) 275 { 276 int active = 1; 277 278 /* Check that the VPE is enabled. */ 279 if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { 280 active = 0; 281 } 282 /* Check that the VPE is activated. */ 283 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { 284 active = 0; 285 } 286 287 /* 288 * Now verify that there are active thread contexts in the VPE. 289 * 290 * This assumes the CPU model will internally reschedule threads 291 * if the active one goes to sleep. If there are no threads available 292 * the active one will be in a sleeping state, and we can turn off 293 * the entire VPE. 294 */ 295 if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { 296 /* TC is not activated. */ 297 active = 0; 298 } 299 if (env->active_tc.CP0_TCHalt & 1) { 300 /* TC is in halt state. */ 301 active = 0; 302 } 303 304 return active; 305 } 306 307 static inline int mips_vp_active(CPUMIPSState *env) 308 { 309 CPUState *other_cs = first_cpu; 310 311 /* Check if the VP disabled other VPs (which means the VP is enabled) */ 312 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { 313 return 1; 314 } 315 316 /* Check if the virtual processor is disabled due to a DVP */ 317 CPU_FOREACH(other_cs) { 318 MIPSCPU *other_cpu = MIPS_CPU(other_cs); 319 if ((&other_cpu->env != env) && 320 ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) { 321 return 0; 322 } 323 } 324 return 1; 325 } 326 327 static inline void compute_hflags(CPUMIPSState *env) 328 { 329 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | 330 MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | 331 MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | 332 MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | 333 MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL); 334 if (env->CP0_Status & (1 << CP0St_ERL)) { 335 env->hflags |= MIPS_HFLAG_ERL; 336 } 337 if (!(env->CP0_Status & (1 << CP0St_EXL)) && 338 !(env->CP0_Status & (1 << CP0St_ERL)) && 339 !(env->hflags & MIPS_HFLAG_DM)) { 340 env->hflags |= (env->CP0_Status >> CP0St_KSU) & 341 MIPS_HFLAG_KSU; 342 } 343 #if defined(TARGET_MIPS64) 344 if ((env->insn_flags & ISA_MIPS3) && 345 (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || 346 (env->CP0_Status & (1 << CP0St_PX)) || 347 (env->CP0_Status & (1 << CP0St_UX)))) { 348 env->hflags |= MIPS_HFLAG_64; 349 } 350 351 if (!(env->insn_flags & ISA_MIPS3)) { 352 env->hflags |= MIPS_HFLAG_AWRAP; 353 } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && 354 !(env->CP0_Status & (1 << CP0St_UX))) { 355 env->hflags |= MIPS_HFLAG_AWRAP; 356 } else if (env->insn_flags & ISA_MIPS64R6) { 357 /* Address wrapping for Supervisor and Kernel is specified in R6 */ 358 if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) && 359 !(env->CP0_Status & (1 << CP0St_SX))) || 360 (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) && 361 !(env->CP0_Status & (1 << CP0St_KX)))) { 362 env->hflags |= MIPS_HFLAG_AWRAP; 363 } 364 } 365 #endif 366 if (((env->CP0_Status & (1 << CP0St_CU0)) && 367 !(env->insn_flags & ISA_MIPS32R6)) || 368 !(env->hflags & MIPS_HFLAG_KSU)) { 369 env->hflags |= MIPS_HFLAG_CP0; 370 } 371 if (env->CP0_Status & (1 << CP0St_CU1)) { 372 env->hflags |= MIPS_HFLAG_FPU; 373 } 374 if (env->CP0_Status & (1 << CP0St_FR)) { 375 env->hflags |= MIPS_HFLAG_F64; 376 } 377 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) && 378 (env->CP0_Config5 & (1 << CP0C5_SBRI))) { 379 env->hflags |= MIPS_HFLAG_SBRI; 380 } 381 if (env->insn_flags & ASE_DSP_R3) { 382 /* 383 * Our cpu supports DSP R3 ASE, so enable 384 * access to DSP R3 resources. 385 */ 386 if (env->CP0_Status & (1 << CP0St_MX)) { 387 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | 388 MIPS_HFLAG_DSP_R3; 389 } 390 } else if (env->insn_flags & ASE_DSP_R2) { 391 /* 392 * Our cpu supports DSP R2 ASE, so enable 393 * access to DSP R2 resources. 394 */ 395 if (env->CP0_Status & (1 << CP0St_MX)) { 396 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2; 397 } 398 399 } else if (env->insn_flags & ASE_DSP) { 400 /* 401 * Our cpu supports DSP ASE, so enable 402 * access to DSP resources. 403 */ 404 if (env->CP0_Status & (1 << CP0St_MX)) { 405 env->hflags |= MIPS_HFLAG_DSP; 406 } 407 408 } 409 if (env->insn_flags & ISA_MIPS32R2) { 410 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { 411 env->hflags |= MIPS_HFLAG_COP1X; 412 } 413 } else if (env->insn_flags & ISA_MIPS32) { 414 if (env->hflags & MIPS_HFLAG_64) { 415 env->hflags |= MIPS_HFLAG_COP1X; 416 } 417 } else if (env->insn_flags & ISA_MIPS4) { 418 /* 419 * All supported MIPS IV CPUs use the XX (CU3) to enable 420 * and disable the MIPS IV extensions to the MIPS III ISA. 421 * Some other MIPS IV CPUs ignore the bit, so the check here 422 * would be too restrictive for them. 423 */ 424 if (env->CP0_Status & (1U << CP0St_CU3)) { 425 env->hflags |= MIPS_HFLAG_COP1X; 426 } 427 } 428 if (env->insn_flags & ASE_MSA) { 429 if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { 430 env->hflags |= MIPS_HFLAG_MSA; 431 } 432 } 433 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { 434 if (env->CP0_Config5 & (1 << CP0C5_FRE)) { 435 env->hflags |= MIPS_HFLAG_FRE; 436 } 437 } 438 if (env->CP0_Config3 & (1 << CP0C3_LPA)) { 439 if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) { 440 env->hflags |= MIPS_HFLAG_ELPA; 441 } 442 } 443 } 444 445 void cpu_mips_tlb_flush(CPUMIPSState *env); 446 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); 447 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); 448 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); 449 450 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception, 451 int error_code, uintptr_t pc); 452 453 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, 454 uint32_t exception, 455 uintptr_t pc) 456 { 457 do_raise_exception_err(env, exception, 0, pc); 458 } 459 460 #endif 461