xref: /openbmc/qemu/target/mips/internal.h (revision 2df1eb27)
1 /*
2  * MIPS internal definitions and helpers
3  *
4  * This work is licensed under the terms of the GNU GPL, version 2 or later.
5  * See the COPYING file in the top-level directory.
6  */
7 
8 #ifndef MIPS_INTERNAL_H
9 #define MIPS_INTERNAL_H
10 
11 #include "exec/memattrs.h"
12 #ifdef CONFIG_TCG
13 #include "tcg/tcg-internal.h"
14 #endif
15 #include "cpu.h"
16 
17 /*
18  * MMU types, the first four entries have the same layout as the
19  * CP0C0_MT field.
20  */
21 enum mips_mmu_types {
22     MMU_TYPE_NONE       = 0,
23     MMU_TYPE_R4000      = 1,    /* Standard TLB */
24     MMU_TYPE_BAT        = 2,    /* Block Address Translation */
25     MMU_TYPE_FMT        = 3,    /* Fixed Mapping */
26     MMU_TYPE_DVF        = 4,    /* Dual VTLB and FTLB */
27     MMU_TYPE_R3000,
28     MMU_TYPE_R6000,
29     MMU_TYPE_R8000
30 };
31 
32 struct mips_def_t {
33     const char *name;
34     int32_t CP0_PRid;
35     int32_t CP0_Config0;
36     int32_t CP0_Config1;
37     int32_t CP0_Config2;
38     int32_t CP0_Config3;
39     int32_t CP0_Config4;
40     int32_t CP0_Config4_rw_bitmask;
41     int32_t CP0_Config5;
42     int32_t CP0_Config5_rw_bitmask;
43     int32_t CP0_Config6;
44     int32_t CP0_Config6_rw_bitmask;
45     int32_t CP0_Config7;
46     int32_t CP0_Config7_rw_bitmask;
47     target_ulong CP0_LLAddr_rw_bitmask;
48     int CP0_LLAddr_shift;
49     int32_t SYNCI_Step;
50     /*
51      * @CCRes: rate at which the coprocessor 0 counter increments
52      *
53      * The Count register acts as a timer, incrementing at a constant rate,
54      * whether or not an instruction is executed, retired, or any forward
55      * progress is made through the pipeline. The rate at which the counter
56      * increments is implementation dependent, and is a function of the
57      * pipeline clock of the processor, not the issue width of the processor.
58      */
59     int32_t CCRes;
60     int32_t CP0_Status_rw_bitmask;
61     int32_t CP0_TCStatus_rw_bitmask;
62     int32_t CP0_SRSCtl;
63     int32_t CP1_fcr0;
64     int32_t CP1_fcr31_rw_bitmask;
65     int32_t CP1_fcr31;
66     int32_t MSAIR;
67     int32_t SEGBITS;
68     int32_t PABITS;
69     int32_t CP0_SRSConf0_rw_bitmask;
70     int32_t CP0_SRSConf0;
71     int32_t CP0_SRSConf1_rw_bitmask;
72     int32_t CP0_SRSConf1;
73     int32_t CP0_SRSConf2_rw_bitmask;
74     int32_t CP0_SRSConf2;
75     int32_t CP0_SRSConf3_rw_bitmask;
76     int32_t CP0_SRSConf3;
77     int32_t CP0_SRSConf4_rw_bitmask;
78     int32_t CP0_SRSConf4;
79     int32_t CP0_PageGrain_rw_bitmask;
80     int32_t CP0_PageGrain;
81     target_ulong CP0_EBaseWG_rw_bitmask;
82     uint32_t lcsr_cpucfg1;
83     uint32_t lcsr_cpucfg2;
84     uint64_t insn_flags;
85     enum mips_mmu_types mmu_type;
86     int32_t SAARP;
87 };
88 
89 extern const char regnames[32][3];
90 extern const char fregnames[32][4];
91 
92 extern const struct mips_def_t mips_defs[];
93 extern const int mips_defs_number;
94 
95 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
96 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
97 
98 #define USEG_LIMIT      ((target_ulong)(int32_t)0x7FFFFFFFUL)
99 #define KSEG0_BASE      ((target_ulong)(int32_t)0x80000000UL)
100 #define KSEG1_BASE      ((target_ulong)(int32_t)0xA0000000UL)
101 #define KSEG2_BASE      ((target_ulong)(int32_t)0xC0000000UL)
102 #define KSEG3_BASE      ((target_ulong)(int32_t)0xE0000000UL)
103 
104 #if !defined(CONFIG_USER_ONLY)
105 
106 enum {
107     TLBRET_XI = -6,
108     TLBRET_RI = -5,
109     TLBRET_DIRTY = -4,
110     TLBRET_INVALID = -3,
111     TLBRET_NOMATCH = -2,
112     TLBRET_BADADDR = -1,
113     TLBRET_MATCH = 0
114 };
115 
116 int get_physical_address(CPUMIPSState *env, hwaddr *physical,
117                          int *prot, target_ulong real_address,
118                          MMUAccessType access_type, int mmu_idx);
119 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
120 
121 typedef struct r4k_tlb_t r4k_tlb_t;
122 struct r4k_tlb_t {
123     target_ulong VPN;
124     uint32_t PageMask;
125     uint16_t ASID;
126     uint32_t MMID;
127     unsigned int G:1;
128     unsigned int C0:3;
129     unsigned int C1:3;
130     unsigned int V0:1;
131     unsigned int V1:1;
132     unsigned int D0:1;
133     unsigned int D1:1;
134     unsigned int XI0:1;
135     unsigned int XI1:1;
136     unsigned int RI0:1;
137     unsigned int RI1:1;
138     unsigned int EHINV:1;
139     uint64_t PFN[2];
140 };
141 
142 struct CPUMIPSTLBContext {
143     uint32_t nb_tlb;
144     uint32_t tlb_in_use;
145     int (*map_address)(CPUMIPSState *env, hwaddr *physical, int *prot,
146                        target_ulong address, MMUAccessType access_type);
147     void (*helper_tlbwi)(CPUMIPSState *env);
148     void (*helper_tlbwr)(CPUMIPSState *env);
149     void (*helper_tlbp)(CPUMIPSState *env);
150     void (*helper_tlbr)(CPUMIPSState *env);
151     void (*helper_tlbinv)(CPUMIPSState *env);
152     void (*helper_tlbinvf)(CPUMIPSState *env);
153     union {
154         struct {
155             r4k_tlb_t tlb[MIPS_TLB_MAX];
156         } r4k;
157     } mmu;
158 };
159 
160 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
161 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
162 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
163 
164 extern const VMStateDescription vmstate_mips_cpu;
165 
166 #endif /* !CONFIG_USER_ONLY */
167 
168 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
169 {
170     return (env->CP0_Status & (1 << CP0St_IE)) &&
171         !(env->CP0_Status & (1 << CP0St_EXL)) &&
172         !(env->CP0_Status & (1 << CP0St_ERL)) &&
173         !(env->hflags & MIPS_HFLAG_DM) &&
174         /*
175          * Note that the TCStatus IXMT field is initialized to zero,
176          * and only MT capable cores can set it to one. So we don't
177          * need to check for MT capabilities here.
178          */
179         !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
180 }
181 
182 /* Check if there is pending and not masked out interrupt */
183 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
184 {
185     int32_t pending;
186     int32_t status;
187     bool r;
188 
189     pending = env->CP0_Cause & CP0Ca_IP_mask;
190     status = env->CP0_Status & CP0Ca_IP_mask;
191 
192     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
193         /*
194          * A MIPS configured with a vectorizing external interrupt controller
195          * will feed a vector into the Cause pending lines. The core treats
196          * the status lines as a vector level, not as individual masks.
197          */
198         r = pending > status;
199     } else {
200         /*
201          * A MIPS configured with compatibility or VInt (Vectored Interrupts)
202          * treats the pending lines as individual interrupt lines, the status
203          * lines are individual masks.
204          */
205         r = (pending & status) != 0;
206     }
207     return r;
208 }
209 
210 void msa_reset(CPUMIPSState *env);
211 
212 /* cp0_timer.c */
213 uint32_t cpu_mips_get_count(CPUMIPSState *env);
214 void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
215 void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
216 void cpu_mips_start_count(CPUMIPSState *env);
217 void cpu_mips_stop_count(CPUMIPSState *env);
218 
219 static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value)
220 {
221     env->active_tc.PC = value & ~(target_ulong)1;
222     if (value & 1) {
223         env->hflags |= MIPS_HFLAG_M16;
224     } else {
225         env->hflags &= ~(MIPS_HFLAG_M16);
226     }
227 }
228 
229 static inline void restore_pamask(CPUMIPSState *env)
230 {
231     if (env->hflags & MIPS_HFLAG_ELPA) {
232         env->PAMask = (1ULL << env->PABITS) - 1;
233     } else {
234         env->PAMask = PAMASK_BASE;
235     }
236 }
237 
238 static inline int mips_vpe_active(CPUMIPSState *env)
239 {
240     int active = 1;
241 
242     /* Check that the VPE is enabled.  */
243     if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
244         active = 0;
245     }
246     /* Check that the VPE is activated.  */
247     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
248         active = 0;
249     }
250 
251     /*
252      * Now verify that there are active thread contexts in the VPE.
253      *
254      * This assumes the CPU model will internally reschedule threads
255      * if the active one goes to sleep. If there are no threads available
256      * the active one will be in a sleeping state, and we can turn off
257      * the entire VPE.
258      */
259     if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
260         /* TC is not activated.  */
261         active = 0;
262     }
263     if (env->active_tc.CP0_TCHalt & 1) {
264         /* TC is in halt state.  */
265         active = 0;
266     }
267 
268     return active;
269 }
270 
271 static inline int mips_vp_active(CPUMIPSState *env)
272 {
273     CPUState *other_cs = first_cpu;
274 
275     /* Check if the VP disabled other VPs (which means the VP is enabled) */
276     if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
277         return 1;
278     }
279 
280     /* Check if the virtual processor is disabled due to a DVP */
281     CPU_FOREACH(other_cs) {
282         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
283         if ((&other_cpu->env != env) &&
284             ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
285             return 0;
286         }
287     }
288     return 1;
289 }
290 
291 static inline void compute_hflags(CPUMIPSState *env)
292 {
293     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
294                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
295                      MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
296                      MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
297                      MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
298     if (env->CP0_Status & (1 << CP0St_ERL)) {
299         env->hflags |= MIPS_HFLAG_ERL;
300     }
301     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
302         !(env->CP0_Status & (1 << CP0St_ERL)) &&
303         !(env->hflags & MIPS_HFLAG_DM)) {
304         env->hflags |= (env->CP0_Status >> CP0St_KSU) &
305                        MIPS_HFLAG_KSU;
306     }
307 #if defined(TARGET_MIPS64)
308     if ((env->insn_flags & ISA_MIPS3) &&
309         (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
310          (env->CP0_Status & (1 << CP0St_PX)) ||
311          (env->CP0_Status & (1 << CP0St_UX)))) {
312         env->hflags |= MIPS_HFLAG_64;
313     }
314 
315     if (!(env->insn_flags & ISA_MIPS3)) {
316         env->hflags |= MIPS_HFLAG_AWRAP;
317     } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
318                !(env->CP0_Status & (1 << CP0St_UX))) {
319         env->hflags |= MIPS_HFLAG_AWRAP;
320     } else if (env->insn_flags & ISA_MIPS_R6) {
321         /* Address wrapping for Supervisor and Kernel is specified in R6 */
322         if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
323              !(env->CP0_Status & (1 << CP0St_SX))) ||
324             (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
325              !(env->CP0_Status & (1 << CP0St_KX)))) {
326             env->hflags |= MIPS_HFLAG_AWRAP;
327         }
328     }
329 #endif
330     if (((env->CP0_Status & (1 << CP0St_CU0)) &&
331          !(env->insn_flags & ISA_MIPS_R6)) ||
332         !(env->hflags & MIPS_HFLAG_KSU)) {
333         env->hflags |= MIPS_HFLAG_CP0;
334     }
335     if (env->CP0_Status & (1 << CP0St_CU1)) {
336         env->hflags |= MIPS_HFLAG_FPU;
337     }
338     if (env->CP0_Status & (1 << CP0St_FR)) {
339         env->hflags |= MIPS_HFLAG_F64;
340     }
341     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
342         (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
343         env->hflags |= MIPS_HFLAG_SBRI;
344     }
345     if (env->insn_flags & ASE_DSP_R3) {
346         /*
347          * Our cpu supports DSP R3 ASE, so enable
348          * access to DSP R3 resources.
349          */
350         if (env->CP0_Status & (1 << CP0St_MX)) {
351             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
352                            MIPS_HFLAG_DSP_R3;
353         }
354     } else if (env->insn_flags & ASE_DSP_R2) {
355         /*
356          * Our cpu supports DSP R2 ASE, so enable
357          * access to DSP R2 resources.
358          */
359         if (env->CP0_Status & (1 << CP0St_MX)) {
360             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2;
361         }
362 
363     } else if (env->insn_flags & ASE_DSP) {
364         /*
365          * Our cpu supports DSP ASE, so enable
366          * access to DSP resources.
367          */
368         if (env->CP0_Status & (1 << CP0St_MX)) {
369             env->hflags |= MIPS_HFLAG_DSP;
370         }
371 
372     }
373     if (env->insn_flags & ISA_MIPS_R2) {
374         if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
375             env->hflags |= MIPS_HFLAG_COP1X;
376         }
377     } else if (env->insn_flags & ISA_MIPS_R1) {
378         if (env->hflags & MIPS_HFLAG_64) {
379             env->hflags |= MIPS_HFLAG_COP1X;
380         }
381     } else if (env->insn_flags & ISA_MIPS4) {
382         /*
383          * All supported MIPS IV CPUs use the XX (CU3) to enable
384          * and disable the MIPS IV extensions to the MIPS III ISA.
385          * Some other MIPS IV CPUs ignore the bit, so the check here
386          * would be too restrictive for them.
387          */
388         if (env->CP0_Status & (1U << CP0St_CU3)) {
389             env->hflags |= MIPS_HFLAG_COP1X;
390         }
391     }
392     if (ase_msa_available(env)) {
393         if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
394             env->hflags |= MIPS_HFLAG_MSA;
395         }
396     }
397     if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
398         if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
399             env->hflags |= MIPS_HFLAG_FRE;
400         }
401     }
402     if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
403         if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
404             env->hflags |= MIPS_HFLAG_ELPA;
405         }
406     }
407 }
408 
409 #endif
410