1 /* 2 * MIPS internal definitions and helpers 3 * 4 * This work is licensed under the terms of the GNU GPL, version 2 or later. 5 * See the COPYING file in the top-level directory. 6 */ 7 8 #ifndef MIPS_INTERNAL_H 9 #define MIPS_INTERNAL_H 10 11 #include "exec/memattrs.h" 12 #ifdef CONFIG_TCG 13 #include "tcg/tcg-internal.h" 14 #endif 15 16 /* 17 * MMU types, the first four entries have the same layout as the 18 * CP0C0_MT field. 19 */ 20 enum mips_mmu_types { 21 MMU_TYPE_NONE = 0, 22 MMU_TYPE_R4000 = 1, /* Standard TLB */ 23 MMU_TYPE_BAT = 2, /* Block Address Translation */ 24 MMU_TYPE_FMT = 3, /* Fixed Mapping */ 25 MMU_TYPE_DVF = 4, /* Dual VTLB and FTLB */ 26 MMU_TYPE_R3000, 27 MMU_TYPE_R6000, 28 MMU_TYPE_R8000 29 }; 30 31 struct mips_def_t { 32 const char *name; 33 int32_t CP0_PRid; 34 int32_t CP0_Config0; 35 int32_t CP0_Config1; 36 int32_t CP0_Config2; 37 int32_t CP0_Config3; 38 int32_t CP0_Config4; 39 int32_t CP0_Config4_rw_bitmask; 40 int32_t CP0_Config5; 41 int32_t CP0_Config5_rw_bitmask; 42 int32_t CP0_Config6; 43 int32_t CP0_Config6_rw_bitmask; 44 int32_t CP0_Config7; 45 int32_t CP0_Config7_rw_bitmask; 46 target_ulong CP0_LLAddr_rw_bitmask; 47 int CP0_LLAddr_shift; 48 int32_t SYNCI_Step; 49 int32_t CCRes; 50 int32_t CP0_Status_rw_bitmask; 51 int32_t CP0_TCStatus_rw_bitmask; 52 int32_t CP0_SRSCtl; 53 int32_t CP1_fcr0; 54 int32_t CP1_fcr31_rw_bitmask; 55 int32_t CP1_fcr31; 56 int32_t MSAIR; 57 int32_t SEGBITS; 58 int32_t PABITS; 59 int32_t CP0_SRSConf0_rw_bitmask; 60 int32_t CP0_SRSConf0; 61 int32_t CP0_SRSConf1_rw_bitmask; 62 int32_t CP0_SRSConf1; 63 int32_t CP0_SRSConf2_rw_bitmask; 64 int32_t CP0_SRSConf2; 65 int32_t CP0_SRSConf3_rw_bitmask; 66 int32_t CP0_SRSConf3; 67 int32_t CP0_SRSConf4_rw_bitmask; 68 int32_t CP0_SRSConf4; 69 int32_t CP0_PageGrain_rw_bitmask; 70 int32_t CP0_PageGrain; 71 target_ulong CP0_EBaseWG_rw_bitmask; 72 uint64_t insn_flags; 73 enum mips_mmu_types mmu_type; 74 int32_t SAARP; 75 }; 76 77 extern const char regnames[32][3]; 78 extern const char fregnames[32][4]; 79 80 extern const struct mips_def_t mips_defs[]; 81 extern const int mips_defs_number; 82 83 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 84 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 85 86 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) 87 #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) 88 #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) 89 #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) 90 #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) 91 92 #define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL) 93 #define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL) 94 95 #if !defined(CONFIG_USER_ONLY) 96 97 enum { 98 TLBRET_XI = -6, 99 TLBRET_RI = -5, 100 TLBRET_DIRTY = -4, 101 TLBRET_INVALID = -3, 102 TLBRET_NOMATCH = -2, 103 TLBRET_BADADDR = -1, 104 TLBRET_MATCH = 0 105 }; 106 107 int get_physical_address(CPUMIPSState *env, hwaddr *physical, 108 int *prot, target_ulong real_address, 109 MMUAccessType access_type, int mmu_idx); 110 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 111 112 typedef struct r4k_tlb_t r4k_tlb_t; 113 struct r4k_tlb_t { 114 target_ulong VPN; 115 uint32_t PageMask; 116 uint16_t ASID; 117 uint32_t MMID; 118 unsigned int G:1; 119 unsigned int C0:3; 120 unsigned int C1:3; 121 unsigned int V0:1; 122 unsigned int V1:1; 123 unsigned int D0:1; 124 unsigned int D1:1; 125 unsigned int XI0:1; 126 unsigned int XI1:1; 127 unsigned int RI0:1; 128 unsigned int RI1:1; 129 unsigned int EHINV:1; 130 uint64_t PFN[2]; 131 }; 132 133 struct CPUMIPSTLBContext { 134 uint32_t nb_tlb; 135 uint32_t tlb_in_use; 136 int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot, 137 target_ulong address, MMUAccessType access_type); 138 void (*helper_tlbwi)(struct CPUMIPSState *env); 139 void (*helper_tlbwr)(struct CPUMIPSState *env); 140 void (*helper_tlbp)(struct CPUMIPSState *env); 141 void (*helper_tlbr)(struct CPUMIPSState *env); 142 void (*helper_tlbinv)(struct CPUMIPSState *env); 143 void (*helper_tlbinvf)(struct CPUMIPSState *env); 144 union { 145 struct { 146 r4k_tlb_t tlb[MIPS_TLB_MAX]; 147 } r4k; 148 } mmu; 149 }; 150 151 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); 152 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); 153 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); 154 155 extern const VMStateDescription vmstate_mips_cpu; 156 157 #endif /* !CONFIG_USER_ONLY */ 158 159 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) 160 { 161 return (env->CP0_Status & (1 << CP0St_IE)) && 162 !(env->CP0_Status & (1 << CP0St_EXL)) && 163 !(env->CP0_Status & (1 << CP0St_ERL)) && 164 !(env->hflags & MIPS_HFLAG_DM) && 165 /* 166 * Note that the TCStatus IXMT field is initialized to zero, 167 * and only MT capable cores can set it to one. So we don't 168 * need to check for MT capabilities here. 169 */ 170 !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); 171 } 172 173 /* Check if there is pending and not masked out interrupt */ 174 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) 175 { 176 int32_t pending; 177 int32_t status; 178 bool r; 179 180 pending = env->CP0_Cause & CP0Ca_IP_mask; 181 status = env->CP0_Status & CP0Ca_IP_mask; 182 183 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { 184 /* 185 * A MIPS configured with a vectorizing external interrupt controller 186 * will feed a vector into the Cause pending lines. The core treats 187 * the status lines as a vector level, not as individual masks. 188 */ 189 r = pending > status; 190 } else { 191 /* 192 * A MIPS configured with compatibility or VInt (Vectored Interrupts) 193 * treats the pending lines as individual interrupt lines, the status 194 * lines are individual masks. 195 */ 196 r = (pending & status) != 0; 197 } 198 return r; 199 } 200 201 void msa_reset(CPUMIPSState *env); 202 203 /* cp0_timer.c */ 204 uint32_t cpu_mips_get_count(CPUMIPSState *env); 205 void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); 206 void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); 207 void cpu_mips_start_count(CPUMIPSState *env); 208 void cpu_mips_stop_count(CPUMIPSState *env); 209 210 static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) 211 { 212 env->active_tc.PC = value & ~(target_ulong)1; 213 if (value & 1) { 214 env->hflags |= MIPS_HFLAG_M16; 215 } else { 216 env->hflags &= ~(MIPS_HFLAG_M16); 217 } 218 } 219 220 static inline void restore_pamask(CPUMIPSState *env) 221 { 222 if (env->hflags & MIPS_HFLAG_ELPA) { 223 env->PAMask = (1ULL << env->PABITS) - 1; 224 } else { 225 env->PAMask = PAMASK_BASE; 226 } 227 } 228 229 static inline int mips_vpe_active(CPUMIPSState *env) 230 { 231 int active = 1; 232 233 /* Check that the VPE is enabled. */ 234 if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { 235 active = 0; 236 } 237 /* Check that the VPE is activated. */ 238 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { 239 active = 0; 240 } 241 242 /* 243 * Now verify that there are active thread contexts in the VPE. 244 * 245 * This assumes the CPU model will internally reschedule threads 246 * if the active one goes to sleep. If there are no threads available 247 * the active one will be in a sleeping state, and we can turn off 248 * the entire VPE. 249 */ 250 if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { 251 /* TC is not activated. */ 252 active = 0; 253 } 254 if (env->active_tc.CP0_TCHalt & 1) { 255 /* TC is in halt state. */ 256 active = 0; 257 } 258 259 return active; 260 } 261 262 static inline int mips_vp_active(CPUMIPSState *env) 263 { 264 CPUState *other_cs = first_cpu; 265 266 /* Check if the VP disabled other VPs (which means the VP is enabled) */ 267 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { 268 return 1; 269 } 270 271 /* Check if the virtual processor is disabled due to a DVP */ 272 CPU_FOREACH(other_cs) { 273 MIPSCPU *other_cpu = MIPS_CPU(other_cs); 274 if ((&other_cpu->env != env) && 275 ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) { 276 return 0; 277 } 278 } 279 return 1; 280 } 281 282 static inline void compute_hflags(CPUMIPSState *env) 283 { 284 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | 285 MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | 286 MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | 287 MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | 288 MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL); 289 if (env->CP0_Status & (1 << CP0St_ERL)) { 290 env->hflags |= MIPS_HFLAG_ERL; 291 } 292 if (!(env->CP0_Status & (1 << CP0St_EXL)) && 293 !(env->CP0_Status & (1 << CP0St_ERL)) && 294 !(env->hflags & MIPS_HFLAG_DM)) { 295 env->hflags |= (env->CP0_Status >> CP0St_KSU) & 296 MIPS_HFLAG_KSU; 297 } 298 #if defined(TARGET_MIPS64) 299 if ((env->insn_flags & ISA_MIPS3) && 300 (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || 301 (env->CP0_Status & (1 << CP0St_PX)) || 302 (env->CP0_Status & (1 << CP0St_UX)))) { 303 env->hflags |= MIPS_HFLAG_64; 304 } 305 306 if (!(env->insn_flags & ISA_MIPS3)) { 307 env->hflags |= MIPS_HFLAG_AWRAP; 308 } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && 309 !(env->CP0_Status & (1 << CP0St_UX))) { 310 env->hflags |= MIPS_HFLAG_AWRAP; 311 } else if (env->insn_flags & ISA_MIPS_R6) { 312 /* Address wrapping for Supervisor and Kernel is specified in R6 */ 313 if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) && 314 !(env->CP0_Status & (1 << CP0St_SX))) || 315 (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) && 316 !(env->CP0_Status & (1 << CP0St_KX)))) { 317 env->hflags |= MIPS_HFLAG_AWRAP; 318 } 319 } 320 #endif 321 if (((env->CP0_Status & (1 << CP0St_CU0)) && 322 !(env->insn_flags & ISA_MIPS_R6)) || 323 !(env->hflags & MIPS_HFLAG_KSU)) { 324 env->hflags |= MIPS_HFLAG_CP0; 325 } 326 if (env->CP0_Status & (1 << CP0St_CU1)) { 327 env->hflags |= MIPS_HFLAG_FPU; 328 } 329 if (env->CP0_Status & (1 << CP0St_FR)) { 330 env->hflags |= MIPS_HFLAG_F64; 331 } 332 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) && 333 (env->CP0_Config5 & (1 << CP0C5_SBRI))) { 334 env->hflags |= MIPS_HFLAG_SBRI; 335 } 336 if (env->insn_flags & ASE_DSP_R3) { 337 /* 338 * Our cpu supports DSP R3 ASE, so enable 339 * access to DSP R3 resources. 340 */ 341 if (env->CP0_Status & (1 << CP0St_MX)) { 342 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | 343 MIPS_HFLAG_DSP_R3; 344 } 345 } else if (env->insn_flags & ASE_DSP_R2) { 346 /* 347 * Our cpu supports DSP R2 ASE, so enable 348 * access to DSP R2 resources. 349 */ 350 if (env->CP0_Status & (1 << CP0St_MX)) { 351 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2; 352 } 353 354 } else if (env->insn_flags & ASE_DSP) { 355 /* 356 * Our cpu supports DSP ASE, so enable 357 * access to DSP resources. 358 */ 359 if (env->CP0_Status & (1 << CP0St_MX)) { 360 env->hflags |= MIPS_HFLAG_DSP; 361 } 362 363 } 364 if (env->insn_flags & ISA_MIPS_R2) { 365 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { 366 env->hflags |= MIPS_HFLAG_COP1X; 367 } 368 } else if (env->insn_flags & ISA_MIPS_R1) { 369 if (env->hflags & MIPS_HFLAG_64) { 370 env->hflags |= MIPS_HFLAG_COP1X; 371 } 372 } else if (env->insn_flags & ISA_MIPS4) { 373 /* 374 * All supported MIPS IV CPUs use the XX (CU3) to enable 375 * and disable the MIPS IV extensions to the MIPS III ISA. 376 * Some other MIPS IV CPUs ignore the bit, so the check here 377 * would be too restrictive for them. 378 */ 379 if (env->CP0_Status & (1U << CP0St_CU3)) { 380 env->hflags |= MIPS_HFLAG_COP1X; 381 } 382 } 383 if (ase_msa_available(env)) { 384 if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { 385 env->hflags |= MIPS_HFLAG_MSA; 386 } 387 } 388 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { 389 if (env->CP0_Config5 & (1 << CP0C5_FRE)) { 390 env->hflags |= MIPS_HFLAG_FRE; 391 } 392 } 393 if (env->CP0_Config3 & (1 << CP0C3_LPA)) { 394 if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) { 395 env->hflags |= MIPS_HFLAG_ELPA; 396 } 397 } 398 } 399 400 #endif 401