1 #ifndef MIPS_CPU_H 2 #define MIPS_CPU_H 3 4 #include "cpu-qom.h" 5 #include "exec/cpu-defs.h" 6 #include "fpu/softfloat-types.h" 7 #include "mips-defs.h" 8 9 #define TCG_GUEST_DEFAULT_MO (0) 10 11 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; 12 13 /* MSA Context */ 14 #define MSA_WRLEN (128) 15 16 typedef union wr_t wr_t; 17 union wr_t { 18 int8_t b[MSA_WRLEN / 8]; 19 int16_t h[MSA_WRLEN / 16]; 20 int32_t w[MSA_WRLEN / 32]; 21 int64_t d[MSA_WRLEN / 64]; 22 }; 23 24 typedef union fpr_t fpr_t; 25 union fpr_t { 26 float64 fd; /* ieee double precision */ 27 float32 fs[2];/* ieee single precision */ 28 uint64_t d; /* binary double fixed-point */ 29 uint32_t w[2]; /* binary single fixed-point */ 30 /* FPU/MSA register mapping is not tested on big-endian hosts. */ 31 wr_t wr; /* vector data */ 32 }; 33 /* 34 *define FP_ENDIAN_IDX to access the same location 35 * in the fpr_t union regardless of the host endianness 36 */ 37 #if defined(HOST_WORDS_BIGENDIAN) 38 # define FP_ENDIAN_IDX 1 39 #else 40 # define FP_ENDIAN_IDX 0 41 #endif 42 43 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; 44 struct CPUMIPSFPUContext { 45 /* Floating point registers */ 46 fpr_t fpr[32]; 47 float_status fp_status; 48 /* fpu implementation/revision register (fir) */ 49 uint32_t fcr0; 50 #define FCR0_FREP 29 51 #define FCR0_UFRP 28 52 #define FCR0_HAS2008 23 53 #define FCR0_F64 22 54 #define FCR0_L 21 55 #define FCR0_W 20 56 #define FCR0_3D 19 57 #define FCR0_PS 18 58 #define FCR0_D 17 59 #define FCR0_S 16 60 #define FCR0_PRID 8 61 #define FCR0_REV 0 62 /* fcsr */ 63 uint32_t fcr31_rw_bitmask; 64 uint32_t fcr31; 65 #define FCR31_FS 24 66 #define FCR31_ABS2008 19 67 #define FCR31_NAN2008 18 68 #define SET_FP_COND(num, env) do { ((env).fcr31) |= \ 69 ((num) ? (1 << ((num) + 24)) : \ 70 (1 << 23)); \ 71 } while (0) 72 #define CLEAR_FP_COND(num, env) do { ((env).fcr31) &= \ 73 ~((num) ? (1 << ((num) + 24)) : \ 74 (1 << 23)); \ 75 } while (0) 76 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \ 77 (((env).fcr31 >> 23) & 0x1)) 78 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) 79 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 80 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) 81 #define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \ 82 ((v & 0x3f) << 12); \ 83 } while (0) 84 #define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \ 85 ((v & 0x1f) << 7); \ 86 } while (0) 87 #define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 2)) | \ 88 ((v & 0x1f) << 2); \ 89 } while (0) 90 #define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 2); } while (0) 91 #define FP_INEXACT 1 92 #define FP_UNDERFLOW 2 93 #define FP_OVERFLOW 4 94 #define FP_DIV0 8 95 #define FP_INVALID 16 96 #define FP_UNIMPLEMENTED 32 97 }; 98 99 #define TARGET_INSN_START_EXTRA_WORDS 2 100 101 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; 102 struct CPUMIPSMVPContext { 103 int32_t CP0_MVPControl; 104 #define CP0MVPCo_CPA 3 105 #define CP0MVPCo_STLB 2 106 #define CP0MVPCo_VPC 1 107 #define CP0MVPCo_EVP 0 108 int32_t CP0_MVPConf0; 109 #define CP0MVPC0_M 31 110 #define CP0MVPC0_TLBS 29 111 #define CP0MVPC0_GS 28 112 #define CP0MVPC0_PCP 27 113 #define CP0MVPC0_PTLBE 16 114 #define CP0MVPC0_TCA 15 115 #define CP0MVPC0_PVPE 10 116 #define CP0MVPC0_PTC 0 117 int32_t CP0_MVPConf1; 118 #define CP0MVPC1_CIM 31 119 #define CP0MVPC1_CIF 30 120 #define CP0MVPC1_PCX 20 121 #define CP0MVPC1_PCP2 10 122 #define CP0MVPC1_PCP1 0 123 }; 124 125 typedef struct mips_def_t mips_def_t; 126 127 #define MIPS_SHADOW_SET_MAX 16 128 #define MIPS_TC_MAX 5 129 #define MIPS_FPU_MAX 1 130 #define MIPS_DSP_ACC 4 131 #define MIPS_KSCRATCH_NUM 6 132 #define MIPS_MAAR_MAX 16 /* Must be an even number. */ 133 134 135 /* 136 * Summary of CP0 registers 137 * ======================== 138 * 139 * 140 * Register 0 Register 1 Register 2 Register 3 141 * ---------- ---------- ---------- ---------- 142 * 143 * 0 Index Random EntryLo0 EntryLo1 144 * 1 MVPControl VPEControl TCStatus GlobalNumber 145 * 2 MVPConf0 VPEConf0 TCBind 146 * 3 MVPConf1 VPEConf1 TCRestart 147 * 4 VPControl YQMask TCHalt 148 * 5 VPESchedule TCContext 149 * 6 VPEScheFBack TCSchedule 150 * 7 VPEOpt TCScheFBack TCOpt 151 * 152 * 153 * Register 4 Register 5 Register 6 Register 7 154 * ---------- ---------- ---------- ---------- 155 * 156 * 0 Context PageMask Wired HWREna 157 * 1 ContextConfig PageGrain SRSConf0 158 * 2 UserLocal SegCtl0 SRSConf1 159 * 3 XContextConfig SegCtl1 SRSConf2 160 * 4 DebugContextID SegCtl2 SRSConf3 161 * 5 MemoryMapID PWBase SRSConf4 162 * 6 PWField PWCtl 163 * 7 PWSize 164 * 165 * 166 * Register 8 Register 9 Register 10 Register 11 167 * ---------- ---------- ----------- ----------- 168 * 169 * 0 BadVAddr Count EntryHi Compare 170 * 1 BadInstr 171 * 2 BadInstrP 172 * 3 BadInstrX 173 * 4 GuestCtl1 GuestCtl0Ext 174 * 5 GuestCtl2 175 * 6 SAARI GuestCtl3 176 * 7 SAAR 177 * 178 * 179 * Register 12 Register 13 Register 14 Register 15 180 * ----------- ----------- ----------- ----------- 181 * 182 * 0 Status Cause EPC PRId 183 * 1 IntCtl EBase 184 * 2 SRSCtl NestedEPC CDMMBase 185 * 3 SRSMap CMGCRBase 186 * 4 View_IPL View_RIPL BEVVA 187 * 5 SRSMap2 NestedExc 188 * 6 GuestCtl0 189 * 7 GTOffset 190 * 191 * 192 * Register 16 Register 17 Register 18 Register 19 193 * ----------- ----------- ----------- ----------- 194 * 195 * 0 Config LLAddr WatchLo WatchHi 196 * 1 Config1 MAAR WatchLo WatchHi 197 * 2 Config2 MAARI WatchLo WatchHi 198 * 3 Config3 WatchLo WatchHi 199 * 4 Config4 WatchLo WatchHi 200 * 5 Config5 WatchLo WatchHi 201 * 6 WatchLo WatchHi 202 * 7 WatchLo WatchHi 203 * 204 * 205 * Register 20 Register 21 Register 22 Register 23 206 * ----------- ----------- ----------- ----------- 207 * 208 * 0 XContext Debug 209 * 1 TraceControl 210 * 2 TraceControl2 211 * 3 UserTraceData1 212 * 4 TraceIBPC 213 * 5 TraceDBPC 214 * 6 Debug2 215 * 7 216 * 217 * 218 * Register 24 Register 25 Register 26 Register 27 219 * ----------- ----------- ----------- ----------- 220 * 221 * 0 DEPC PerfCnt ErrCtl CacheErr 222 * 1 PerfCnt 223 * 2 TraceControl3 PerfCnt 224 * 3 UserTraceData2 PerfCnt 225 * 4 PerfCnt 226 * 5 PerfCnt 227 * 6 PerfCnt 228 * 7 PerfCnt 229 * 230 * 231 * Register 28 Register 29 Register 30 Register 31 232 * ----------- ----------- ----------- ----------- 233 * 234 * 0 DataLo DataHi ErrorEPC DESAVE 235 * 1 TagLo TagHi 236 * 2 DataLo DataHi KScratch<n> 237 * 3 TagLo TagHi KScratch<n> 238 * 4 DataLo DataHi KScratch<n> 239 * 5 TagLo TagHi KScratch<n> 240 * 6 DataLo DataHi KScratch<n> 241 * 7 TagLo TagHi KScratch<n> 242 * 243 */ 244 #define CP0_REGISTER_00 0 245 #define CP0_REGISTER_01 1 246 #define CP0_REGISTER_02 2 247 #define CP0_REGISTER_03 3 248 #define CP0_REGISTER_04 4 249 #define CP0_REGISTER_05 5 250 #define CP0_REGISTER_06 6 251 #define CP0_REGISTER_07 7 252 #define CP0_REGISTER_08 8 253 #define CP0_REGISTER_09 9 254 #define CP0_REGISTER_10 10 255 #define CP0_REGISTER_11 11 256 #define CP0_REGISTER_12 12 257 #define CP0_REGISTER_13 13 258 #define CP0_REGISTER_14 14 259 #define CP0_REGISTER_15 15 260 #define CP0_REGISTER_16 16 261 #define CP0_REGISTER_17 17 262 #define CP0_REGISTER_18 18 263 #define CP0_REGISTER_19 19 264 #define CP0_REGISTER_20 20 265 #define CP0_REGISTER_21 21 266 #define CP0_REGISTER_22 22 267 #define CP0_REGISTER_23 23 268 #define CP0_REGISTER_24 24 269 #define CP0_REGISTER_25 25 270 #define CP0_REGISTER_26 26 271 #define CP0_REGISTER_27 27 272 #define CP0_REGISTER_28 28 273 #define CP0_REGISTER_29 29 274 #define CP0_REGISTER_30 30 275 #define CP0_REGISTER_31 31 276 277 278 /* CP0 Register 00 */ 279 #define CP0_REG00__INDEX 0 280 #define CP0_REG00__VPCONTROL 4 281 /* CP0 Register 01 */ 282 /* CP0 Register 02 */ 283 #define CP0_REG02__ENTRYLO0 0 284 /* CP0 Register 03 */ 285 #define CP0_REG03__ENTRYLO1 0 286 #define CP0_REG03__GLOBALNUM 1 287 /* CP0 Register 04 */ 288 #define CP0_REG04__CONTEXT 0 289 #define CP0_REG04__USERLOCAL 2 290 #define CP0_REG04__DBGCONTEXTID 4 291 #define CP0_REG00__MMID 5 292 /* CP0 Register 05 */ 293 #define CP0_REG05__PAGEMASK 0 294 #define CP0_REG05__PAGEGRAIN 1 295 /* CP0 Register 06 */ 296 #define CP0_REG06__WIRED 0 297 /* CP0 Register 07 */ 298 #define CP0_REG07__HWRENA 0 299 /* CP0 Register 08 */ 300 #define CP0_REG08__BADVADDR 0 301 #define CP0_REG08__BADINSTR 1 302 #define CP0_REG08__BADINSTRP 2 303 /* CP0 Register 09 */ 304 #define CP0_REG09__COUNT 0 305 #define CP0_REG09__SAARI 6 306 #define CP0_REG09__SAAR 7 307 /* CP0 Register 10 */ 308 #define CP0_REG10__ENTRYHI 0 309 #define CP0_REG10__GUESTCTL1 4 310 #define CP0_REG10__GUESTCTL2 5 311 /* CP0 Register 11 */ 312 #define CP0_REG11__COMPARE 0 313 #define CP0_REG11__GUESTCTL0EXT 4 314 /* CP0 Register 12 */ 315 #define CP0_REG12__STATUS 0 316 #define CP0_REG12__INTCTL 1 317 #define CP0_REG12__SRSCTL 2 318 #define CP0_REG12__GUESTCTL0 6 319 #define CP0_REG12__GTOFFSET 7 320 /* CP0 Register 13 */ 321 #define CP0_REG13__CAUSE 0 322 /* CP0 Register 14 */ 323 #define CP0_REG14__EPC 0 324 /* CP0 Register 15 */ 325 #define CP0_REG15__PRID 0 326 #define CP0_REG15__EBASE 1 327 #define CP0_REG15__CDMMBASE 2 328 #define CP0_REG15__CMGCRBASE 3 329 /* CP0 Register 16 */ 330 #define CP0_REG16__CONFIG 0 331 #define CP0_REG16__CONFIG1 1 332 #define CP0_REG16__CONFIG2 2 333 #define CP0_REG16__CONFIG3 3 334 #define CP0_REG16__CONFIG4 4 335 #define CP0_REG16__CONFIG5 5 336 #define CP0_REG00__CONFIG7 7 337 /* CP0 Register 17 */ 338 #define CP0_REG17__LLADDR 0 339 #define CP0_REG17__MAAR 1 340 #define CP0_REG17__MAARI 2 341 /* CP0 Register 18 */ 342 #define CP0_REG18__WATCHLO0 0 343 #define CP0_REG18__WATCHLO1 1 344 #define CP0_REG18__WATCHLO2 2 345 #define CP0_REG18__WATCHLO3 3 346 /* CP0 Register 19 */ 347 #define CP0_REG19__WATCHHI0 0 348 #define CP0_REG19__WATCHHI1 1 349 #define CP0_REG19__WATCHHI2 2 350 #define CP0_REG19__WATCHHI3 3 351 /* CP0 Register 20 */ 352 #define CP0_REG20__XCONTEXT 0 353 /* CP0 Register 21 */ 354 /* CP0 Register 22 */ 355 /* CP0 Register 23 */ 356 #define CP0_REG23__DEBUG 0 357 /* CP0 Register 24 */ 358 #define CP0_REG24__DEPC 0 359 /* CP0 Register 25 */ 360 #define CP0_REG25__PERFCTL0 0 361 #define CP0_REG25__PERFCNT0 1 362 #define CP0_REG25__PERFCTL1 2 363 #define CP0_REG25__PERFCNT1 3 364 #define CP0_REG25__PERFCTL2 4 365 #define CP0_REG25__PERFCNT2 5 366 #define CP0_REG25__PERFCTL3 6 367 #define CP0_REG25__PERFCNT3 7 368 /* CP0 Register 26 */ 369 #define CP0_REG00__ERRCTL 0 370 /* CP0 Register 27 */ 371 #define CP0_REG27__CACHERR 0 372 /* CP0 Register 28 */ 373 #define CP0_REG28__ITAGLO 0 374 #define CP0_REG28__IDATALO 1 375 #define CP0_REG28__DTAGLO 2 376 #define CP0_REG28__DDATALO 3 377 /* CP0 Register 29 */ 378 #define CP0_REG29__IDATAHI 1 379 #define CP0_REG29__DDATAHI 3 380 /* CP0 Register 30 */ 381 #define CP0_REG30__ERROREPC 0 382 /* CP0 Register 31 */ 383 #define CP0_REG31__DESAVE 0 384 #define CP0_REG31__KSCRATCH1 2 385 #define CP0_REG31__KSCRATCH2 3 386 #define CP0_REG31__KSCRATCH3 4 387 #define CP0_REG31__KSCRATCH4 5 388 #define CP0_REG31__KSCRATCH5 6 389 #define CP0_REG31__KSCRATCH6 7 390 391 392 typedef struct TCState TCState; 393 struct TCState { 394 target_ulong gpr[32]; 395 target_ulong PC; 396 target_ulong HI[MIPS_DSP_ACC]; 397 target_ulong LO[MIPS_DSP_ACC]; 398 target_ulong ACX[MIPS_DSP_ACC]; 399 target_ulong DSPControl; 400 int32_t CP0_TCStatus; 401 #define CP0TCSt_TCU3 31 402 #define CP0TCSt_TCU2 30 403 #define CP0TCSt_TCU1 29 404 #define CP0TCSt_TCU0 28 405 #define CP0TCSt_TMX 27 406 #define CP0TCSt_RNST 23 407 #define CP0TCSt_TDS 21 408 #define CP0TCSt_DT 20 409 #define CP0TCSt_DA 15 410 #define CP0TCSt_A 13 411 #define CP0TCSt_TKSU 11 412 #define CP0TCSt_IXMT 10 413 #define CP0TCSt_TASID 0 414 int32_t CP0_TCBind; 415 #define CP0TCBd_CurTC 21 416 #define CP0TCBd_TBE 17 417 #define CP0TCBd_CurVPE 0 418 target_ulong CP0_TCHalt; 419 target_ulong CP0_TCContext; 420 target_ulong CP0_TCSchedule; 421 target_ulong CP0_TCScheFBack; 422 int32_t CP0_Debug_tcstatus; 423 target_ulong CP0_UserLocal; 424 425 int32_t msacsr; 426 427 #define MSACSR_FS 24 428 #define MSACSR_FS_MASK (1 << MSACSR_FS) 429 #define MSACSR_NX 18 430 #define MSACSR_NX_MASK (1 << MSACSR_NX) 431 #define MSACSR_CEF 2 432 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF) 433 #define MSACSR_RM 0 434 #define MSACSR_RM_MASK (0x3 << MSACSR_RM) 435 #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \ 436 MSACSR_FS_MASK) 437 438 float_status msa_fp_status; 439 440 /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */ 441 uint64_t mmr[32]; 442 443 #define NUMBER_OF_MXU_REGISTERS 16 444 target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; 445 target_ulong mxu_cr; 446 #define MXU_CR_LC 31 447 #define MXU_CR_RC 30 448 #define MXU_CR_BIAS 2 449 #define MXU_CR_RD_EN 1 450 #define MXU_CR_MXU_EN 0 451 452 }; 453 454 struct MIPSITUState; 455 typedef struct CPUMIPSState CPUMIPSState; 456 struct CPUMIPSState { 457 TCState active_tc; 458 CPUMIPSFPUContext active_fpu; 459 460 uint32_t current_tc; 461 uint32_t current_fpu; 462 463 uint32_t SEGBITS; 464 uint32_t PABITS; 465 #if defined(TARGET_MIPS64) 466 # define PABITS_BASE 36 467 #else 468 # define PABITS_BASE 32 469 #endif 470 target_ulong SEGMask; 471 uint64_t PAMask; 472 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1) 473 474 int32_t msair; 475 #define MSAIR_ProcID 8 476 #define MSAIR_Rev 0 477 478 /* 479 * CP0 Register 0 480 */ 481 int32_t CP0_Index; 482 /* CP0_MVP* are per MVP registers. */ 483 int32_t CP0_VPControl; 484 #define CP0VPCtl_DIS 0 485 /* 486 * CP0 Register 1 487 */ 488 int32_t CP0_Random; 489 int32_t CP0_VPEControl; 490 #define CP0VPECo_YSI 21 491 #define CP0VPECo_GSI 20 492 #define CP0VPECo_EXCPT 16 493 #define CP0VPECo_TE 15 494 #define CP0VPECo_TargTC 0 495 int32_t CP0_VPEConf0; 496 #define CP0VPEC0_M 31 497 #define CP0VPEC0_XTC 21 498 #define CP0VPEC0_TCS 19 499 #define CP0VPEC0_SCS 18 500 #define CP0VPEC0_DSC 17 501 #define CP0VPEC0_ICS 16 502 #define CP0VPEC0_MVP 1 503 #define CP0VPEC0_VPA 0 504 int32_t CP0_VPEConf1; 505 #define CP0VPEC1_NCX 20 506 #define CP0VPEC1_NCP2 10 507 #define CP0VPEC1_NCP1 0 508 target_ulong CP0_YQMask; 509 target_ulong CP0_VPESchedule; 510 target_ulong CP0_VPEScheFBack; 511 int32_t CP0_VPEOpt; 512 #define CP0VPEOpt_IWX7 15 513 #define CP0VPEOpt_IWX6 14 514 #define CP0VPEOpt_IWX5 13 515 #define CP0VPEOpt_IWX4 12 516 #define CP0VPEOpt_IWX3 11 517 #define CP0VPEOpt_IWX2 10 518 #define CP0VPEOpt_IWX1 9 519 #define CP0VPEOpt_IWX0 8 520 #define CP0VPEOpt_DWX7 7 521 #define CP0VPEOpt_DWX6 6 522 #define CP0VPEOpt_DWX5 5 523 #define CP0VPEOpt_DWX4 4 524 #define CP0VPEOpt_DWX3 3 525 #define CP0VPEOpt_DWX2 2 526 #define CP0VPEOpt_DWX1 1 527 #define CP0VPEOpt_DWX0 0 528 /* 529 * CP0 Register 2 530 */ 531 uint64_t CP0_EntryLo0; 532 /* 533 * CP0 Register 3 534 */ 535 uint64_t CP0_EntryLo1; 536 #if defined(TARGET_MIPS64) 537 # define CP0EnLo_RI 63 538 # define CP0EnLo_XI 62 539 #else 540 # define CP0EnLo_RI 31 541 # define CP0EnLo_XI 30 542 #endif 543 int32_t CP0_GlobalNumber; 544 #define CP0GN_VPId 0 545 /* 546 * CP0 Register 4 547 */ 548 target_ulong CP0_Context; 549 target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; 550 int32_t CP0_MemoryMapID; 551 /* 552 * CP0 Register 5 553 */ 554 int32_t CP0_PageMask; 555 int32_t CP0_PageGrain_rw_bitmask; 556 int32_t CP0_PageGrain; 557 #define CP0PG_RIE 31 558 #define CP0PG_XIE 30 559 #define CP0PG_ELPA 29 560 #define CP0PG_IEC 27 561 target_ulong CP0_SegCtl0; 562 target_ulong CP0_SegCtl1; 563 target_ulong CP0_SegCtl2; 564 #define CP0SC_PA 9 565 #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA) 566 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA) 567 #define CP0SC_AM 4 568 #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM) 569 #define CP0SC_AM_UK 0ULL 570 #define CP0SC_AM_MK 1ULL 571 #define CP0SC_AM_MSK 2ULL 572 #define CP0SC_AM_MUSK 3ULL 573 #define CP0SC_AM_MUSUK 4ULL 574 #define CP0SC_AM_USK 5ULL 575 #define CP0SC_AM_UUSK 7ULL 576 #define CP0SC_EU 3 577 #define CP0SC_EU_MASK (1ULL << CP0SC_EU) 578 #define CP0SC_C 0 579 #define CP0SC_C_MASK (0x7ULL << CP0SC_C) 580 #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ 581 CP0SC_PA_MASK) 582 #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ 583 CP0SC_PA_1GMASK) 584 #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16)) 585 #define CP0SC1_XAM 59 586 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM) 587 #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK) 588 #define CP0SC2_XR 56 589 #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR) 590 #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK) 591 target_ulong CP0_PWBase; 592 target_ulong CP0_PWField; 593 #if defined(TARGET_MIPS64) 594 #define CP0PF_BDI 32 /* 37..32 */ 595 #define CP0PF_GDI 24 /* 29..24 */ 596 #define CP0PF_UDI 18 /* 23..18 */ 597 #define CP0PF_MDI 12 /* 17..12 */ 598 #define CP0PF_PTI 6 /* 11..6 */ 599 #define CP0PF_PTEI 0 /* 5..0 */ 600 #else 601 #define CP0PF_GDW 24 /* 29..24 */ 602 #define CP0PF_UDW 18 /* 23..18 */ 603 #define CP0PF_MDW 12 /* 17..12 */ 604 #define CP0PF_PTW 6 /* 11..6 */ 605 #define CP0PF_PTEW 0 /* 5..0 */ 606 #endif 607 target_ulong CP0_PWSize; 608 #if defined(TARGET_MIPS64) 609 #define CP0PS_BDW 32 /* 37..32 */ 610 #endif 611 #define CP0PS_PS 30 612 #define CP0PS_GDW 24 /* 29..24 */ 613 #define CP0PS_UDW 18 /* 23..18 */ 614 #define CP0PS_MDW 12 /* 17..12 */ 615 #define CP0PS_PTW 6 /* 11..6 */ 616 #define CP0PS_PTEW 0 /* 5..0 */ 617 /* 618 * CP0 Register 6 619 */ 620 int32_t CP0_Wired; 621 int32_t CP0_PWCtl; 622 #define CP0PC_PWEN 31 623 #if defined(TARGET_MIPS64) 624 #define CP0PC_PWDIREXT 30 625 #define CP0PC_XK 28 626 #define CP0PC_XS 27 627 #define CP0PC_XU 26 628 #endif 629 #define CP0PC_DPH 7 630 #define CP0PC_HUGEPG 6 631 #define CP0PC_PSN 0 /* 5..0 */ 632 int32_t CP0_SRSConf0_rw_bitmask; 633 int32_t CP0_SRSConf0; 634 #define CP0SRSC0_M 31 635 #define CP0SRSC0_SRS3 20 636 #define CP0SRSC0_SRS2 10 637 #define CP0SRSC0_SRS1 0 638 int32_t CP0_SRSConf1_rw_bitmask; 639 int32_t CP0_SRSConf1; 640 #define CP0SRSC1_M 31 641 #define CP0SRSC1_SRS6 20 642 #define CP0SRSC1_SRS5 10 643 #define CP0SRSC1_SRS4 0 644 int32_t CP0_SRSConf2_rw_bitmask; 645 int32_t CP0_SRSConf2; 646 #define CP0SRSC2_M 31 647 #define CP0SRSC2_SRS9 20 648 #define CP0SRSC2_SRS8 10 649 #define CP0SRSC2_SRS7 0 650 int32_t CP0_SRSConf3_rw_bitmask; 651 int32_t CP0_SRSConf3; 652 #define CP0SRSC3_M 31 653 #define CP0SRSC3_SRS12 20 654 #define CP0SRSC3_SRS11 10 655 #define CP0SRSC3_SRS10 0 656 int32_t CP0_SRSConf4_rw_bitmask; 657 int32_t CP0_SRSConf4; 658 #define CP0SRSC4_SRS15 20 659 #define CP0SRSC4_SRS14 10 660 #define CP0SRSC4_SRS13 0 661 /* 662 * CP0 Register 7 663 */ 664 int32_t CP0_HWREna; 665 /* 666 * CP0 Register 8 667 */ 668 target_ulong CP0_BadVAddr; 669 uint32_t CP0_BadInstr; 670 uint32_t CP0_BadInstrP; 671 uint32_t CP0_BadInstrX; 672 /* 673 * CP0 Register 9 674 */ 675 int32_t CP0_Count; 676 uint32_t CP0_SAARI; 677 #define CP0SAARI_TARGET 0 /* 5..0 */ 678 uint64_t CP0_SAAR[2]; 679 #define CP0SAAR_BASE 12 /* 43..12 */ 680 #define CP0SAAR_SIZE 1 /* 5..1 */ 681 #define CP0SAAR_EN 0 682 /* 683 * CP0 Register 10 684 */ 685 target_ulong CP0_EntryHi; 686 #define CP0EnHi_EHINV 10 687 target_ulong CP0_EntryHi_ASID_mask; 688 /* 689 * CP0 Register 11 690 */ 691 int32_t CP0_Compare; 692 /* 693 * CP0 Register 12 694 */ 695 int32_t CP0_Status; 696 #define CP0St_CU3 31 697 #define CP0St_CU2 30 698 #define CP0St_CU1 29 699 #define CP0St_CU0 28 700 #define CP0St_RP 27 701 #define CP0St_FR 26 702 #define CP0St_RE 25 703 #define CP0St_MX 24 704 #define CP0St_PX 23 705 #define CP0St_BEV 22 706 #define CP0St_TS 21 707 #define CP0St_SR 20 708 #define CP0St_NMI 19 709 #define CP0St_IM 8 710 #define CP0St_KX 7 711 #define CP0St_SX 6 712 #define CP0St_UX 5 713 #define CP0St_KSU 3 714 #define CP0St_ERL 2 715 #define CP0St_EXL 1 716 #define CP0St_IE 0 717 int32_t CP0_IntCtl; 718 #define CP0IntCtl_IPTI 29 719 #define CP0IntCtl_IPPCI 26 720 #define CP0IntCtl_VS 5 721 int32_t CP0_SRSCtl; 722 #define CP0SRSCtl_HSS 26 723 #define CP0SRSCtl_EICSS 18 724 #define CP0SRSCtl_ESS 12 725 #define CP0SRSCtl_PSS 6 726 #define CP0SRSCtl_CSS 0 727 int32_t CP0_SRSMap; 728 #define CP0SRSMap_SSV7 28 729 #define CP0SRSMap_SSV6 24 730 #define CP0SRSMap_SSV5 20 731 #define CP0SRSMap_SSV4 16 732 #define CP0SRSMap_SSV3 12 733 #define CP0SRSMap_SSV2 8 734 #define CP0SRSMap_SSV1 4 735 #define CP0SRSMap_SSV0 0 736 /* 737 * CP0 Register 13 738 */ 739 int32_t CP0_Cause; 740 #define CP0Ca_BD 31 741 #define CP0Ca_TI 30 742 #define CP0Ca_CE 28 743 #define CP0Ca_DC 27 744 #define CP0Ca_PCI 26 745 #define CP0Ca_IV 23 746 #define CP0Ca_WP 22 747 #define CP0Ca_IP 8 748 #define CP0Ca_IP_mask 0x0000FF00 749 #define CP0Ca_EC 2 750 /* 751 * CP0 Register 14 752 */ 753 target_ulong CP0_EPC; 754 /* 755 * CP0 Register 15 756 */ 757 int32_t CP0_PRid; 758 target_ulong CP0_EBase; 759 target_ulong CP0_EBaseWG_rw_bitmask; 760 #define CP0EBase_WG 11 761 target_ulong CP0_CMGCRBase; 762 /* 763 * CP0 Register 16 764 */ 765 int32_t CP0_Config0; 766 #define CP0C0_M 31 767 #define CP0C0_K23 28 /* 30..28 */ 768 #define CP0C0_KU 25 /* 27..25 */ 769 #define CP0C0_MDU 20 770 #define CP0C0_MM 18 771 #define CP0C0_BM 16 772 #define CP0C0_Impl 16 /* 24..16 */ 773 #define CP0C0_BE 15 774 #define CP0C0_AT 13 /* 14..13 */ 775 #define CP0C0_AR 10 /* 12..10 */ 776 #define CP0C0_MT 7 /* 9..7 */ 777 #define CP0C0_VI 3 778 #define CP0C0_K0 0 /* 2..0 */ 779 int32_t CP0_Config1; 780 #define CP0C1_M 31 781 #define CP0C1_MMU 25 /* 30..25 */ 782 #define CP0C1_IS 22 /* 24..22 */ 783 #define CP0C1_IL 19 /* 21..19 */ 784 #define CP0C1_IA 16 /* 18..16 */ 785 #define CP0C1_DS 13 /* 15..13 */ 786 #define CP0C1_DL 10 /* 12..10 */ 787 #define CP0C1_DA 7 /* 9..7 */ 788 #define CP0C1_C2 6 789 #define CP0C1_MD 5 790 #define CP0C1_PC 4 791 #define CP0C1_WR 3 792 #define CP0C1_CA 2 793 #define CP0C1_EP 1 794 #define CP0C1_FP 0 795 int32_t CP0_Config2; 796 #define CP0C2_M 31 797 #define CP0C2_TU 28 /* 30..28 */ 798 #define CP0C2_TS 24 /* 27..24 */ 799 #define CP0C2_TL 20 /* 23..20 */ 800 #define CP0C2_TA 16 /* 19..16 */ 801 #define CP0C2_SU 12 /* 15..12 */ 802 #define CP0C2_SS 8 /* 11..8 */ 803 #define CP0C2_SL 4 /* 7..4 */ 804 #define CP0C2_SA 0 /* 3..0 */ 805 int32_t CP0_Config3; 806 #define CP0C3_M 31 807 #define CP0C3_BPG 30 808 #define CP0C3_CMGCR 29 809 #define CP0C3_MSAP 28 810 #define CP0C3_BP 27 811 #define CP0C3_BI 26 812 #define CP0C3_SC 25 813 #define CP0C3_PW 24 814 #define CP0C3_VZ 23 815 #define CP0C3_IPLV 21 /* 22..21 */ 816 #define CP0C3_MMAR 18 /* 20..18 */ 817 #define CP0C3_MCU 17 818 #define CP0C3_ISA_ON_EXC 16 819 #define CP0C3_ISA 14 /* 15..14 */ 820 #define CP0C3_ULRI 13 821 #define CP0C3_RXI 12 822 #define CP0C3_DSP2P 11 823 #define CP0C3_DSPP 10 824 #define CP0C3_CTXTC 9 825 #define CP0C3_ITL 8 826 #define CP0C3_LPA 7 827 #define CP0C3_VEIC 6 828 #define CP0C3_VInt 5 829 #define CP0C3_SP 4 830 #define CP0C3_CDMM 3 831 #define CP0C3_MT 2 832 #define CP0C3_SM 1 833 #define CP0C3_TL 0 834 int32_t CP0_Config4; 835 int32_t CP0_Config4_rw_bitmask; 836 #define CP0C4_M 31 837 #define CP0C4_IE 29 /* 30..29 */ 838 #define CP0C4_AE 28 839 #define CP0C4_VTLBSizeExt 24 /* 27..24 */ 840 #define CP0C4_KScrExist 16 841 #define CP0C4_MMUExtDef 14 842 #define CP0C4_FTLBPageSize 8 /* 12..8 */ 843 /* bit layout if MMUExtDef=1 */ 844 #define CP0C4_MMUSizeExt 0 /* 7..0 */ 845 /* bit layout if MMUExtDef=2 */ 846 #define CP0C4_FTLBWays 4 /* 7..4 */ 847 #define CP0C4_FTLBSets 0 /* 3..0 */ 848 int32_t CP0_Config5; 849 int32_t CP0_Config5_rw_bitmask; 850 #define CP0C5_M 31 851 #define CP0C5_K 30 852 #define CP0C5_CV 29 853 #define CP0C5_EVA 28 854 #define CP0C5_MSAEn 27 855 #define CP0C5_PMJ 23 /* 25..23 */ 856 #define CP0C5_WR2 22 857 #define CP0C5_NMS 21 858 #define CP0C5_ULS 20 859 #define CP0C5_XPA 19 860 #define CP0C5_CRCP 18 861 #define CP0C5_MI 17 862 #define CP0C5_GI 15 /* 16..15 */ 863 #define CP0C5_CA2 14 864 #define CP0C5_XNP 13 865 #define CP0C5_DEC 11 866 #define CP0C5_L2C 10 867 #define CP0C5_UFE 9 868 #define CP0C5_FRE 8 869 #define CP0C5_VP 7 870 #define CP0C5_SBRI 6 871 #define CP0C5_MVH 5 872 #define CP0C5_LLB 4 873 #define CP0C5_MRP 3 874 #define CP0C5_UFR 2 875 #define CP0C5_NFExists 0 876 int32_t CP0_Config6; 877 int32_t CP0_Config7; 878 uint64_t CP0_LLAddr; 879 uint64_t CP0_MAAR[MIPS_MAAR_MAX]; 880 int32_t CP0_MAARI; 881 /* XXX: Maybe make LLAddr per-TC? */ 882 /* 883 * CP0 Register 17 884 */ 885 target_ulong lladdr; /* LL virtual address compared against SC */ 886 target_ulong llval; 887 uint64_t llval_wp; 888 uint32_t llnewval_wp; 889 uint64_t CP0_LLAddr_rw_bitmask; 890 int CP0_LLAddr_shift; 891 /* 892 * CP0 Register 18 893 */ 894 target_ulong CP0_WatchLo[8]; 895 /* 896 * CP0 Register 19 897 */ 898 int32_t CP0_WatchHi[8]; 899 #define CP0WH_ASID 16 900 /* 901 * CP0 Register 20 902 */ 903 target_ulong CP0_XContext; 904 int32_t CP0_Framemask; 905 /* 906 * CP0 Register 23 907 */ 908 int32_t CP0_Debug; 909 #define CP0DB_DBD 31 910 #define CP0DB_DM 30 911 #define CP0DB_LSNM 28 912 #define CP0DB_Doze 27 913 #define CP0DB_Halt 26 914 #define CP0DB_CNT 25 915 #define CP0DB_IBEP 24 916 #define CP0DB_DBEP 21 917 #define CP0DB_IEXI 20 918 #define CP0DB_VER 15 919 #define CP0DB_DEC 10 920 #define CP0DB_SSt 8 921 #define CP0DB_DINT 5 922 #define CP0DB_DIB 4 923 #define CP0DB_DDBS 3 924 #define CP0DB_DDBL 2 925 #define CP0DB_DBp 1 926 #define CP0DB_DSS 0 927 /* 928 * CP0 Register 24 929 */ 930 target_ulong CP0_DEPC; 931 /* 932 * CP0 Register 25 933 */ 934 int32_t CP0_Performance0; 935 /* 936 * CP0 Register 26 937 */ 938 int32_t CP0_ErrCtl; 939 #define CP0EC_WST 29 940 #define CP0EC_SPR 28 941 #define CP0EC_ITC 26 942 /* 943 * CP0 Register 28 944 */ 945 uint64_t CP0_TagLo; 946 int32_t CP0_DataLo; 947 /* 948 * CP0 Register 29 949 */ 950 int32_t CP0_TagHi; 951 int32_t CP0_DataHi; 952 /* 953 * CP0 Register 30 954 */ 955 target_ulong CP0_ErrorEPC; 956 /* 957 * CP0 Register 31 958 */ 959 int32_t CP0_DESAVE; 960 961 /* We waste some space so we can handle shadow registers like TCs. */ 962 TCState tcs[MIPS_SHADOW_SET_MAX]; 963 CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; 964 /* QEMU */ 965 int error_code; 966 #define EXCP_TLB_NOMATCH 0x1 967 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ 968 uint32_t hflags; /* CPU State */ 969 /* TMASK defines different execution modes */ 970 #define MIPS_HFLAG_TMASK 0x1F5807FF 971 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ 972 /* 973 * The KSU flags must be the lowest bits in hflags. The flag order 974 * must be the same as defined for CP0 Status. This allows to use 975 * the bits as the value of mmu_idx. 976 */ 977 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ 978 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ 979 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ 980 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ 981 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ 982 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ 983 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ 984 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ 985 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ 986 /* 987 * True if the MIPS IV COP1X instructions can be used. This also 988 * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S 989 * and RSQRT.D. 990 */ 991 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ 992 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ 993 #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ 994 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ 995 #define MIPS_HFLAG_M16_SHIFT 10 996 /* 997 * If translation is interrupted between the branch instruction and 998 * the delay slot, record what type of branch it is so that we can 999 * resume translation properly. It might be possible to reduce 1000 * this from three bits to two. 1001 */ 1002 #define MIPS_HFLAG_BMASK_BASE 0x803800 1003 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ 1004 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ 1005 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ 1006 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ 1007 /* Extra flags about the current pending branch. */ 1008 #define MIPS_HFLAG_BMASK_EXT 0x7C000 1009 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ 1010 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ 1011 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ 1012 #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */ 1013 #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */ 1014 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) 1015 /* MIPS DSP resources access. */ 1016 #define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */ 1017 #define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */ 1018 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */ 1019 /* Extra flag about HWREna register. */ 1020 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ 1021 #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */ 1022 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */ 1023 #define MIPS_HFLAG_MSA 0x1000000 1024 #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */ 1025 #define MIPS_HFLAG_ELPA 0x4000000 1026 #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */ 1027 #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */ 1028 target_ulong btarget; /* Jump / branch target */ 1029 target_ulong bcond; /* Branch condition (if needed) */ 1030 1031 int SYNCI_Step; /* Address step size for SYNCI */ 1032 int CCRes; /* Cycle count resolution/divisor */ 1033 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ 1034 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ 1035 uint64_t insn_flags; /* Supported instruction set */ 1036 int saarp; 1037 1038 /* Fields up to this point are cleared by a CPU reset */ 1039 struct {} end_reset_fields; 1040 1041 /* Fields from here on are preserved across CPU reset. */ 1042 CPUMIPSMVPContext *mvp; 1043 #if !defined(CONFIG_USER_ONLY) 1044 CPUMIPSTLBContext *tlb; 1045 #endif 1046 1047 const mips_def_t *cpu_model; 1048 void *irq[8]; 1049 QEMUTimer *timer; /* Internal timer */ 1050 struct MIPSITUState *itu; 1051 MemoryRegion *itc_tag; /* ITC Configuration Tags */ 1052 target_ulong exception_base; /* ExceptionBase input to the core */ 1053 }; 1054 1055 /** 1056 * MIPSCPU: 1057 * @env: #CPUMIPSState 1058 * 1059 * A MIPS CPU. 1060 */ 1061 struct MIPSCPU { 1062 /*< private >*/ 1063 CPUState parent_obj; 1064 /*< public >*/ 1065 1066 CPUNegativeOffsetState neg; 1067 CPUMIPSState env; 1068 }; 1069 1070 1071 void mips_cpu_list(void); 1072 1073 #define cpu_signal_handler cpu_mips_signal_handler 1074 #define cpu_list mips_cpu_list 1075 1076 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); 1077 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); 1078 1079 /* 1080 * MMU modes definitions. We carefully match the indices with our 1081 * hflags layout. 1082 */ 1083 #define MMU_MODE0_SUFFIX _kernel 1084 #define MMU_MODE1_SUFFIX _super 1085 #define MMU_MODE2_SUFFIX _user 1086 #define MMU_MODE3_SUFFIX _error 1087 #define MMU_USER_IDX 2 1088 1089 static inline int hflags_mmu_index(uint32_t hflags) 1090 { 1091 if (hflags & MIPS_HFLAG_ERL) { 1092 return 3; /* ERL */ 1093 } else { 1094 return hflags & MIPS_HFLAG_KSU; 1095 } 1096 } 1097 1098 static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) 1099 { 1100 return hflags_mmu_index(env->hflags); 1101 } 1102 1103 typedef CPUMIPSState CPUArchState; 1104 typedef MIPSCPU ArchCPU; 1105 1106 #include "exec/cpu-all.h" 1107 1108 /* 1109 * Memory access type : 1110 * may be needed for precise access rights control and precise exceptions. 1111 */ 1112 enum { 1113 /* 1 bit to define user level / supervisor access */ 1114 ACCESS_USER = 0x00, 1115 ACCESS_SUPER = 0x01, 1116 /* 1 bit to indicate direction */ 1117 ACCESS_STORE = 0x02, 1118 /* Type of instruction that generated the access */ 1119 ACCESS_CODE = 0x10, /* Code fetch access */ 1120 ACCESS_INT = 0x20, /* Integer load/store access */ 1121 ACCESS_FLOAT = 0x30, /* floating point load/store access */ 1122 }; 1123 1124 /* Exceptions */ 1125 enum { 1126 EXCP_NONE = -1, 1127 EXCP_RESET = 0, 1128 EXCP_SRESET, 1129 EXCP_DSS, 1130 EXCP_DINT, 1131 EXCP_DDBL, 1132 EXCP_DDBS, 1133 EXCP_NMI, 1134 EXCP_MCHECK, 1135 EXCP_EXT_INTERRUPT, /* 8 */ 1136 EXCP_DFWATCH, 1137 EXCP_DIB, 1138 EXCP_IWATCH, 1139 EXCP_AdEL, 1140 EXCP_AdES, 1141 EXCP_TLBF, 1142 EXCP_IBE, 1143 EXCP_DBp, /* 16 */ 1144 EXCP_SYSCALL, 1145 EXCP_BREAK, 1146 EXCP_CpU, 1147 EXCP_RI, 1148 EXCP_OVERFLOW, 1149 EXCP_TRAP, 1150 EXCP_FPE, 1151 EXCP_DWATCH, /* 24 */ 1152 EXCP_LTLBL, 1153 EXCP_TLBL, 1154 EXCP_TLBS, 1155 EXCP_DBE, 1156 EXCP_THREAD, 1157 EXCP_MDMX, 1158 EXCP_C2E, 1159 EXCP_CACHE, /* 32 */ 1160 EXCP_DSPDIS, 1161 EXCP_MSADIS, 1162 EXCP_MSAFPE, 1163 EXCP_TLBXI, 1164 EXCP_TLBRI, 1165 1166 EXCP_LAST = EXCP_TLBRI, 1167 }; 1168 1169 /* 1170 * This is an internally generated WAKE request line. 1171 * It is driven by the CPU itself. Raised when the MT 1172 * block wants to wake a VPE from an inactive state and 1173 * cleared when VPE goes from active to inactive. 1174 */ 1175 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 1176 1177 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); 1178 1179 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU 1180 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX 1181 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU 1182 1183 bool cpu_supports_cps_smp(const char *cpu_type); 1184 bool cpu_supports_isa(const char *cpu_type, uint64_t isa); 1185 void cpu_set_exception_base(int vp_index, target_ulong address); 1186 1187 /* mips_int.c */ 1188 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); 1189 1190 /* mips_itu.c */ 1191 void itc_reconfigure(struct MIPSITUState *tag); 1192 1193 /* helper.c */ 1194 target_ulong exception_resume_pc(CPUMIPSState *env); 1195 1196 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, 1197 target_ulong *cs_base, uint32_t *flags) 1198 { 1199 *pc = env->active_tc.PC; 1200 *cs_base = 0; 1201 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | 1202 MIPS_HFLAG_HWRENA_ULR); 1203 } 1204 1205 #endif /* MIPS_CPU_H */ 1206