1 #ifndef MIPS_CPU_H 2 #define MIPS_CPU_H 3 4 //#define DEBUG_OP 5 6 #define ALIGNED_ONLY 7 8 #define CPUArchState struct CPUMIPSState 9 10 #include "qemu-common.h" 11 #include "cpu-qom.h" 12 #include "mips-defs.h" 13 #include "exec/cpu-defs.h" 14 #include "fpu/softfloat.h" 15 16 struct CPUMIPSState; 17 18 typedef struct r4k_tlb_t r4k_tlb_t; 19 struct r4k_tlb_t { 20 target_ulong VPN; 21 uint32_t PageMask; 22 uint16_t ASID; 23 unsigned int G:1; 24 unsigned int C0:3; 25 unsigned int C1:3; 26 unsigned int V0:1; 27 unsigned int V1:1; 28 unsigned int D0:1; 29 unsigned int D1:1; 30 unsigned int XI0:1; 31 unsigned int XI1:1; 32 unsigned int RI0:1; 33 unsigned int RI1:1; 34 unsigned int EHINV:1; 35 uint64_t PFN[2]; 36 }; 37 38 #if !defined(CONFIG_USER_ONLY) 39 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; 40 struct CPUMIPSTLBContext { 41 uint32_t nb_tlb; 42 uint32_t tlb_in_use; 43 int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type); 44 void (*helper_tlbwi)(struct CPUMIPSState *env); 45 void (*helper_tlbwr)(struct CPUMIPSState *env); 46 void (*helper_tlbp)(struct CPUMIPSState *env); 47 void (*helper_tlbr)(struct CPUMIPSState *env); 48 void (*helper_tlbinv)(struct CPUMIPSState *env); 49 void (*helper_tlbinvf)(struct CPUMIPSState *env); 50 union { 51 struct { 52 r4k_tlb_t tlb[MIPS_TLB_MAX]; 53 } r4k; 54 } mmu; 55 }; 56 #endif 57 58 /* MSA Context */ 59 #define MSA_WRLEN (128) 60 61 enum CPUMIPSMSADataFormat { 62 DF_BYTE = 0, 63 DF_HALF, 64 DF_WORD, 65 DF_DOUBLE 66 }; 67 68 typedef union wr_t wr_t; 69 union wr_t { 70 int8_t b[MSA_WRLEN/8]; 71 int16_t h[MSA_WRLEN/16]; 72 int32_t w[MSA_WRLEN/32]; 73 int64_t d[MSA_WRLEN/64]; 74 }; 75 76 typedef union fpr_t fpr_t; 77 union fpr_t { 78 float64 fd; /* ieee double precision */ 79 float32 fs[2];/* ieee single precision */ 80 uint64_t d; /* binary double fixed-point */ 81 uint32_t w[2]; /* binary single fixed-point */ 82 /* FPU/MSA register mapping is not tested on big-endian hosts. */ 83 wr_t wr; /* vector data */ 84 }; 85 /* define FP_ENDIAN_IDX to access the same location 86 * in the fpr_t union regardless of the host endianness 87 */ 88 #if defined(HOST_WORDS_BIGENDIAN) 89 # define FP_ENDIAN_IDX 1 90 #else 91 # define FP_ENDIAN_IDX 0 92 #endif 93 94 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; 95 struct CPUMIPSFPUContext { 96 /* Floating point registers */ 97 fpr_t fpr[32]; 98 float_status fp_status; 99 /* fpu implementation/revision register (fir) */ 100 uint32_t fcr0; 101 #define FCR0_FREP 29 102 #define FCR0_UFRP 28 103 #define FCR0_HAS2008 23 104 #define FCR0_F64 22 105 #define FCR0_L 21 106 #define FCR0_W 20 107 #define FCR0_3D 19 108 #define FCR0_PS 18 109 #define FCR0_D 17 110 #define FCR0_S 16 111 #define FCR0_PRID 8 112 #define FCR0_REV 0 113 /* fcsr */ 114 uint32_t fcr31_rw_bitmask; 115 uint32_t fcr31; 116 #define FCR31_FS 24 117 #define FCR31_ABS2008 19 118 #define FCR31_NAN2008 18 119 #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) 120 #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) 121 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1)) 122 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) 123 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 124 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) 125 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) 126 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) 127 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) 128 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) 129 #define FP_INEXACT 1 130 #define FP_UNDERFLOW 2 131 #define FP_OVERFLOW 4 132 #define FP_DIV0 8 133 #define FP_INVALID 16 134 #define FP_UNIMPLEMENTED 32 135 }; 136 137 #define NB_MMU_MODES 3 138 #define TARGET_INSN_START_EXTRA_WORDS 2 139 140 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; 141 struct CPUMIPSMVPContext { 142 int32_t CP0_MVPControl; 143 #define CP0MVPCo_CPA 3 144 #define CP0MVPCo_STLB 2 145 #define CP0MVPCo_VPC 1 146 #define CP0MVPCo_EVP 0 147 int32_t CP0_MVPConf0; 148 #define CP0MVPC0_M 31 149 #define CP0MVPC0_TLBS 29 150 #define CP0MVPC0_GS 28 151 #define CP0MVPC0_PCP 27 152 #define CP0MVPC0_PTLBE 16 153 #define CP0MVPC0_TCA 15 154 #define CP0MVPC0_PVPE 10 155 #define CP0MVPC0_PTC 0 156 int32_t CP0_MVPConf1; 157 #define CP0MVPC1_CIM 31 158 #define CP0MVPC1_CIF 30 159 #define CP0MVPC1_PCX 20 160 #define CP0MVPC1_PCP2 10 161 #define CP0MVPC1_PCP1 0 162 }; 163 164 typedef struct mips_def_t mips_def_t; 165 166 #define MIPS_SHADOW_SET_MAX 16 167 #define MIPS_TC_MAX 5 168 #define MIPS_FPU_MAX 1 169 #define MIPS_DSP_ACC 4 170 #define MIPS_KSCRATCH_NUM 6 171 #define MIPS_MAAR_MAX 16 /* Must be an even number. */ 172 173 typedef struct TCState TCState; 174 struct TCState { 175 target_ulong gpr[32]; 176 target_ulong PC; 177 target_ulong HI[MIPS_DSP_ACC]; 178 target_ulong LO[MIPS_DSP_ACC]; 179 target_ulong ACX[MIPS_DSP_ACC]; 180 target_ulong DSPControl; 181 int32_t CP0_TCStatus; 182 #define CP0TCSt_TCU3 31 183 #define CP0TCSt_TCU2 30 184 #define CP0TCSt_TCU1 29 185 #define CP0TCSt_TCU0 28 186 #define CP0TCSt_TMX 27 187 #define CP0TCSt_RNST 23 188 #define CP0TCSt_TDS 21 189 #define CP0TCSt_DT 20 190 #define CP0TCSt_DA 15 191 #define CP0TCSt_A 13 192 #define CP0TCSt_TKSU 11 193 #define CP0TCSt_IXMT 10 194 #define CP0TCSt_TASID 0 195 int32_t CP0_TCBind; 196 #define CP0TCBd_CurTC 21 197 #define CP0TCBd_TBE 17 198 #define CP0TCBd_CurVPE 0 199 target_ulong CP0_TCHalt; 200 target_ulong CP0_TCContext; 201 target_ulong CP0_TCSchedule; 202 target_ulong CP0_TCScheFBack; 203 int32_t CP0_Debug_tcstatus; 204 target_ulong CP0_UserLocal; 205 206 int32_t msacsr; 207 208 #define MSACSR_FS 24 209 #define MSACSR_FS_MASK (1 << MSACSR_FS) 210 #define MSACSR_NX 18 211 #define MSACSR_NX_MASK (1 << MSACSR_NX) 212 #define MSACSR_CEF 2 213 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF) 214 #define MSACSR_RM 0 215 #define MSACSR_RM_MASK (0x3 << MSACSR_RM) 216 #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \ 217 MSACSR_FS_MASK) 218 219 float_status msa_fp_status; 220 }; 221 222 typedef struct CPUMIPSState CPUMIPSState; 223 struct CPUMIPSState { 224 TCState active_tc; 225 CPUMIPSFPUContext active_fpu; 226 227 uint32_t current_tc; 228 uint32_t current_fpu; 229 230 uint32_t SEGBITS; 231 uint32_t PABITS; 232 #if defined(TARGET_MIPS64) 233 # define PABITS_BASE 36 234 #else 235 # define PABITS_BASE 32 236 #endif 237 target_ulong SEGMask; 238 uint64_t PAMask; 239 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1) 240 241 int32_t msair; 242 #define MSAIR_ProcID 8 243 #define MSAIR_Rev 0 244 245 int32_t CP0_Index; 246 /* CP0_MVP* are per MVP registers. */ 247 int32_t CP0_VPControl; 248 #define CP0VPCtl_DIS 0 249 int32_t CP0_Random; 250 int32_t CP0_VPEControl; 251 #define CP0VPECo_YSI 21 252 #define CP0VPECo_GSI 20 253 #define CP0VPECo_EXCPT 16 254 #define CP0VPECo_TE 15 255 #define CP0VPECo_TargTC 0 256 int32_t CP0_VPEConf0; 257 #define CP0VPEC0_M 31 258 #define CP0VPEC0_XTC 21 259 #define CP0VPEC0_TCS 19 260 #define CP0VPEC0_SCS 18 261 #define CP0VPEC0_DSC 17 262 #define CP0VPEC0_ICS 16 263 #define CP0VPEC0_MVP 1 264 #define CP0VPEC0_VPA 0 265 int32_t CP0_VPEConf1; 266 #define CP0VPEC1_NCX 20 267 #define CP0VPEC1_NCP2 10 268 #define CP0VPEC1_NCP1 0 269 target_ulong CP0_YQMask; 270 target_ulong CP0_VPESchedule; 271 target_ulong CP0_VPEScheFBack; 272 int32_t CP0_VPEOpt; 273 #define CP0VPEOpt_IWX7 15 274 #define CP0VPEOpt_IWX6 14 275 #define CP0VPEOpt_IWX5 13 276 #define CP0VPEOpt_IWX4 12 277 #define CP0VPEOpt_IWX3 11 278 #define CP0VPEOpt_IWX2 10 279 #define CP0VPEOpt_IWX1 9 280 #define CP0VPEOpt_IWX0 8 281 #define CP0VPEOpt_DWX7 7 282 #define CP0VPEOpt_DWX6 6 283 #define CP0VPEOpt_DWX5 5 284 #define CP0VPEOpt_DWX4 4 285 #define CP0VPEOpt_DWX3 3 286 #define CP0VPEOpt_DWX2 2 287 #define CP0VPEOpt_DWX1 1 288 #define CP0VPEOpt_DWX0 0 289 uint64_t CP0_EntryLo0; 290 uint64_t CP0_EntryLo1; 291 #if defined(TARGET_MIPS64) 292 # define CP0EnLo_RI 63 293 # define CP0EnLo_XI 62 294 #else 295 # define CP0EnLo_RI 31 296 # define CP0EnLo_XI 30 297 #endif 298 int32_t CP0_GlobalNumber; 299 #define CP0GN_VPId 0 300 target_ulong CP0_Context; 301 target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; 302 int32_t CP0_PageMask; 303 int32_t CP0_PageGrain_rw_bitmask; 304 int32_t CP0_PageGrain; 305 #define CP0PG_RIE 31 306 #define CP0PG_XIE 30 307 #define CP0PG_ELPA 29 308 #define CP0PG_IEC 27 309 int32_t CP0_Wired; 310 int32_t CP0_SRSConf0_rw_bitmask; 311 int32_t CP0_SRSConf0; 312 #define CP0SRSC0_M 31 313 #define CP0SRSC0_SRS3 20 314 #define CP0SRSC0_SRS2 10 315 #define CP0SRSC0_SRS1 0 316 int32_t CP0_SRSConf1_rw_bitmask; 317 int32_t CP0_SRSConf1; 318 #define CP0SRSC1_M 31 319 #define CP0SRSC1_SRS6 20 320 #define CP0SRSC1_SRS5 10 321 #define CP0SRSC1_SRS4 0 322 int32_t CP0_SRSConf2_rw_bitmask; 323 int32_t CP0_SRSConf2; 324 #define CP0SRSC2_M 31 325 #define CP0SRSC2_SRS9 20 326 #define CP0SRSC2_SRS8 10 327 #define CP0SRSC2_SRS7 0 328 int32_t CP0_SRSConf3_rw_bitmask; 329 int32_t CP0_SRSConf3; 330 #define CP0SRSC3_M 31 331 #define CP0SRSC3_SRS12 20 332 #define CP0SRSC3_SRS11 10 333 #define CP0SRSC3_SRS10 0 334 int32_t CP0_SRSConf4_rw_bitmask; 335 int32_t CP0_SRSConf4; 336 #define CP0SRSC4_SRS15 20 337 #define CP0SRSC4_SRS14 10 338 #define CP0SRSC4_SRS13 0 339 int32_t CP0_HWREna; 340 target_ulong CP0_BadVAddr; 341 uint32_t CP0_BadInstr; 342 uint32_t CP0_BadInstrP; 343 int32_t CP0_Count; 344 target_ulong CP0_EntryHi; 345 #define CP0EnHi_EHINV 10 346 target_ulong CP0_EntryHi_ASID_mask; 347 int32_t CP0_Compare; 348 int32_t CP0_Status; 349 #define CP0St_CU3 31 350 #define CP0St_CU2 30 351 #define CP0St_CU1 29 352 #define CP0St_CU0 28 353 #define CP0St_RP 27 354 #define CP0St_FR 26 355 #define CP0St_RE 25 356 #define CP0St_MX 24 357 #define CP0St_PX 23 358 #define CP0St_BEV 22 359 #define CP0St_TS 21 360 #define CP0St_SR 20 361 #define CP0St_NMI 19 362 #define CP0St_IM 8 363 #define CP0St_KX 7 364 #define CP0St_SX 6 365 #define CP0St_UX 5 366 #define CP0St_KSU 3 367 #define CP0St_ERL 2 368 #define CP0St_EXL 1 369 #define CP0St_IE 0 370 int32_t CP0_IntCtl; 371 #define CP0IntCtl_IPTI 29 372 #define CP0IntCtl_IPPCI 26 373 #define CP0IntCtl_VS 5 374 int32_t CP0_SRSCtl; 375 #define CP0SRSCtl_HSS 26 376 #define CP0SRSCtl_EICSS 18 377 #define CP0SRSCtl_ESS 12 378 #define CP0SRSCtl_PSS 6 379 #define CP0SRSCtl_CSS 0 380 int32_t CP0_SRSMap; 381 #define CP0SRSMap_SSV7 28 382 #define CP0SRSMap_SSV6 24 383 #define CP0SRSMap_SSV5 20 384 #define CP0SRSMap_SSV4 16 385 #define CP0SRSMap_SSV3 12 386 #define CP0SRSMap_SSV2 8 387 #define CP0SRSMap_SSV1 4 388 #define CP0SRSMap_SSV0 0 389 int32_t CP0_Cause; 390 #define CP0Ca_BD 31 391 #define CP0Ca_TI 30 392 #define CP0Ca_CE 28 393 #define CP0Ca_DC 27 394 #define CP0Ca_PCI 26 395 #define CP0Ca_IV 23 396 #define CP0Ca_WP 22 397 #define CP0Ca_IP 8 398 #define CP0Ca_IP_mask 0x0000FF00 399 #define CP0Ca_EC 2 400 target_ulong CP0_EPC; 401 int32_t CP0_PRid; 402 int32_t CP0_EBase; 403 target_ulong CP0_CMGCRBase; 404 int32_t CP0_Config0; 405 #define CP0C0_M 31 406 #define CP0C0_K23 28 407 #define CP0C0_KU 25 408 #define CP0C0_MDU 20 409 #define CP0C0_MM 18 410 #define CP0C0_BM 16 411 #define CP0C0_BE 15 412 #define CP0C0_AT 13 413 #define CP0C0_AR 10 414 #define CP0C0_MT 7 415 #define CP0C0_VI 3 416 #define CP0C0_K0 0 417 int32_t CP0_Config1; 418 #define CP0C1_M 31 419 #define CP0C1_MMU 25 420 #define CP0C1_IS 22 421 #define CP0C1_IL 19 422 #define CP0C1_IA 16 423 #define CP0C1_DS 13 424 #define CP0C1_DL 10 425 #define CP0C1_DA 7 426 #define CP0C1_C2 6 427 #define CP0C1_MD 5 428 #define CP0C1_PC 4 429 #define CP0C1_WR 3 430 #define CP0C1_CA 2 431 #define CP0C1_EP 1 432 #define CP0C1_FP 0 433 int32_t CP0_Config2; 434 #define CP0C2_M 31 435 #define CP0C2_TU 28 436 #define CP0C2_TS 24 437 #define CP0C2_TL 20 438 #define CP0C2_TA 16 439 #define CP0C2_SU 12 440 #define CP0C2_SS 8 441 #define CP0C2_SL 4 442 #define CP0C2_SA 0 443 int32_t CP0_Config3; 444 #define CP0C3_M 31 445 #define CP0C3_BPG 30 446 #define CP0C3_CMGCR 29 447 #define CP0C3_MSAP 28 448 #define CP0C3_BP 27 449 #define CP0C3_BI 26 450 #define CP0C3_IPLW 21 451 #define CP0C3_MMAR 18 452 #define CP0C3_MCU 17 453 #define CP0C3_ISA_ON_EXC 16 454 #define CP0C3_ISA 14 455 #define CP0C3_ULRI 13 456 #define CP0C3_RXI 12 457 #define CP0C3_DSP2P 11 458 #define CP0C3_DSPP 10 459 #define CP0C3_LPA 7 460 #define CP0C3_VEIC 6 461 #define CP0C3_VInt 5 462 #define CP0C3_SP 4 463 #define CP0C3_CDMM 3 464 #define CP0C3_MT 2 465 #define CP0C3_SM 1 466 #define CP0C3_TL 0 467 int32_t CP0_Config4; 468 int32_t CP0_Config4_rw_bitmask; 469 #define CP0C4_M 31 470 #define CP0C4_IE 29 471 #define CP0C4_AE 28 472 #define CP0C4_KScrExist 16 473 #define CP0C4_MMUExtDef 14 474 #define CP0C4_FTLBPageSize 8 475 #define CP0C4_FTLBWays 4 476 #define CP0C4_FTLBSets 0 477 #define CP0C4_MMUSizeExt 0 478 int32_t CP0_Config5; 479 int32_t CP0_Config5_rw_bitmask; 480 #define CP0C5_M 31 481 #define CP0C5_K 30 482 #define CP0C5_CV 29 483 #define CP0C5_EVA 28 484 #define CP0C5_MSAEn 27 485 #define CP0C5_XNP 13 486 #define CP0C5_UFE 9 487 #define CP0C5_FRE 8 488 #define CP0C5_VP 7 489 #define CP0C5_SBRI 6 490 #define CP0C5_MVH 5 491 #define CP0C5_LLB 4 492 #define CP0C5_MRP 3 493 #define CP0C5_UFR 2 494 #define CP0C5_NFExists 0 495 int32_t CP0_Config6; 496 int32_t CP0_Config7; 497 uint64_t CP0_MAAR[MIPS_MAAR_MAX]; 498 int32_t CP0_MAARI; 499 /* XXX: Maybe make LLAddr per-TC? */ 500 uint64_t lladdr; 501 target_ulong llval; 502 target_ulong llnewval; 503 target_ulong llreg; 504 uint64_t CP0_LLAddr_rw_bitmask; 505 int CP0_LLAddr_shift; 506 target_ulong CP0_WatchLo[8]; 507 int32_t CP0_WatchHi[8]; 508 #define CP0WH_ASID 16 509 target_ulong CP0_XContext; 510 int32_t CP0_Framemask; 511 int32_t CP0_Debug; 512 #define CP0DB_DBD 31 513 #define CP0DB_DM 30 514 #define CP0DB_LSNM 28 515 #define CP0DB_Doze 27 516 #define CP0DB_Halt 26 517 #define CP0DB_CNT 25 518 #define CP0DB_IBEP 24 519 #define CP0DB_DBEP 21 520 #define CP0DB_IEXI 20 521 #define CP0DB_VER 15 522 #define CP0DB_DEC 10 523 #define CP0DB_SSt 8 524 #define CP0DB_DINT 5 525 #define CP0DB_DIB 4 526 #define CP0DB_DDBS 3 527 #define CP0DB_DDBL 2 528 #define CP0DB_DBp 1 529 #define CP0DB_DSS 0 530 target_ulong CP0_DEPC; 531 int32_t CP0_Performance0; 532 int32_t CP0_ErrCtl; 533 #define CP0EC_WST 29 534 #define CP0EC_SPR 28 535 #define CP0EC_ITC 26 536 uint64_t CP0_TagLo; 537 int32_t CP0_DataLo; 538 int32_t CP0_TagHi; 539 int32_t CP0_DataHi; 540 target_ulong CP0_ErrorEPC; 541 int32_t CP0_DESAVE; 542 /* We waste some space so we can handle shadow registers like TCs. */ 543 TCState tcs[MIPS_SHADOW_SET_MAX]; 544 CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; 545 /* QEMU */ 546 int error_code; 547 #define EXCP_TLB_NOMATCH 0x1 548 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ 549 uint32_t hflags; /* CPU State */ 550 /* TMASK defines different execution modes */ 551 #define MIPS_HFLAG_TMASK 0xF5807FF 552 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ 553 /* The KSU flags must be the lowest bits in hflags. The flag order 554 must be the same as defined for CP0 Status. This allows to use 555 the bits as the value of mmu_idx. */ 556 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ 557 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ 558 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ 559 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ 560 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ 561 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ 562 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ 563 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ 564 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ 565 /* True if the MIPS IV COP1X instructions can be used. This also 566 controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S 567 and RSQRT.D. */ 568 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ 569 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ 570 #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ 571 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ 572 #define MIPS_HFLAG_M16_SHIFT 10 573 /* If translation is interrupted between the branch instruction and 574 * the delay slot, record what type of branch it is so that we can 575 * resume translation properly. It might be possible to reduce 576 * this from three bits to two. */ 577 #define MIPS_HFLAG_BMASK_BASE 0x803800 578 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ 579 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ 580 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ 581 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ 582 /* Extra flags about the current pending branch. */ 583 #define MIPS_HFLAG_BMASK_EXT 0x7C000 584 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ 585 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ 586 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ 587 #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */ 588 #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */ 589 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) 590 /* MIPS DSP resources access. */ 591 #define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources. */ 592 #define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resources. */ 593 /* Extra flag about HWREna register. */ 594 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ 595 #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */ 596 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */ 597 #define MIPS_HFLAG_MSA 0x1000000 598 #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */ 599 #define MIPS_HFLAG_ELPA 0x4000000 600 #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */ 601 target_ulong btarget; /* Jump / branch target */ 602 target_ulong bcond; /* Branch condition (if needed) */ 603 604 int SYNCI_Step; /* Address step size for SYNCI */ 605 int CCRes; /* Cycle count resolution/divisor */ 606 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ 607 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ 608 int insn_flags; /* Supported instruction set */ 609 610 /* Fields up to this point are cleared by a CPU reset */ 611 struct {} end_reset_fields; 612 613 CPU_COMMON 614 615 /* Fields from here on are preserved across CPU reset. */ 616 CPUMIPSMVPContext *mvp; 617 #if !defined(CONFIG_USER_ONLY) 618 CPUMIPSTLBContext *tlb; 619 #endif 620 621 const mips_def_t *cpu_model; 622 void *irq[8]; 623 QEMUTimer *timer; /* Internal timer */ 624 MemoryRegion *itc_tag; /* ITC Configuration Tags */ 625 target_ulong exception_base; /* ExceptionBase input to the core */ 626 }; 627 628 /** 629 * MIPSCPU: 630 * @env: #CPUMIPSState 631 * 632 * A MIPS CPU. 633 */ 634 struct MIPSCPU { 635 /*< private >*/ 636 CPUState parent_obj; 637 /*< public >*/ 638 639 CPUMIPSState env; 640 }; 641 642 static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) 643 { 644 return container_of(env, MIPSCPU, env); 645 } 646 647 #define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e)) 648 649 #define ENV_OFFSET offsetof(MIPSCPU, env) 650 651 #ifndef CONFIG_USER_ONLY 652 extern const struct VMStateDescription vmstate_mips_cpu; 653 #endif 654 655 void mips_cpu_do_interrupt(CPUState *cpu); 656 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); 657 void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, 658 int flags); 659 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 660 int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 661 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 662 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 663 MMUAccessType access_type, 664 int mmu_idx, uintptr_t retaddr); 665 666 #if !defined(CONFIG_USER_ONLY) 667 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, 668 target_ulong address, int rw, int access_type); 669 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, 670 target_ulong address, int rw, int access_type); 671 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, 672 target_ulong address, int rw, int access_type); 673 void r4k_helper_tlbwi(CPUMIPSState *env); 674 void r4k_helper_tlbwr(CPUMIPSState *env); 675 void r4k_helper_tlbp(CPUMIPSState *env); 676 void r4k_helper_tlbr(CPUMIPSState *env); 677 void r4k_helper_tlbinv(CPUMIPSState *env); 678 void r4k_helper_tlbinvf(CPUMIPSState *env); 679 680 void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr, 681 bool is_write, bool is_exec, int unused, 682 unsigned size); 683 #endif 684 685 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); 686 687 #define cpu_signal_handler cpu_mips_signal_handler 688 #define cpu_list mips_cpu_list 689 690 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); 691 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); 692 693 /* MMU modes definitions. We carefully match the indices with our 694 hflags layout. */ 695 #define MMU_MODE0_SUFFIX _kernel 696 #define MMU_MODE1_SUFFIX _super 697 #define MMU_MODE2_SUFFIX _user 698 #define MMU_USER_IDX 2 699 static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch) 700 { 701 return env->hflags & MIPS_HFLAG_KSU; 702 } 703 704 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) 705 { 706 return (env->CP0_Status & (1 << CP0St_IE)) && 707 !(env->CP0_Status & (1 << CP0St_EXL)) && 708 !(env->CP0_Status & (1 << CP0St_ERL)) && 709 !(env->hflags & MIPS_HFLAG_DM) && 710 /* Note that the TCStatus IXMT field is initialized to zero, 711 and only MT capable cores can set it to one. So we don't 712 need to check for MT capabilities here. */ 713 !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); 714 } 715 716 /* Check if there is pending and not masked out interrupt */ 717 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) 718 { 719 int32_t pending; 720 int32_t status; 721 bool r; 722 723 pending = env->CP0_Cause & CP0Ca_IP_mask; 724 status = env->CP0_Status & CP0Ca_IP_mask; 725 726 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { 727 /* A MIPS configured with a vectorizing external interrupt controller 728 will feed a vector into the Cause pending lines. The core treats 729 the status lines as a vector level, not as indiviual masks. */ 730 r = pending > status; 731 } else { 732 /* A MIPS configured with compatibility or VInt (Vectored Interrupts) 733 treats the pending lines as individual interrupt lines, the status 734 lines are individual masks. */ 735 r = (pending & status) != 0; 736 } 737 return r; 738 } 739 740 #include "exec/cpu-all.h" 741 742 /* Memory access type : 743 * may be needed for precise access rights control and precise exceptions. 744 */ 745 enum { 746 /* 1 bit to define user level / supervisor access */ 747 ACCESS_USER = 0x00, 748 ACCESS_SUPER = 0x01, 749 /* 1 bit to indicate direction */ 750 ACCESS_STORE = 0x02, 751 /* Type of instruction that generated the access */ 752 ACCESS_CODE = 0x10, /* Code fetch access */ 753 ACCESS_INT = 0x20, /* Integer load/store access */ 754 ACCESS_FLOAT = 0x30, /* floating point load/store access */ 755 }; 756 757 /* Exceptions */ 758 enum { 759 EXCP_NONE = -1, 760 EXCP_RESET = 0, 761 EXCP_SRESET, 762 EXCP_DSS, 763 EXCP_DINT, 764 EXCP_DDBL, 765 EXCP_DDBS, 766 EXCP_NMI, 767 EXCP_MCHECK, 768 EXCP_EXT_INTERRUPT, /* 8 */ 769 EXCP_DFWATCH, 770 EXCP_DIB, 771 EXCP_IWATCH, 772 EXCP_AdEL, 773 EXCP_AdES, 774 EXCP_TLBF, 775 EXCP_IBE, 776 EXCP_DBp, /* 16 */ 777 EXCP_SYSCALL, 778 EXCP_BREAK, 779 EXCP_CpU, 780 EXCP_RI, 781 EXCP_OVERFLOW, 782 EXCP_TRAP, 783 EXCP_FPE, 784 EXCP_DWATCH, /* 24 */ 785 EXCP_LTLBL, 786 EXCP_TLBL, 787 EXCP_TLBS, 788 EXCP_DBE, 789 EXCP_THREAD, 790 EXCP_MDMX, 791 EXCP_C2E, 792 EXCP_CACHE, /* 32 */ 793 EXCP_DSPDIS, 794 EXCP_MSADIS, 795 EXCP_MSAFPE, 796 EXCP_TLBXI, 797 EXCP_TLBRI, 798 799 EXCP_LAST = EXCP_TLBRI, 800 }; 801 /* Dummy exception for conditional stores. */ 802 #define EXCP_SC 0x100 803 804 /* 805 * This is an interrnally generated WAKE request line. 806 * It is driven by the CPU itself. Raised when the MT 807 * block wants to wake a VPE from an inactive state and 808 * cleared when VPE goes from active to inactive. 809 */ 810 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 811 812 void mips_tcg_init(void); 813 MIPSCPU *cpu_mips_init(const char *cpu_model); 814 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); 815 816 #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model)) 817 bool cpu_supports_cps_smp(const char *cpu_model); 818 bool cpu_supports_isa(const char *cpu_model, unsigned int isa); 819 void cpu_set_exception_base(int vp_index, target_ulong address); 820 821 /* TODO QOM'ify CPU reset and remove */ 822 void cpu_state_reset(CPUMIPSState *s); 823 824 /* mips_timer.c */ 825 uint32_t cpu_mips_get_random (CPUMIPSState *env); 826 uint32_t cpu_mips_get_count (CPUMIPSState *env); 827 void cpu_mips_store_count (CPUMIPSState *env, uint32_t value); 828 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value); 829 void cpu_mips_start_count(CPUMIPSState *env); 830 void cpu_mips_stop_count(CPUMIPSState *env); 831 832 /* mips_int.c */ 833 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); 834 835 /* helper.c */ 836 int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, 837 int mmu_idx); 838 839 /* op_helper.c */ 840 uint32_t float_class_s(uint32_t arg, float_status *fst); 841 uint64_t float_class_d(uint64_t arg, float_status *fst); 842 843 #if !defined(CONFIG_USER_ONLY) 844 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra); 845 hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address, 846 int rw); 847 #endif 848 target_ulong exception_resume_pc (CPUMIPSState *env); 849 850 /* op_helper.c */ 851 extern unsigned int ieee_rm[]; 852 int ieee_ex_to_mips(int xcpt); 853 854 static inline void restore_rounding_mode(CPUMIPSState *env) 855 { 856 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], 857 &env->active_fpu.fp_status); 858 } 859 860 static inline void restore_flush_mode(CPUMIPSState *env) 861 { 862 set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0, 863 &env->active_fpu.fp_status); 864 } 865 866 static inline void restore_snan_bit_mode(CPUMIPSState *env) 867 { 868 set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, 869 &env->active_fpu.fp_status); 870 } 871 872 static inline void restore_fp_status(CPUMIPSState *env) 873 { 874 restore_rounding_mode(env); 875 restore_flush_mode(env); 876 restore_snan_bit_mode(env); 877 } 878 879 static inline void restore_msa_fp_status(CPUMIPSState *env) 880 { 881 float_status *status = &env->active_tc.msa_fp_status; 882 int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM; 883 bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0; 884 885 set_float_rounding_mode(ieee_rm[rounding_mode], status); 886 set_flush_to_zero(flush_to_zero, status); 887 set_flush_inputs_to_zero(flush_to_zero, status); 888 } 889 890 static inline void restore_pamask(CPUMIPSState *env) 891 { 892 if (env->hflags & MIPS_HFLAG_ELPA) { 893 env->PAMask = (1ULL << env->PABITS) - 1; 894 } else { 895 env->PAMask = PAMASK_BASE; 896 } 897 } 898 899 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, 900 target_ulong *cs_base, uint32_t *flags) 901 { 902 *pc = env->active_tc.PC; 903 *cs_base = 0; 904 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | 905 MIPS_HFLAG_HWRENA_ULR); 906 } 907 908 static inline int mips_vpe_active(CPUMIPSState *env) 909 { 910 int active = 1; 911 912 /* Check that the VPE is enabled. */ 913 if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { 914 active = 0; 915 } 916 /* Check that the VPE is activated. */ 917 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { 918 active = 0; 919 } 920 921 /* Now verify that there are active thread contexts in the VPE. 922 923 This assumes the CPU model will internally reschedule threads 924 if the active one goes to sleep. If there are no threads available 925 the active one will be in a sleeping state, and we can turn off 926 the entire VPE. */ 927 if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { 928 /* TC is not activated. */ 929 active = 0; 930 } 931 if (env->active_tc.CP0_TCHalt & 1) { 932 /* TC is in halt state. */ 933 active = 0; 934 } 935 936 return active; 937 } 938 939 static inline int mips_vp_active(CPUMIPSState *env) 940 { 941 CPUState *other_cs = first_cpu; 942 943 /* Check if the VP disabled other VPs (which means the VP is enabled) */ 944 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { 945 return 1; 946 } 947 948 /* Check if the virtual processor is disabled due to a DVP */ 949 CPU_FOREACH(other_cs) { 950 MIPSCPU *other_cpu = MIPS_CPU(other_cs); 951 if ((&other_cpu->env != env) && 952 ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) { 953 return 0; 954 } 955 } 956 return 1; 957 } 958 959 static inline void compute_hflags(CPUMIPSState *env) 960 { 961 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | 962 MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | 963 MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 | 964 MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE | 965 MIPS_HFLAG_ELPA); 966 if (!(env->CP0_Status & (1 << CP0St_EXL)) && 967 !(env->CP0_Status & (1 << CP0St_ERL)) && 968 !(env->hflags & MIPS_HFLAG_DM)) { 969 env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; 970 } 971 #if defined(TARGET_MIPS64) 972 if ((env->insn_flags & ISA_MIPS3) && 973 (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || 974 (env->CP0_Status & (1 << CP0St_PX)) || 975 (env->CP0_Status & (1 << CP0St_UX)))) { 976 env->hflags |= MIPS_HFLAG_64; 977 } 978 979 if (!(env->insn_flags & ISA_MIPS3)) { 980 env->hflags |= MIPS_HFLAG_AWRAP; 981 } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && 982 !(env->CP0_Status & (1 << CP0St_UX))) { 983 env->hflags |= MIPS_HFLAG_AWRAP; 984 } else if (env->insn_flags & ISA_MIPS64R6) { 985 /* Address wrapping for Supervisor and Kernel is specified in R6 */ 986 if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) && 987 !(env->CP0_Status & (1 << CP0St_SX))) || 988 (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) && 989 !(env->CP0_Status & (1 << CP0St_KX)))) { 990 env->hflags |= MIPS_HFLAG_AWRAP; 991 } 992 } 993 #endif 994 if (((env->CP0_Status & (1 << CP0St_CU0)) && 995 !(env->insn_flags & ISA_MIPS32R6)) || 996 !(env->hflags & MIPS_HFLAG_KSU)) { 997 env->hflags |= MIPS_HFLAG_CP0; 998 } 999 if (env->CP0_Status & (1 << CP0St_CU1)) { 1000 env->hflags |= MIPS_HFLAG_FPU; 1001 } 1002 if (env->CP0_Status & (1 << CP0St_FR)) { 1003 env->hflags |= MIPS_HFLAG_F64; 1004 } 1005 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) && 1006 (env->CP0_Config5 & (1 << CP0C5_SBRI))) { 1007 env->hflags |= MIPS_HFLAG_SBRI; 1008 } 1009 if (env->insn_flags & ASE_DSPR2) { 1010 /* Enables access MIPS DSP resources, now our cpu is DSP ASER2, 1011 so enable to access DSPR2 resources. */ 1012 if (env->CP0_Status & (1 << CP0St_MX)) { 1013 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2; 1014 } 1015 1016 } else if (env->insn_flags & ASE_DSP) { 1017 /* Enables access MIPS DSP resources, now our cpu is DSP ASE, 1018 so enable to access DSP resources. */ 1019 if (env->CP0_Status & (1 << CP0St_MX)) { 1020 env->hflags |= MIPS_HFLAG_DSP; 1021 } 1022 1023 } 1024 if (env->insn_flags & ISA_MIPS32R2) { 1025 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { 1026 env->hflags |= MIPS_HFLAG_COP1X; 1027 } 1028 } else if (env->insn_flags & ISA_MIPS32) { 1029 if (env->hflags & MIPS_HFLAG_64) { 1030 env->hflags |= MIPS_HFLAG_COP1X; 1031 } 1032 } else if (env->insn_flags & ISA_MIPS4) { 1033 /* All supported MIPS IV CPUs use the XX (CU3) to enable 1034 and disable the MIPS IV extensions to the MIPS III ISA. 1035 Some other MIPS IV CPUs ignore the bit, so the check here 1036 would be too restrictive for them. */ 1037 if (env->CP0_Status & (1U << CP0St_CU3)) { 1038 env->hflags |= MIPS_HFLAG_COP1X; 1039 } 1040 } 1041 if (env->insn_flags & ASE_MSA) { 1042 if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { 1043 env->hflags |= MIPS_HFLAG_MSA; 1044 } 1045 } 1046 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { 1047 if (env->CP0_Config5 & (1 << CP0C5_FRE)) { 1048 env->hflags |= MIPS_HFLAG_FRE; 1049 } 1050 } 1051 if (env->CP0_Config3 & (1 << CP0C3_LPA)) { 1052 if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) { 1053 env->hflags |= MIPS_HFLAG_ELPA; 1054 } 1055 } 1056 } 1057 1058 void cpu_mips_tlb_flush(CPUMIPSState *env); 1059 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); 1060 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); 1061 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); 1062 1063 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception, 1064 int error_code, uintptr_t pc); 1065 1066 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, 1067 uint32_t exception, 1068 uintptr_t pc) 1069 { 1070 do_raise_exception_err(env, exception, 0, pc); 1071 } 1072 1073 #endif /* MIPS_CPU_H */ 1074