1 #ifndef MIPS_CPU_H 2 #define MIPS_CPU_H 3 4 #define ALIGNED_ONLY 5 6 #define CPUArchState struct CPUMIPSState 7 8 #include "qemu-common.h" 9 #include "cpu-qom.h" 10 #include "exec/cpu-defs.h" 11 #include "fpu/softfloat.h" 12 #include "mips-defs.h" 13 14 #define TCG_GUEST_DEFAULT_MO (0) 15 16 struct CPUMIPSState; 17 18 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; 19 20 /* MSA Context */ 21 #define MSA_WRLEN (128) 22 23 typedef union wr_t wr_t; 24 union wr_t { 25 int8_t b[MSA_WRLEN / 8]; 26 int16_t h[MSA_WRLEN / 16]; 27 int32_t w[MSA_WRLEN / 32]; 28 int64_t d[MSA_WRLEN / 64]; 29 }; 30 31 typedef union fpr_t fpr_t; 32 union fpr_t { 33 float64 fd; /* ieee double precision */ 34 float32 fs[2];/* ieee single precision */ 35 uint64_t d; /* binary double fixed-point */ 36 uint32_t w[2]; /* binary single fixed-point */ 37 /* FPU/MSA register mapping is not tested on big-endian hosts. */ 38 wr_t wr; /* vector data */ 39 }; 40 /* 41 *define FP_ENDIAN_IDX to access the same location 42 * in the fpr_t union regardless of the host endianness 43 */ 44 #if defined(HOST_WORDS_BIGENDIAN) 45 # define FP_ENDIAN_IDX 1 46 #else 47 # define FP_ENDIAN_IDX 0 48 #endif 49 50 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; 51 struct CPUMIPSFPUContext { 52 /* Floating point registers */ 53 fpr_t fpr[32]; 54 float_status fp_status; 55 /* fpu implementation/revision register (fir) */ 56 uint32_t fcr0; 57 #define FCR0_FREP 29 58 #define FCR0_UFRP 28 59 #define FCR0_HAS2008 23 60 #define FCR0_F64 22 61 #define FCR0_L 21 62 #define FCR0_W 20 63 #define FCR0_3D 19 64 #define FCR0_PS 18 65 #define FCR0_D 17 66 #define FCR0_S 16 67 #define FCR0_PRID 8 68 #define FCR0_REV 0 69 /* fcsr */ 70 uint32_t fcr31_rw_bitmask; 71 uint32_t fcr31; 72 #define FCR31_FS 24 73 #define FCR31_ABS2008 19 74 #define FCR31_NAN2008 18 75 #define SET_FP_COND(num, env) do { ((env).fcr31) |= \ 76 ((num) ? (1 << ((num) + 24)) : \ 77 (1 << 23)); \ 78 } while (0) 79 #define CLEAR_FP_COND(num, env) do { ((env).fcr31) &= \ 80 ~((num) ? (1 << ((num) + 24)) : \ 81 (1 << 23)); \ 82 } while (0) 83 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \ 84 (((env).fcr31 >> 23) & 0x1)) 85 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) 86 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 87 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) 88 #define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \ 89 ((v & 0x3f) << 12); \ 90 } while (0) 91 #define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \ 92 ((v & 0x1f) << 7); \ 93 } while (0) 94 #define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 2)) | \ 95 ((v & 0x1f) << 2); \ 96 } while (0) 97 #define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 2); } while (0) 98 #define FP_INEXACT 1 99 #define FP_UNDERFLOW 2 100 #define FP_OVERFLOW 4 101 #define FP_DIV0 8 102 #define FP_INVALID 16 103 #define FP_UNIMPLEMENTED 32 104 }; 105 106 #define TARGET_INSN_START_EXTRA_WORDS 2 107 108 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; 109 struct CPUMIPSMVPContext { 110 int32_t CP0_MVPControl; 111 #define CP0MVPCo_CPA 3 112 #define CP0MVPCo_STLB 2 113 #define CP0MVPCo_VPC 1 114 #define CP0MVPCo_EVP 0 115 int32_t CP0_MVPConf0; 116 #define CP0MVPC0_M 31 117 #define CP0MVPC0_TLBS 29 118 #define CP0MVPC0_GS 28 119 #define CP0MVPC0_PCP 27 120 #define CP0MVPC0_PTLBE 16 121 #define CP0MVPC0_TCA 15 122 #define CP0MVPC0_PVPE 10 123 #define CP0MVPC0_PTC 0 124 int32_t CP0_MVPConf1; 125 #define CP0MVPC1_CIM 31 126 #define CP0MVPC1_CIF 30 127 #define CP0MVPC1_PCX 20 128 #define CP0MVPC1_PCP2 10 129 #define CP0MVPC1_PCP1 0 130 }; 131 132 typedef struct mips_def_t mips_def_t; 133 134 #define MIPS_SHADOW_SET_MAX 16 135 #define MIPS_TC_MAX 5 136 #define MIPS_FPU_MAX 1 137 #define MIPS_DSP_ACC 4 138 #define MIPS_KSCRATCH_NUM 6 139 #define MIPS_MAAR_MAX 16 /* Must be an even number. */ 140 141 142 /* 143 * Summary of CP0 registers 144 * ======================== 145 * 146 * 147 * Register 0 Register 1 Register 2 Register 3 148 * ---------- ---------- ---------- ---------- 149 * 150 * 0 Index Random EntryLo0 EntryLo1 151 * 1 MVPControl VPEControl TCStatus GlobalNumber 152 * 2 MVPConf0 VPEConf0 TCBind 153 * 3 MVPConf1 VPEConf1 TCRestart 154 * 4 VPControl YQMask TCHalt 155 * 5 VPESchedule TCContext 156 * 6 VPEScheFBack TCSchedule 157 * 7 VPEOpt TCScheFBack TCOpt 158 * 159 * 160 * Register 4 Register 5 Register 6 Register 7 161 * ---------- ---------- ---------- ---------- 162 * 163 * 0 Context PageMask Wired HWREna 164 * 1 ContextConfig PageGrain SRSConf0 165 * 2 UserLocal SegCtl0 SRSConf1 166 * 3 XContextConfig SegCtl1 SRSConf2 167 * 4 DebugContextID SegCtl2 SRSConf3 168 * 5 MemoryMapID PWBase SRSConf4 169 * 6 PWField PWCtl 170 * 7 PWSize 171 * 172 * 173 * Register 8 Register 9 Register 10 Register 11 174 * ---------- ---------- ----------- ----------- 175 * 176 * 0 BadVAddr Count EntryHi Compare 177 * 1 BadInstr 178 * 2 BadInstrP 179 * 3 BadInstrX 180 * 4 GuestCtl1 GuestCtl0Ext 181 * 5 GuestCtl2 182 * 6 SAARI GuestCtl3 183 * 7 SAAR 184 * 185 * 186 * Register 12 Register 13 Register 14 Register 15 187 * ----------- ----------- ----------- ----------- 188 * 189 * 0 Status Cause EPC PRId 190 * 1 IntCtl EBase 191 * 2 SRSCtl NestedEPC CDMMBase 192 * 3 SRSMap CMGCRBase 193 * 4 View_IPL View_RIPL BEVVA 194 * 5 SRSMap2 NestedExc 195 * 6 GuestCtl0 196 * 7 GTOffset 197 * 198 * 199 * Register 16 Register 17 Register 18 Register 19 200 * ----------- ----------- ----------- ----------- 201 * 202 * 0 Config LLAddr WatchLo WatchHi 203 * 1 Config1 MAAR WatchLo WatchHi 204 * 2 Config2 MAARI WatchLo WatchHi 205 * 3 Config3 WatchLo WatchHi 206 * 4 Config4 WatchLo WatchHi 207 * 5 Config5 WatchLo WatchHi 208 * 6 WatchLo WatchHi 209 * 7 WatchLo WatchHi 210 * 211 * 212 * Register 20 Register 21 Register 22 Register 23 213 * ----------- ----------- ----------- ----------- 214 * 215 * 0 XContext Debug 216 * 1 TraceControl 217 * 2 TraceControl2 218 * 3 UserTraceData1 219 * 4 TraceIBPC 220 * 5 TraceDBPC 221 * 6 Debug2 222 * 7 223 * 224 * 225 * Register 24 Register 25 Register 26 Register 27 226 * ----------- ----------- ----------- ----------- 227 * 228 * 0 DEPC PerfCnt ErrCtl CacheErr 229 * 1 PerfCnt 230 * 2 TraceControl3 PerfCnt 231 * 3 UserTraceData2 PerfCnt 232 * 4 PerfCnt 233 * 5 PerfCnt 234 * 6 PerfCnt 235 * 7 PerfCnt 236 * 237 * 238 * Register 28 Register 29 Register 30 Register 31 239 * ----------- ----------- ----------- ----------- 240 * 241 * 0 DataLo DataHi ErrorEPC DESAVE 242 * 1 TagLo TagHi 243 * 2 DataLo DataHi KScratch<n> 244 * 3 TagLo TagHi KScratch<n> 245 * 4 DataLo DataHi KScratch<n> 246 * 5 TagLo TagHi KScratch<n> 247 * 6 DataLo DataHi KScratch<n> 248 * 7 TagLo TagHi KScratch<n> 249 * 250 */ 251 #define CP0_REGISTER_00 0 252 #define CP0_REGISTER_01 1 253 #define CP0_REGISTER_02 2 254 #define CP0_REGISTER_03 3 255 #define CP0_REGISTER_04 4 256 #define CP0_REGISTER_05 5 257 #define CP0_REGISTER_06 6 258 #define CP0_REGISTER_07 7 259 #define CP0_REGISTER_08 8 260 #define CP0_REGISTER_09 9 261 #define CP0_REGISTER_10 10 262 #define CP0_REGISTER_11 11 263 #define CP0_REGISTER_12 12 264 #define CP0_REGISTER_13 13 265 #define CP0_REGISTER_14 14 266 #define CP0_REGISTER_15 15 267 #define CP0_REGISTER_16 16 268 #define CP0_REGISTER_17 17 269 #define CP0_REGISTER_18 18 270 #define CP0_REGISTER_19 19 271 #define CP0_REGISTER_20 20 272 #define CP0_REGISTER_21 21 273 #define CP0_REGISTER_22 22 274 #define CP0_REGISTER_23 23 275 #define CP0_REGISTER_24 24 276 #define CP0_REGISTER_25 25 277 #define CP0_REGISTER_26 26 278 #define CP0_REGISTER_27 27 279 #define CP0_REGISTER_28 28 280 #define CP0_REGISTER_29 29 281 #define CP0_REGISTER_30 30 282 #define CP0_REGISTER_31 31 283 284 285 /* CP0 Register 00 */ 286 #define CP0_REG00__INDEX 0 287 #define CP0_REG00__VPCONTROL 4 288 /* CP0 Register 01 */ 289 /* CP0 Register 02 */ 290 #define CP0_REG02__ENTRYLO0 0 291 /* CP0 Register 03 */ 292 #define CP0_REG03__ENTRYLO1 0 293 #define CP0_REG03__GLOBALNUM 1 294 /* CP0 Register 04 */ 295 #define CP0_REG04__CONTEXT 0 296 #define CP0_REG04__USERLOCAL 2 297 #define CP0_REG04__DBGCONTEXTID 4 298 #define CP0_REG00__MMID 5 299 /* CP0 Register 05 */ 300 #define CP0_REG05__PAGEMASK 0 301 #define CP0_REG05__PAGEGRAIN 1 302 /* CP0 Register 06 */ 303 #define CP0_REG06__WIRED 0 304 /* CP0 Register 07 */ 305 #define CP0_REG07__HWRENA 0 306 /* CP0 Register 08 */ 307 #define CP0_REG08__BADVADDR 0 308 #define CP0_REG08__BADINSTR 1 309 #define CP0_REG08__BADINSTRP 2 310 /* CP0 Register 09 */ 311 #define CP0_REG09__COUNT 0 312 #define CP0_REG09__SAARI 6 313 #define CP0_REG09__SAAR 7 314 /* CP0 Register 10 */ 315 #define CP0_REG10__ENTRYHI 0 316 #define CP0_REG10__GUESTCTL1 4 317 #define CP0_REG10__GUESTCTL2 5 318 /* CP0 Register 11 */ 319 #define CP0_REG11__COMPARE 0 320 #define CP0_REG11__GUESTCTL0EXT 4 321 /* CP0 Register 12 */ 322 #define CP0_REG12__STATUS 0 323 #define CP0_REG12__INTCTL 1 324 #define CP0_REG12__SRSCTL 2 325 #define CP0_REG12__GUESTCTL0 6 326 #define CP0_REG12__GTOFFSET 7 327 /* CP0 Register 13 */ 328 #define CP0_REG13__CAUSE 0 329 /* CP0 Register 14 */ 330 #define CP0_REG14__EPC 0 331 /* CP0 Register 15 */ 332 #define CP0_REG15__PRID 0 333 #define CP0_REG15__EBASE 1 334 #define CP0_REG15__CDMMBASE 2 335 #define CP0_REG15__CMGCRBASE 3 336 /* CP0 Register 16 */ 337 #define CP0_REG16__CONFIG 0 338 #define CP0_REG16__CONFIG1 1 339 #define CP0_REG16__CONFIG2 2 340 #define CP0_REG16__CONFIG3 3 341 #define CP0_REG16__CONFIG4 4 342 #define CP0_REG16__CONFIG5 5 343 #define CP0_REG00__CONFIG7 7 344 /* CP0 Register 17 */ 345 #define CP0_REG17__LLADDR 0 346 #define CP0_REG17__MAAR 1 347 #define CP0_REG17__MAARI 2 348 /* CP0 Register 18 */ 349 #define CP0_REG18__WATCHLO0 0 350 #define CP0_REG18__WATCHLO1 1 351 #define CP0_REG18__WATCHLO2 2 352 #define CP0_REG18__WATCHLO3 3 353 /* CP0 Register 19 */ 354 #define CP0_REG19__WATCHHI0 0 355 #define CP0_REG19__WATCHHI1 1 356 #define CP0_REG19__WATCHHI2 2 357 #define CP0_REG19__WATCHHI3 3 358 /* CP0 Register 20 */ 359 #define CP0_REG20__XCONTEXT 0 360 /* CP0 Register 21 */ 361 /* CP0 Register 22 */ 362 /* CP0 Register 23 */ 363 #define CP0_REG23__DEBUG 0 364 /* CP0 Register 24 */ 365 #define CP0_REG24__DEPC 0 366 /* CP0 Register 25 */ 367 #define CP0_REG25__PERFCTL0 0 368 #define CP0_REG25__PERFCNT0 1 369 #define CP0_REG25__PERFCTL1 2 370 #define CP0_REG25__PERFCNT1 3 371 #define CP0_REG25__PERFCTL2 4 372 #define CP0_REG25__PERFCNT2 5 373 #define CP0_REG25__PERFCTL3 6 374 #define CP0_REG25__PERFCNT3 7 375 /* CP0 Register 26 */ 376 #define CP0_REG00__ERRCTL 0 377 /* CP0 Register 27 */ 378 #define CP0_REG27__CACHERR 0 379 /* CP0 Register 28 */ 380 #define CP0_REG28__ITAGLO 0 381 #define CP0_REG28__IDATALO 1 382 #define CP0_REG28__DTAGLO 2 383 #define CP0_REG28__DDATALO 3 384 /* CP0 Register 29 */ 385 #define CP0_REG29__IDATAHI 1 386 #define CP0_REG29__DDATAHI 3 387 /* CP0 Register 30 */ 388 #define CP0_REG30__ERROREPC 0 389 /* CP0 Register 31 */ 390 #define CP0_REG31__DESAVE 0 391 #define CP0_REG31__KSCRATCH1 2 392 #define CP0_REG31__KSCRATCH2 3 393 #define CP0_REG31__KSCRATCH3 4 394 #define CP0_REG31__KSCRATCH4 5 395 #define CP0_REG31__KSCRATCH5 6 396 #define CP0_REG31__KSCRATCH6 7 397 398 399 typedef struct TCState TCState; 400 struct TCState { 401 target_ulong gpr[32]; 402 target_ulong PC; 403 target_ulong HI[MIPS_DSP_ACC]; 404 target_ulong LO[MIPS_DSP_ACC]; 405 target_ulong ACX[MIPS_DSP_ACC]; 406 target_ulong DSPControl; 407 int32_t CP0_TCStatus; 408 #define CP0TCSt_TCU3 31 409 #define CP0TCSt_TCU2 30 410 #define CP0TCSt_TCU1 29 411 #define CP0TCSt_TCU0 28 412 #define CP0TCSt_TMX 27 413 #define CP0TCSt_RNST 23 414 #define CP0TCSt_TDS 21 415 #define CP0TCSt_DT 20 416 #define CP0TCSt_DA 15 417 #define CP0TCSt_A 13 418 #define CP0TCSt_TKSU 11 419 #define CP0TCSt_IXMT 10 420 #define CP0TCSt_TASID 0 421 int32_t CP0_TCBind; 422 #define CP0TCBd_CurTC 21 423 #define CP0TCBd_TBE 17 424 #define CP0TCBd_CurVPE 0 425 target_ulong CP0_TCHalt; 426 target_ulong CP0_TCContext; 427 target_ulong CP0_TCSchedule; 428 target_ulong CP0_TCScheFBack; 429 int32_t CP0_Debug_tcstatus; 430 target_ulong CP0_UserLocal; 431 432 int32_t msacsr; 433 434 #define MSACSR_FS 24 435 #define MSACSR_FS_MASK (1 << MSACSR_FS) 436 #define MSACSR_NX 18 437 #define MSACSR_NX_MASK (1 << MSACSR_NX) 438 #define MSACSR_CEF 2 439 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF) 440 #define MSACSR_RM 0 441 #define MSACSR_RM_MASK (0x3 << MSACSR_RM) 442 #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \ 443 MSACSR_FS_MASK) 444 445 float_status msa_fp_status; 446 447 /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */ 448 uint64_t mmr[32]; 449 450 #define NUMBER_OF_MXU_REGISTERS 16 451 target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; 452 target_ulong mxu_cr; 453 #define MXU_CR_LC 31 454 #define MXU_CR_RC 30 455 #define MXU_CR_BIAS 2 456 #define MXU_CR_RD_EN 1 457 #define MXU_CR_MXU_EN 0 458 459 }; 460 461 struct MIPSITUState; 462 typedef struct CPUMIPSState CPUMIPSState; 463 struct CPUMIPSState { 464 TCState active_tc; 465 CPUMIPSFPUContext active_fpu; 466 467 uint32_t current_tc; 468 uint32_t current_fpu; 469 470 uint32_t SEGBITS; 471 uint32_t PABITS; 472 #if defined(TARGET_MIPS64) 473 # define PABITS_BASE 36 474 #else 475 # define PABITS_BASE 32 476 #endif 477 target_ulong SEGMask; 478 uint64_t PAMask; 479 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1) 480 481 int32_t msair; 482 #define MSAIR_ProcID 8 483 #define MSAIR_Rev 0 484 485 /* 486 * CP0 Register 0 487 */ 488 int32_t CP0_Index; 489 /* CP0_MVP* are per MVP registers. */ 490 int32_t CP0_VPControl; 491 #define CP0VPCtl_DIS 0 492 /* 493 * CP0 Register 1 494 */ 495 int32_t CP0_Random; 496 int32_t CP0_VPEControl; 497 #define CP0VPECo_YSI 21 498 #define CP0VPECo_GSI 20 499 #define CP0VPECo_EXCPT 16 500 #define CP0VPECo_TE 15 501 #define CP0VPECo_TargTC 0 502 int32_t CP0_VPEConf0; 503 #define CP0VPEC0_M 31 504 #define CP0VPEC0_XTC 21 505 #define CP0VPEC0_TCS 19 506 #define CP0VPEC0_SCS 18 507 #define CP0VPEC0_DSC 17 508 #define CP0VPEC0_ICS 16 509 #define CP0VPEC0_MVP 1 510 #define CP0VPEC0_VPA 0 511 int32_t CP0_VPEConf1; 512 #define CP0VPEC1_NCX 20 513 #define CP0VPEC1_NCP2 10 514 #define CP0VPEC1_NCP1 0 515 target_ulong CP0_YQMask; 516 target_ulong CP0_VPESchedule; 517 target_ulong CP0_VPEScheFBack; 518 int32_t CP0_VPEOpt; 519 #define CP0VPEOpt_IWX7 15 520 #define CP0VPEOpt_IWX6 14 521 #define CP0VPEOpt_IWX5 13 522 #define CP0VPEOpt_IWX4 12 523 #define CP0VPEOpt_IWX3 11 524 #define CP0VPEOpt_IWX2 10 525 #define CP0VPEOpt_IWX1 9 526 #define CP0VPEOpt_IWX0 8 527 #define CP0VPEOpt_DWX7 7 528 #define CP0VPEOpt_DWX6 6 529 #define CP0VPEOpt_DWX5 5 530 #define CP0VPEOpt_DWX4 4 531 #define CP0VPEOpt_DWX3 3 532 #define CP0VPEOpt_DWX2 2 533 #define CP0VPEOpt_DWX1 1 534 #define CP0VPEOpt_DWX0 0 535 /* 536 * CP0 Register 2 537 */ 538 uint64_t CP0_EntryLo0; 539 /* 540 * CP0 Register 3 541 */ 542 uint64_t CP0_EntryLo1; 543 #if defined(TARGET_MIPS64) 544 # define CP0EnLo_RI 63 545 # define CP0EnLo_XI 62 546 #else 547 # define CP0EnLo_RI 31 548 # define CP0EnLo_XI 30 549 #endif 550 int32_t CP0_GlobalNumber; 551 #define CP0GN_VPId 0 552 /* 553 * CP0 Register 4 554 */ 555 target_ulong CP0_Context; 556 target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; 557 int32_t CP0_MemoryMapID; 558 /* 559 * CP0 Register 5 560 */ 561 int32_t CP0_PageMask; 562 int32_t CP0_PageGrain_rw_bitmask; 563 int32_t CP0_PageGrain; 564 #define CP0PG_RIE 31 565 #define CP0PG_XIE 30 566 #define CP0PG_ELPA 29 567 #define CP0PG_IEC 27 568 target_ulong CP0_SegCtl0; 569 target_ulong CP0_SegCtl1; 570 target_ulong CP0_SegCtl2; 571 #define CP0SC_PA 9 572 #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA) 573 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA) 574 #define CP0SC_AM 4 575 #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM) 576 #define CP0SC_AM_UK 0ULL 577 #define CP0SC_AM_MK 1ULL 578 #define CP0SC_AM_MSK 2ULL 579 #define CP0SC_AM_MUSK 3ULL 580 #define CP0SC_AM_MUSUK 4ULL 581 #define CP0SC_AM_USK 5ULL 582 #define CP0SC_AM_UUSK 7ULL 583 #define CP0SC_EU 3 584 #define CP0SC_EU_MASK (1ULL << CP0SC_EU) 585 #define CP0SC_C 0 586 #define CP0SC_C_MASK (0x7ULL << CP0SC_C) 587 #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ 588 CP0SC_PA_MASK) 589 #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ 590 CP0SC_PA_1GMASK) 591 #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16)) 592 #define CP0SC1_XAM 59 593 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM) 594 #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK) 595 #define CP0SC2_XR 56 596 #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR) 597 #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK) 598 target_ulong CP0_PWBase; 599 target_ulong CP0_PWField; 600 #if defined(TARGET_MIPS64) 601 #define CP0PF_BDI 32 /* 37..32 */ 602 #define CP0PF_GDI 24 /* 29..24 */ 603 #define CP0PF_UDI 18 /* 23..18 */ 604 #define CP0PF_MDI 12 /* 17..12 */ 605 #define CP0PF_PTI 6 /* 11..6 */ 606 #define CP0PF_PTEI 0 /* 5..0 */ 607 #else 608 #define CP0PF_GDW 24 /* 29..24 */ 609 #define CP0PF_UDW 18 /* 23..18 */ 610 #define CP0PF_MDW 12 /* 17..12 */ 611 #define CP0PF_PTW 6 /* 11..6 */ 612 #define CP0PF_PTEW 0 /* 5..0 */ 613 #endif 614 target_ulong CP0_PWSize; 615 #if defined(TARGET_MIPS64) 616 #define CP0PS_BDW 32 /* 37..32 */ 617 #endif 618 #define CP0PS_PS 30 619 #define CP0PS_GDW 24 /* 29..24 */ 620 #define CP0PS_UDW 18 /* 23..18 */ 621 #define CP0PS_MDW 12 /* 17..12 */ 622 #define CP0PS_PTW 6 /* 11..6 */ 623 #define CP0PS_PTEW 0 /* 5..0 */ 624 /* 625 * CP0 Register 6 626 */ 627 int32_t CP0_Wired; 628 int32_t CP0_PWCtl; 629 #define CP0PC_PWEN 31 630 #if defined(TARGET_MIPS64) 631 #define CP0PC_PWDIREXT 30 632 #define CP0PC_XK 28 633 #define CP0PC_XS 27 634 #define CP0PC_XU 26 635 #endif 636 #define CP0PC_DPH 7 637 #define CP0PC_HUGEPG 6 638 #define CP0PC_PSN 0 /* 5..0 */ 639 int32_t CP0_SRSConf0_rw_bitmask; 640 int32_t CP0_SRSConf0; 641 #define CP0SRSC0_M 31 642 #define CP0SRSC0_SRS3 20 643 #define CP0SRSC0_SRS2 10 644 #define CP0SRSC0_SRS1 0 645 int32_t CP0_SRSConf1_rw_bitmask; 646 int32_t CP0_SRSConf1; 647 #define CP0SRSC1_M 31 648 #define CP0SRSC1_SRS6 20 649 #define CP0SRSC1_SRS5 10 650 #define CP0SRSC1_SRS4 0 651 int32_t CP0_SRSConf2_rw_bitmask; 652 int32_t CP0_SRSConf2; 653 #define CP0SRSC2_M 31 654 #define CP0SRSC2_SRS9 20 655 #define CP0SRSC2_SRS8 10 656 #define CP0SRSC2_SRS7 0 657 int32_t CP0_SRSConf3_rw_bitmask; 658 int32_t CP0_SRSConf3; 659 #define CP0SRSC3_M 31 660 #define CP0SRSC3_SRS12 20 661 #define CP0SRSC3_SRS11 10 662 #define CP0SRSC3_SRS10 0 663 int32_t CP0_SRSConf4_rw_bitmask; 664 int32_t CP0_SRSConf4; 665 #define CP0SRSC4_SRS15 20 666 #define CP0SRSC4_SRS14 10 667 #define CP0SRSC4_SRS13 0 668 /* 669 * CP0 Register 7 670 */ 671 int32_t CP0_HWREna; 672 /* 673 * CP0 Register 8 674 */ 675 target_ulong CP0_BadVAddr; 676 uint32_t CP0_BadInstr; 677 uint32_t CP0_BadInstrP; 678 uint32_t CP0_BadInstrX; 679 /* 680 * CP0 Register 9 681 */ 682 int32_t CP0_Count; 683 uint32_t CP0_SAARI; 684 #define CP0SAARI_TARGET 0 /* 5..0 */ 685 uint64_t CP0_SAAR[2]; 686 #define CP0SAAR_BASE 12 /* 43..12 */ 687 #define CP0SAAR_SIZE 1 /* 5..1 */ 688 #define CP0SAAR_EN 0 689 /* 690 * CP0 Register 10 691 */ 692 target_ulong CP0_EntryHi; 693 #define CP0EnHi_EHINV 10 694 target_ulong CP0_EntryHi_ASID_mask; 695 /* 696 * CP0 Register 11 697 */ 698 int32_t CP0_Compare; 699 /* 700 * CP0 Register 12 701 */ 702 int32_t CP0_Status; 703 #define CP0St_CU3 31 704 #define CP0St_CU2 30 705 #define CP0St_CU1 29 706 #define CP0St_CU0 28 707 #define CP0St_RP 27 708 #define CP0St_FR 26 709 #define CP0St_RE 25 710 #define CP0St_MX 24 711 #define CP0St_PX 23 712 #define CP0St_BEV 22 713 #define CP0St_TS 21 714 #define CP0St_SR 20 715 #define CP0St_NMI 19 716 #define CP0St_IM 8 717 #define CP0St_KX 7 718 #define CP0St_SX 6 719 #define CP0St_UX 5 720 #define CP0St_KSU 3 721 #define CP0St_ERL 2 722 #define CP0St_EXL 1 723 #define CP0St_IE 0 724 int32_t CP0_IntCtl; 725 #define CP0IntCtl_IPTI 29 726 #define CP0IntCtl_IPPCI 26 727 #define CP0IntCtl_VS 5 728 int32_t CP0_SRSCtl; 729 #define CP0SRSCtl_HSS 26 730 #define CP0SRSCtl_EICSS 18 731 #define CP0SRSCtl_ESS 12 732 #define CP0SRSCtl_PSS 6 733 #define CP0SRSCtl_CSS 0 734 int32_t CP0_SRSMap; 735 #define CP0SRSMap_SSV7 28 736 #define CP0SRSMap_SSV6 24 737 #define CP0SRSMap_SSV5 20 738 #define CP0SRSMap_SSV4 16 739 #define CP0SRSMap_SSV3 12 740 #define CP0SRSMap_SSV2 8 741 #define CP0SRSMap_SSV1 4 742 #define CP0SRSMap_SSV0 0 743 /* 744 * CP0 Register 13 745 */ 746 int32_t CP0_Cause; 747 #define CP0Ca_BD 31 748 #define CP0Ca_TI 30 749 #define CP0Ca_CE 28 750 #define CP0Ca_DC 27 751 #define CP0Ca_PCI 26 752 #define CP0Ca_IV 23 753 #define CP0Ca_WP 22 754 #define CP0Ca_IP 8 755 #define CP0Ca_IP_mask 0x0000FF00 756 #define CP0Ca_EC 2 757 /* 758 * CP0 Register 14 759 */ 760 target_ulong CP0_EPC; 761 /* 762 * CP0 Register 15 763 */ 764 int32_t CP0_PRid; 765 target_ulong CP0_EBase; 766 target_ulong CP0_EBaseWG_rw_bitmask; 767 #define CP0EBase_WG 11 768 target_ulong CP0_CMGCRBase; 769 /* 770 * CP0 Register 16 771 */ 772 int32_t CP0_Config0; 773 #define CP0C0_M 31 774 #define CP0C0_K23 28 /* 30..28 */ 775 #define CP0C0_KU 25 /* 27..25 */ 776 #define CP0C0_MDU 20 777 #define CP0C0_MM 18 778 #define CP0C0_BM 16 779 #define CP0C0_Impl 16 /* 24..16 */ 780 #define CP0C0_BE 15 781 #define CP0C0_AT 13 /* 14..13 */ 782 #define CP0C0_AR 10 /* 12..10 */ 783 #define CP0C0_MT 7 /* 9..7 */ 784 #define CP0C0_VI 3 785 #define CP0C0_K0 0 /* 2..0 */ 786 int32_t CP0_Config1; 787 #define CP0C1_M 31 788 #define CP0C1_MMU 25 /* 30..25 */ 789 #define CP0C1_IS 22 /* 24..22 */ 790 #define CP0C1_IL 19 /* 21..19 */ 791 #define CP0C1_IA 16 /* 18..16 */ 792 #define CP0C1_DS 13 /* 15..13 */ 793 #define CP0C1_DL 10 /* 12..10 */ 794 #define CP0C1_DA 7 /* 9..7 */ 795 #define CP0C1_C2 6 796 #define CP0C1_MD 5 797 #define CP0C1_PC 4 798 #define CP0C1_WR 3 799 #define CP0C1_CA 2 800 #define CP0C1_EP 1 801 #define CP0C1_FP 0 802 int32_t CP0_Config2; 803 #define CP0C2_M 31 804 #define CP0C2_TU 28 /* 30..28 */ 805 #define CP0C2_TS 24 /* 27..24 */ 806 #define CP0C2_TL 20 /* 23..20 */ 807 #define CP0C2_TA 16 /* 19..16 */ 808 #define CP0C2_SU 12 /* 15..12 */ 809 #define CP0C2_SS 8 /* 11..8 */ 810 #define CP0C2_SL 4 /* 7..4 */ 811 #define CP0C2_SA 0 /* 3..0 */ 812 int32_t CP0_Config3; 813 #define CP0C3_M 31 814 #define CP0C3_BPG 30 815 #define CP0C3_CMGCR 29 816 #define CP0C3_MSAP 28 817 #define CP0C3_BP 27 818 #define CP0C3_BI 26 819 #define CP0C3_SC 25 820 #define CP0C3_PW 24 821 #define CP0C3_VZ 23 822 #define CP0C3_IPLV 21 /* 22..21 */ 823 #define CP0C3_MMAR 18 /* 20..18 */ 824 #define CP0C3_MCU 17 825 #define CP0C3_ISA_ON_EXC 16 826 #define CP0C3_ISA 14 /* 15..14 */ 827 #define CP0C3_ULRI 13 828 #define CP0C3_RXI 12 829 #define CP0C3_DSP2P 11 830 #define CP0C3_DSPP 10 831 #define CP0C3_CTXTC 9 832 #define CP0C3_ITL 8 833 #define CP0C3_LPA 7 834 #define CP0C3_VEIC 6 835 #define CP0C3_VInt 5 836 #define CP0C3_SP 4 837 #define CP0C3_CDMM 3 838 #define CP0C3_MT 2 839 #define CP0C3_SM 1 840 #define CP0C3_TL 0 841 int32_t CP0_Config4; 842 int32_t CP0_Config4_rw_bitmask; 843 #define CP0C4_M 31 844 #define CP0C4_IE 29 /* 30..29 */ 845 #define CP0C4_AE 28 846 #define CP0C4_VTLBSizeExt 24 /* 27..24 */ 847 #define CP0C4_KScrExist 16 848 #define CP0C4_MMUExtDef 14 849 #define CP0C4_FTLBPageSize 8 /* 12..8 */ 850 /* bit layout if MMUExtDef=1 */ 851 #define CP0C4_MMUSizeExt 0 /* 7..0 */ 852 /* bit layout if MMUExtDef=2 */ 853 #define CP0C4_FTLBWays 4 /* 7..4 */ 854 #define CP0C4_FTLBSets 0 /* 3..0 */ 855 int32_t CP0_Config5; 856 int32_t CP0_Config5_rw_bitmask; 857 #define CP0C5_M 31 858 #define CP0C5_K 30 859 #define CP0C5_CV 29 860 #define CP0C5_EVA 28 861 #define CP0C5_MSAEn 27 862 #define CP0C5_PMJ 23 /* 25..23 */ 863 #define CP0C5_WR2 22 864 #define CP0C5_NMS 21 865 #define CP0C5_ULS 20 866 #define CP0C5_XPA 19 867 #define CP0C5_CRCP 18 868 #define CP0C5_MI 17 869 #define CP0C5_GI 15 /* 16..15 */ 870 #define CP0C5_CA2 14 871 #define CP0C5_XNP 13 872 #define CP0C5_DEC 11 873 #define CP0C5_L2C 10 874 #define CP0C5_UFE 9 875 #define CP0C5_FRE 8 876 #define CP0C5_VP 7 877 #define CP0C5_SBRI 6 878 #define CP0C5_MVH 5 879 #define CP0C5_LLB 4 880 #define CP0C5_MRP 3 881 #define CP0C5_UFR 2 882 #define CP0C5_NFExists 0 883 int32_t CP0_Config6; 884 int32_t CP0_Config7; 885 uint64_t CP0_LLAddr; 886 uint64_t CP0_MAAR[MIPS_MAAR_MAX]; 887 int32_t CP0_MAARI; 888 /* XXX: Maybe make LLAddr per-TC? */ 889 /* 890 * CP0 Register 17 891 */ 892 target_ulong lladdr; /* LL virtual address compared against SC */ 893 target_ulong llval; 894 uint64_t llval_wp; 895 uint32_t llnewval_wp; 896 uint64_t CP0_LLAddr_rw_bitmask; 897 int CP0_LLAddr_shift; 898 /* 899 * CP0 Register 18 900 */ 901 target_ulong CP0_WatchLo[8]; 902 /* 903 * CP0 Register 19 904 */ 905 int32_t CP0_WatchHi[8]; 906 #define CP0WH_ASID 16 907 /* 908 * CP0 Register 20 909 */ 910 target_ulong CP0_XContext; 911 int32_t CP0_Framemask; 912 /* 913 * CP0 Register 23 914 */ 915 int32_t CP0_Debug; 916 #define CP0DB_DBD 31 917 #define CP0DB_DM 30 918 #define CP0DB_LSNM 28 919 #define CP0DB_Doze 27 920 #define CP0DB_Halt 26 921 #define CP0DB_CNT 25 922 #define CP0DB_IBEP 24 923 #define CP0DB_DBEP 21 924 #define CP0DB_IEXI 20 925 #define CP0DB_VER 15 926 #define CP0DB_DEC 10 927 #define CP0DB_SSt 8 928 #define CP0DB_DINT 5 929 #define CP0DB_DIB 4 930 #define CP0DB_DDBS 3 931 #define CP0DB_DDBL 2 932 #define CP0DB_DBp 1 933 #define CP0DB_DSS 0 934 /* 935 * CP0 Register 24 936 */ 937 target_ulong CP0_DEPC; 938 /* 939 * CP0 Register 25 940 */ 941 int32_t CP0_Performance0; 942 /* 943 * CP0 Register 26 944 */ 945 int32_t CP0_ErrCtl; 946 #define CP0EC_WST 29 947 #define CP0EC_SPR 28 948 #define CP0EC_ITC 26 949 /* 950 * CP0 Register 28 951 */ 952 uint64_t CP0_TagLo; 953 int32_t CP0_DataLo; 954 /* 955 * CP0 Register 29 956 */ 957 int32_t CP0_TagHi; 958 int32_t CP0_DataHi; 959 /* 960 * CP0 Register 30 961 */ 962 target_ulong CP0_ErrorEPC; 963 /* 964 * CP0 Register 31 965 */ 966 int32_t CP0_DESAVE; 967 968 /* We waste some space so we can handle shadow registers like TCs. */ 969 TCState tcs[MIPS_SHADOW_SET_MAX]; 970 CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; 971 /* QEMU */ 972 int error_code; 973 #define EXCP_TLB_NOMATCH 0x1 974 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ 975 uint32_t hflags; /* CPU State */ 976 /* TMASK defines different execution modes */ 977 #define MIPS_HFLAG_TMASK 0x1F5807FF 978 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ 979 /* 980 * The KSU flags must be the lowest bits in hflags. The flag order 981 * must be the same as defined for CP0 Status. This allows to use 982 * the bits as the value of mmu_idx. 983 */ 984 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ 985 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ 986 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ 987 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ 988 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ 989 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ 990 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ 991 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ 992 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ 993 /* 994 * True if the MIPS IV COP1X instructions can be used. This also 995 * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S 996 * and RSQRT.D. 997 */ 998 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ 999 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ 1000 #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ 1001 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ 1002 #define MIPS_HFLAG_M16_SHIFT 10 1003 /* 1004 * If translation is interrupted between the branch instruction and 1005 * the delay slot, record what type of branch it is so that we can 1006 * resume translation properly. It might be possible to reduce 1007 * this from three bits to two. 1008 */ 1009 #define MIPS_HFLAG_BMASK_BASE 0x803800 1010 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ 1011 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ 1012 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ 1013 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ 1014 /* Extra flags about the current pending branch. */ 1015 #define MIPS_HFLAG_BMASK_EXT 0x7C000 1016 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ 1017 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ 1018 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ 1019 #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */ 1020 #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */ 1021 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) 1022 /* MIPS DSP resources access. */ 1023 #define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */ 1024 #define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */ 1025 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */ 1026 /* Extra flag about HWREna register. */ 1027 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ 1028 #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */ 1029 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */ 1030 #define MIPS_HFLAG_MSA 0x1000000 1031 #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */ 1032 #define MIPS_HFLAG_ELPA 0x4000000 1033 #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */ 1034 #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */ 1035 target_ulong btarget; /* Jump / branch target */ 1036 target_ulong bcond; /* Branch condition (if needed) */ 1037 1038 int SYNCI_Step; /* Address step size for SYNCI */ 1039 int CCRes; /* Cycle count resolution/divisor */ 1040 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ 1041 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ 1042 uint64_t insn_flags; /* Supported instruction set */ 1043 int saarp; 1044 1045 /* Fields up to this point are cleared by a CPU reset */ 1046 struct {} end_reset_fields; 1047 1048 CPU_COMMON 1049 1050 /* Fields from here on are preserved across CPU reset. */ 1051 CPUMIPSMVPContext *mvp; 1052 #if !defined(CONFIG_USER_ONLY) 1053 CPUMIPSTLBContext *tlb; 1054 #endif 1055 1056 const mips_def_t *cpu_model; 1057 void *irq[8]; 1058 QEMUTimer *timer; /* Internal timer */ 1059 struct MIPSITUState *itu; 1060 MemoryRegion *itc_tag; /* ITC Configuration Tags */ 1061 target_ulong exception_base; /* ExceptionBase input to the core */ 1062 }; 1063 1064 /** 1065 * MIPSCPU: 1066 * @env: #CPUMIPSState 1067 * 1068 * A MIPS CPU. 1069 */ 1070 struct MIPSCPU { 1071 /*< private >*/ 1072 CPUState parent_obj; 1073 /*< public >*/ 1074 1075 CPUMIPSState env; 1076 }; 1077 1078 static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) 1079 { 1080 return container_of(env, MIPSCPU, env); 1081 } 1082 1083 #define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e)) 1084 1085 #define ENV_OFFSET offsetof(MIPSCPU, env) 1086 1087 void mips_cpu_list(void); 1088 1089 #define cpu_signal_handler cpu_mips_signal_handler 1090 #define cpu_list mips_cpu_list 1091 1092 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); 1093 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); 1094 1095 /* 1096 * MMU modes definitions. We carefully match the indices with our 1097 * hflags layout. 1098 */ 1099 #define MMU_MODE0_SUFFIX _kernel 1100 #define MMU_MODE1_SUFFIX _super 1101 #define MMU_MODE2_SUFFIX _user 1102 #define MMU_MODE3_SUFFIX _error 1103 #define MMU_USER_IDX 2 1104 1105 static inline int hflags_mmu_index(uint32_t hflags) 1106 { 1107 if (hflags & MIPS_HFLAG_ERL) { 1108 return 3; /* ERL */ 1109 } else { 1110 return hflags & MIPS_HFLAG_KSU; 1111 } 1112 } 1113 1114 static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) 1115 { 1116 return hflags_mmu_index(env->hflags); 1117 } 1118 1119 #include "exec/cpu-all.h" 1120 1121 /* 1122 * Memory access type : 1123 * may be needed for precise access rights control and precise exceptions. 1124 */ 1125 enum { 1126 /* 1 bit to define user level / supervisor access */ 1127 ACCESS_USER = 0x00, 1128 ACCESS_SUPER = 0x01, 1129 /* 1 bit to indicate direction */ 1130 ACCESS_STORE = 0x02, 1131 /* Type of instruction that generated the access */ 1132 ACCESS_CODE = 0x10, /* Code fetch access */ 1133 ACCESS_INT = 0x20, /* Integer load/store access */ 1134 ACCESS_FLOAT = 0x30, /* floating point load/store access */ 1135 }; 1136 1137 /* Exceptions */ 1138 enum { 1139 EXCP_NONE = -1, 1140 EXCP_RESET = 0, 1141 EXCP_SRESET, 1142 EXCP_DSS, 1143 EXCP_DINT, 1144 EXCP_DDBL, 1145 EXCP_DDBS, 1146 EXCP_NMI, 1147 EXCP_MCHECK, 1148 EXCP_EXT_INTERRUPT, /* 8 */ 1149 EXCP_DFWATCH, 1150 EXCP_DIB, 1151 EXCP_IWATCH, 1152 EXCP_AdEL, 1153 EXCP_AdES, 1154 EXCP_TLBF, 1155 EXCP_IBE, 1156 EXCP_DBp, /* 16 */ 1157 EXCP_SYSCALL, 1158 EXCP_BREAK, 1159 EXCP_CpU, 1160 EXCP_RI, 1161 EXCP_OVERFLOW, 1162 EXCP_TRAP, 1163 EXCP_FPE, 1164 EXCP_DWATCH, /* 24 */ 1165 EXCP_LTLBL, 1166 EXCP_TLBL, 1167 EXCP_TLBS, 1168 EXCP_DBE, 1169 EXCP_THREAD, 1170 EXCP_MDMX, 1171 EXCP_C2E, 1172 EXCP_CACHE, /* 32 */ 1173 EXCP_DSPDIS, 1174 EXCP_MSADIS, 1175 EXCP_MSAFPE, 1176 EXCP_TLBXI, 1177 EXCP_TLBRI, 1178 1179 EXCP_LAST = EXCP_TLBRI, 1180 }; 1181 1182 /* 1183 * This is an internally generated WAKE request line. 1184 * It is driven by the CPU itself. Raised when the MT 1185 * block wants to wake a VPE from an inactive state and 1186 * cleared when VPE goes from active to inactive. 1187 */ 1188 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 1189 1190 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); 1191 1192 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU 1193 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX 1194 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU 1195 1196 bool cpu_supports_cps_smp(const char *cpu_type); 1197 bool cpu_supports_isa(const char *cpu_type, uint64_t isa); 1198 void cpu_set_exception_base(int vp_index, target_ulong address); 1199 1200 /* mips_int.c */ 1201 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); 1202 1203 /* mips_itu.c */ 1204 void itc_reconfigure(struct MIPSITUState *tag); 1205 1206 /* helper.c */ 1207 target_ulong exception_resume_pc(CPUMIPSState *env); 1208 1209 static inline void restore_snan_bit_mode(CPUMIPSState *env) 1210 { 1211 set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, 1212 &env->active_fpu.fp_status); 1213 } 1214 1215 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, 1216 target_ulong *cs_base, uint32_t *flags) 1217 { 1218 *pc = env->active_tc.PC; 1219 *cs_base = 0; 1220 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | 1221 MIPS_HFLAG_HWRENA_ULR); 1222 } 1223 1224 #endif /* MIPS_CPU_H */ 1225