1 #ifndef MIPS_CPU_H 2 #define MIPS_CPU_H 3 4 #define ALIGNED_ONLY 5 6 #define CPUArchState struct CPUMIPSState 7 8 #include "qemu-common.h" 9 #include "cpu-qom.h" 10 #include "mips-defs.h" 11 #include "exec/cpu-defs.h" 12 #include "fpu/softfloat.h" 13 14 #define TCG_GUEST_DEFAULT_MO (0) 15 16 struct CPUMIPSState; 17 18 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; 19 20 /* MSA Context */ 21 #define MSA_WRLEN (128) 22 23 typedef union wr_t wr_t; 24 union wr_t { 25 int8_t b[MSA_WRLEN / 8]; 26 int16_t h[MSA_WRLEN / 16]; 27 int32_t w[MSA_WRLEN / 32]; 28 int64_t d[MSA_WRLEN / 64]; 29 }; 30 31 typedef union fpr_t fpr_t; 32 union fpr_t { 33 float64 fd; /* ieee double precision */ 34 float32 fs[2];/* ieee single precision */ 35 uint64_t d; /* binary double fixed-point */ 36 uint32_t w[2]; /* binary single fixed-point */ 37 /* FPU/MSA register mapping is not tested on big-endian hosts. */ 38 wr_t wr; /* vector data */ 39 }; 40 /* 41 *define FP_ENDIAN_IDX to access the same location 42 * in the fpr_t union regardless of the host endianness 43 */ 44 #if defined(HOST_WORDS_BIGENDIAN) 45 # define FP_ENDIAN_IDX 1 46 #else 47 # define FP_ENDIAN_IDX 0 48 #endif 49 50 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; 51 struct CPUMIPSFPUContext { 52 /* Floating point registers */ 53 fpr_t fpr[32]; 54 float_status fp_status; 55 /* fpu implementation/revision register (fir) */ 56 uint32_t fcr0; 57 #define FCR0_FREP 29 58 #define FCR0_UFRP 28 59 #define FCR0_HAS2008 23 60 #define FCR0_F64 22 61 #define FCR0_L 21 62 #define FCR0_W 20 63 #define FCR0_3D 19 64 #define FCR0_PS 18 65 #define FCR0_D 17 66 #define FCR0_S 16 67 #define FCR0_PRID 8 68 #define FCR0_REV 0 69 /* fcsr */ 70 uint32_t fcr31_rw_bitmask; 71 uint32_t fcr31; 72 #define FCR31_FS 24 73 #define FCR31_ABS2008 19 74 #define FCR31_NAN2008 18 75 #define SET_FP_COND(num, env) do { ((env).fcr31) |= \ 76 ((num) ? (1 << ((num) + 24)) : \ 77 (1 << 23)); \ 78 } while (0) 79 #define CLEAR_FP_COND(num, env) do { ((env).fcr31) &= \ 80 ~((num) ? (1 << ((num) + 24)) : \ 81 (1 << 23)); \ 82 } while (0) 83 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \ 84 (((env).fcr31 >> 23) & 0x1)) 85 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) 86 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 87 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) 88 #define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \ 89 ((v & 0x3f) << 12); \ 90 } while (0) 91 #define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \ 92 ((v & 0x1f) << 7); \ 93 } while (0) 94 #define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 2)) | \ 95 ((v & 0x1f) << 2); \ 96 } while (0) 97 #define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 2); } while (0) 98 #define FP_INEXACT 1 99 #define FP_UNDERFLOW 2 100 #define FP_OVERFLOW 4 101 #define FP_DIV0 8 102 #define FP_INVALID 16 103 #define FP_UNIMPLEMENTED 32 104 }; 105 106 #define NB_MMU_MODES 4 107 #define TARGET_INSN_START_EXTRA_WORDS 2 108 109 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; 110 struct CPUMIPSMVPContext { 111 int32_t CP0_MVPControl; 112 #define CP0MVPCo_CPA 3 113 #define CP0MVPCo_STLB 2 114 #define CP0MVPCo_VPC 1 115 #define CP0MVPCo_EVP 0 116 int32_t CP0_MVPConf0; 117 #define CP0MVPC0_M 31 118 #define CP0MVPC0_TLBS 29 119 #define CP0MVPC0_GS 28 120 #define CP0MVPC0_PCP 27 121 #define CP0MVPC0_PTLBE 16 122 #define CP0MVPC0_TCA 15 123 #define CP0MVPC0_PVPE 10 124 #define CP0MVPC0_PTC 0 125 int32_t CP0_MVPConf1; 126 #define CP0MVPC1_CIM 31 127 #define CP0MVPC1_CIF 30 128 #define CP0MVPC1_PCX 20 129 #define CP0MVPC1_PCP2 10 130 #define CP0MVPC1_PCP1 0 131 }; 132 133 typedef struct mips_def_t mips_def_t; 134 135 #define MIPS_SHADOW_SET_MAX 16 136 #define MIPS_TC_MAX 5 137 #define MIPS_FPU_MAX 1 138 #define MIPS_DSP_ACC 4 139 #define MIPS_KSCRATCH_NUM 6 140 #define MIPS_MAAR_MAX 16 /* Must be an even number. */ 141 142 143 /* 144 * Summary of CP0 registers 145 * ======================== 146 * 147 * 148 * Register 0 Register 1 Register 2 Register 3 149 * ---------- ---------- ---------- ---------- 150 * 151 * 0 Index Random EntryLo0 EntryLo1 152 * 1 MVPControl VPEControl TCStatus GlobalNumber 153 * 2 MVPConf0 VPEConf0 TCBind 154 * 3 MVPConf1 VPEConf1 TCRestart 155 * 4 VPControl YQMask TCHalt 156 * 5 VPESchedule TCContext 157 * 6 VPEScheFBack TCSchedule 158 * 7 VPEOpt TCScheFBack TCOpt 159 * 160 * 161 * Register 4 Register 5 Register 6 Register 7 162 * ---------- ---------- ---------- ---------- 163 * 164 * 0 Context PageMask Wired HWREna 165 * 1 ContextConfig PageGrain SRSConf0 166 * 2 UserLocal SegCtl0 SRSConf1 167 * 3 XContextConfig SegCtl1 SRSConf2 168 * 4 DebugContextID SegCtl2 SRSConf3 169 * 5 MemoryMapID PWBase SRSConf4 170 * 6 PWField PWCtl 171 * 7 PWSize 172 * 173 * 174 * Register 8 Register 9 Register 10 Register 11 175 * ---------- ---------- ----------- ----------- 176 * 177 * 0 BadVAddr Count EntryHi Compare 178 * 1 BadInstr 179 * 2 BadInstrP 180 * 3 BadInstrX 181 * 4 GuestCtl1 GuestCtl0Ext 182 * 5 GuestCtl2 183 * 6 SAARI GuestCtl3 184 * 7 SAAR 185 * 186 * 187 * Register 12 Register 13 Register 14 Register 15 188 * ----------- ----------- ----------- ----------- 189 * 190 * 0 Status Cause EPC PRId 191 * 1 IntCtl EBase 192 * 2 SRSCtl NestedEPC CDMMBase 193 * 3 SRSMap CMGCRBase 194 * 4 View_IPL View_RIPL BEVVA 195 * 5 SRSMap2 NestedExc 196 * 6 GuestCtl0 197 * 7 GTOffset 198 * 199 * 200 * Register 16 Register 17 Register 18 Register 19 201 * ----------- ----------- ----------- ----------- 202 * 203 * 0 Config LLAddr WatchLo WatchHi 204 * 1 Config1 MAAR WatchLo WatchHi 205 * 2 Config2 MAARI WatchLo WatchHi 206 * 3 Config3 WatchLo WatchHi 207 * 4 Config4 WatchLo WatchHi 208 * 5 Config5 WatchLo WatchHi 209 * 6 WatchLo WatchHi 210 * 7 WatchLo WatchHi 211 * 212 * 213 * Register 20 Register 21 Register 22 Register 23 214 * ----------- ----------- ----------- ----------- 215 * 216 * 0 XContext Debug 217 * 1 TraceControl 218 * 2 TraceControl2 219 * 3 UserTraceData1 220 * 4 TraceIBPC 221 * 5 TraceDBPC 222 * 6 Debug2 223 * 7 224 * 225 * 226 * Register 24 Register 25 Register 26 Register 27 227 * ----------- ----------- ----------- ----------- 228 * 229 * 0 DEPC PerfCnt ErrCtl CacheErr 230 * 1 PerfCnt 231 * 2 TraceControl3 PerfCnt 232 * 3 UserTraceData2 PerfCnt 233 * 4 PerfCnt 234 * 5 PerfCnt 235 * 6 PerfCnt 236 * 7 PerfCnt 237 * 238 * 239 * Register 28 Register 29 Register 30 Register 31 240 * ----------- ----------- ----------- ----------- 241 * 242 * 0 DataLo DataHi ErrorEPC DESAVE 243 * 1 TagLo TagHi 244 * 2 DataLo DataHi KScratch<n> 245 * 3 TagLo TagHi KScratch<n> 246 * 4 DataLo DataHi KScratch<n> 247 * 5 TagLo TagHi KScratch<n> 248 * 6 DataLo DataHi KScratch<n> 249 * 7 TagLo TagHi KScratch<n> 250 * 251 */ 252 #define CP0_REGISTER_00 0 253 #define CP0_REGISTER_01 1 254 #define CP0_REGISTER_02 2 255 #define CP0_REGISTER_03 3 256 #define CP0_REGISTER_04 4 257 #define CP0_REGISTER_05 5 258 #define CP0_REGISTER_06 6 259 #define CP0_REGISTER_07 7 260 #define CP0_REGISTER_08 8 261 #define CP0_REGISTER_09 9 262 #define CP0_REGISTER_10 10 263 #define CP0_REGISTER_11 11 264 #define CP0_REGISTER_12 12 265 #define CP0_REGISTER_13 13 266 #define CP0_REGISTER_14 14 267 #define CP0_REGISTER_15 15 268 #define CP0_REGISTER_16 16 269 #define CP0_REGISTER_17 17 270 #define CP0_REGISTER_18 18 271 #define CP0_REGISTER_19 19 272 #define CP0_REGISTER_20 20 273 #define CP0_REGISTER_21 21 274 #define CP0_REGISTER_22 22 275 #define CP0_REGISTER_23 23 276 #define CP0_REGISTER_24 24 277 #define CP0_REGISTER_25 25 278 #define CP0_REGISTER_26 26 279 #define CP0_REGISTER_27 27 280 #define CP0_REGISTER_28 28 281 #define CP0_REGISTER_29 29 282 #define CP0_REGISTER_30 30 283 #define CP0_REGISTER_31 31 284 285 286 /* CP0 Register 00 */ 287 #define CP0_REG00__INDEX 0 288 #define CP0_REG00__VPCONTROL 4 289 /* CP0 Register 01 */ 290 /* CP0 Register 02 */ 291 #define CP0_REG02__ENTRYLO0 0 292 /* CP0 Register 03 */ 293 #define CP0_REG03__ENTRYLO1 0 294 #define CP0_REG03__GLOBALNUM 1 295 /* CP0 Register 04 */ 296 #define CP0_REG04__CONTEXT 0 297 #define CP0_REG04__USERLOCAL 2 298 #define CP0_REG04__DBGCONTEXTID 4 299 #define CP0_REG00__MMID 5 300 /* CP0 Register 05 */ 301 #define CP0_REG05__PAGEMASK 0 302 #define CP0_REG05__PAGEGRAIN 1 303 /* CP0 Register 06 */ 304 #define CP0_REG06__WIRED 0 305 /* CP0 Register 07 */ 306 #define CP0_REG07__HWRENA 0 307 /* CP0 Register 08 */ 308 #define CP0_REG08__BADVADDR 0 309 #define CP0_REG08__BADINSTR 1 310 #define CP0_REG08__BADINSTRP 2 311 /* CP0 Register 09 */ 312 #define CP0_REG09__COUNT 0 313 #define CP0_REG09__SAARI 6 314 #define CP0_REG09__SAAR 7 315 /* CP0 Register 10 */ 316 #define CP0_REG10__ENTRYHI 0 317 #define CP0_REG10__GUESTCTL1 4 318 #define CP0_REG10__GUESTCTL2 5 319 /* CP0 Register 11 */ 320 #define CP0_REG11__COMPARE 0 321 #define CP0_REG11__GUESTCTL0EXT 4 322 /* CP0 Register 12 */ 323 #define CP0_REG12__STATUS 0 324 #define CP0_REG12__INTCTL 1 325 #define CP0_REG12__SRSCTL 2 326 #define CP0_REG12__GUESTCTL0 6 327 #define CP0_REG12__GTOFFSET 7 328 /* CP0 Register 13 */ 329 #define CP0_REG13__CAUSE 0 330 /* CP0 Register 14 */ 331 #define CP0_REG14__EPC 0 332 /* CP0 Register 15 */ 333 #define CP0_REG15__PRID 0 334 #define CP0_REG15__EBASE 1 335 #define CP0_REG15__CDMMBASE 2 336 #define CP0_REG15__CMGCRBASE 3 337 /* CP0 Register 16 */ 338 #define CP0_REG16__CONFIG 0 339 #define CP0_REG16__CONFIG1 1 340 #define CP0_REG16__CONFIG2 2 341 #define CP0_REG16__CONFIG3 3 342 #define CP0_REG16__CONFIG4 4 343 #define CP0_REG16__CONFIG5 5 344 #define CP0_REG00__CONFIG7 7 345 /* CP0 Register 17 */ 346 #define CP0_REG17__LLADDR 0 347 #define CP0_REG17__MAAR 1 348 #define CP0_REG17__MAARI 2 349 /* CP0 Register 18 */ 350 #define CP0_REG18__WATCHLO0 0 351 #define CP0_REG18__WATCHLO1 1 352 #define CP0_REG18__WATCHLO2 2 353 #define CP0_REG18__WATCHLO3 3 354 /* CP0 Register 19 */ 355 #define CP0_REG19__WATCHHI0 0 356 #define CP0_REG19__WATCHHI1 1 357 #define CP0_REG19__WATCHHI2 2 358 #define CP0_REG19__WATCHHI3 3 359 /* CP0 Register 20 */ 360 #define CP0_REG20__XCONTEXT 0 361 /* CP0 Register 21 */ 362 /* CP0 Register 22 */ 363 /* CP0 Register 23 */ 364 #define CP0_REG23__DEBUG 0 365 /* CP0 Register 24 */ 366 #define CP0_REG24__DEPC 0 367 /* CP0 Register 25 */ 368 #define CP0_REG25__PERFCTL0 0 369 #define CP0_REG25__PERFCNT0 1 370 #define CP0_REG25__PERFCTL1 2 371 #define CP0_REG25__PERFCNT1 3 372 #define CP0_REG25__PERFCTL2 4 373 #define CP0_REG25__PERFCNT2 5 374 #define CP0_REG25__PERFCTL3 6 375 #define CP0_REG25__PERFCNT3 7 376 /* CP0 Register 26 */ 377 #define CP0_REG00__ERRCTL 0 378 /* CP0 Register 27 */ 379 #define CP0_REG27__CACHERR 0 380 /* CP0 Register 28 */ 381 #define CP0_REG28__ITAGLO 0 382 #define CP0_REG28__IDATALO 1 383 #define CP0_REG28__DTAGLO 2 384 #define CP0_REG28__DDATALO 3 385 /* CP0 Register 29 */ 386 #define CP0_REG29__IDATAHI 1 387 #define CP0_REG29__DDATAHI 3 388 /* CP0 Register 30 */ 389 #define CP0_REG30__ERROREPC 0 390 /* CP0 Register 31 */ 391 #define CP0_REG31__DESAVE 0 392 #define CP0_REG31__KSCRATCH1 2 393 #define CP0_REG31__KSCRATCH2 3 394 #define CP0_REG31__KSCRATCH3 4 395 #define CP0_REG31__KSCRATCH4 5 396 #define CP0_REG31__KSCRATCH5 6 397 #define CP0_REG31__KSCRATCH6 7 398 399 400 typedef struct TCState TCState; 401 struct TCState { 402 target_ulong gpr[32]; 403 target_ulong PC; 404 target_ulong HI[MIPS_DSP_ACC]; 405 target_ulong LO[MIPS_DSP_ACC]; 406 target_ulong ACX[MIPS_DSP_ACC]; 407 target_ulong DSPControl; 408 int32_t CP0_TCStatus; 409 #define CP0TCSt_TCU3 31 410 #define CP0TCSt_TCU2 30 411 #define CP0TCSt_TCU1 29 412 #define CP0TCSt_TCU0 28 413 #define CP0TCSt_TMX 27 414 #define CP0TCSt_RNST 23 415 #define CP0TCSt_TDS 21 416 #define CP0TCSt_DT 20 417 #define CP0TCSt_DA 15 418 #define CP0TCSt_A 13 419 #define CP0TCSt_TKSU 11 420 #define CP0TCSt_IXMT 10 421 #define CP0TCSt_TASID 0 422 int32_t CP0_TCBind; 423 #define CP0TCBd_CurTC 21 424 #define CP0TCBd_TBE 17 425 #define CP0TCBd_CurVPE 0 426 target_ulong CP0_TCHalt; 427 target_ulong CP0_TCContext; 428 target_ulong CP0_TCSchedule; 429 target_ulong CP0_TCScheFBack; 430 int32_t CP0_Debug_tcstatus; 431 target_ulong CP0_UserLocal; 432 433 int32_t msacsr; 434 435 #define MSACSR_FS 24 436 #define MSACSR_FS_MASK (1 << MSACSR_FS) 437 #define MSACSR_NX 18 438 #define MSACSR_NX_MASK (1 << MSACSR_NX) 439 #define MSACSR_CEF 2 440 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF) 441 #define MSACSR_RM 0 442 #define MSACSR_RM_MASK (0x3 << MSACSR_RM) 443 #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \ 444 MSACSR_FS_MASK) 445 446 float_status msa_fp_status; 447 448 /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */ 449 uint64_t mmr[32]; 450 451 #define NUMBER_OF_MXU_REGISTERS 16 452 target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; 453 target_ulong mxu_cr; 454 #define MXU_CR_LC 31 455 #define MXU_CR_RC 30 456 #define MXU_CR_BIAS 2 457 #define MXU_CR_RD_EN 1 458 #define MXU_CR_MXU_EN 0 459 460 }; 461 462 struct MIPSITUState; 463 typedef struct CPUMIPSState CPUMIPSState; 464 struct CPUMIPSState { 465 TCState active_tc; 466 CPUMIPSFPUContext active_fpu; 467 468 uint32_t current_tc; 469 uint32_t current_fpu; 470 471 uint32_t SEGBITS; 472 uint32_t PABITS; 473 #if defined(TARGET_MIPS64) 474 # define PABITS_BASE 36 475 #else 476 # define PABITS_BASE 32 477 #endif 478 target_ulong SEGMask; 479 uint64_t PAMask; 480 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1) 481 482 int32_t msair; 483 #define MSAIR_ProcID 8 484 #define MSAIR_Rev 0 485 486 /* 487 * CP0 Register 0 488 */ 489 int32_t CP0_Index; 490 /* CP0_MVP* are per MVP registers. */ 491 int32_t CP0_VPControl; 492 #define CP0VPCtl_DIS 0 493 /* 494 * CP0 Register 1 495 */ 496 int32_t CP0_Random; 497 int32_t CP0_VPEControl; 498 #define CP0VPECo_YSI 21 499 #define CP0VPECo_GSI 20 500 #define CP0VPECo_EXCPT 16 501 #define CP0VPECo_TE 15 502 #define CP0VPECo_TargTC 0 503 int32_t CP0_VPEConf0; 504 #define CP0VPEC0_M 31 505 #define CP0VPEC0_XTC 21 506 #define CP0VPEC0_TCS 19 507 #define CP0VPEC0_SCS 18 508 #define CP0VPEC0_DSC 17 509 #define CP0VPEC0_ICS 16 510 #define CP0VPEC0_MVP 1 511 #define CP0VPEC0_VPA 0 512 int32_t CP0_VPEConf1; 513 #define CP0VPEC1_NCX 20 514 #define CP0VPEC1_NCP2 10 515 #define CP0VPEC1_NCP1 0 516 target_ulong CP0_YQMask; 517 target_ulong CP0_VPESchedule; 518 target_ulong CP0_VPEScheFBack; 519 int32_t CP0_VPEOpt; 520 #define CP0VPEOpt_IWX7 15 521 #define CP0VPEOpt_IWX6 14 522 #define CP0VPEOpt_IWX5 13 523 #define CP0VPEOpt_IWX4 12 524 #define CP0VPEOpt_IWX3 11 525 #define CP0VPEOpt_IWX2 10 526 #define CP0VPEOpt_IWX1 9 527 #define CP0VPEOpt_IWX0 8 528 #define CP0VPEOpt_DWX7 7 529 #define CP0VPEOpt_DWX6 6 530 #define CP0VPEOpt_DWX5 5 531 #define CP0VPEOpt_DWX4 4 532 #define CP0VPEOpt_DWX3 3 533 #define CP0VPEOpt_DWX2 2 534 #define CP0VPEOpt_DWX1 1 535 #define CP0VPEOpt_DWX0 0 536 /* 537 * CP0 Register 2 538 */ 539 uint64_t CP0_EntryLo0; 540 /* 541 * CP0 Register 3 542 */ 543 uint64_t CP0_EntryLo1; 544 #if defined(TARGET_MIPS64) 545 # define CP0EnLo_RI 63 546 # define CP0EnLo_XI 62 547 #else 548 # define CP0EnLo_RI 31 549 # define CP0EnLo_XI 30 550 #endif 551 int32_t CP0_GlobalNumber; 552 #define CP0GN_VPId 0 553 /* 554 * CP0 Register 4 555 */ 556 target_ulong CP0_Context; 557 target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; 558 int32_t CP0_MemoryMapID; 559 /* 560 * CP0 Register 5 561 */ 562 int32_t CP0_PageMask; 563 int32_t CP0_PageGrain_rw_bitmask; 564 int32_t CP0_PageGrain; 565 #define CP0PG_RIE 31 566 #define CP0PG_XIE 30 567 #define CP0PG_ELPA 29 568 #define CP0PG_IEC 27 569 target_ulong CP0_SegCtl0; 570 target_ulong CP0_SegCtl1; 571 target_ulong CP0_SegCtl2; 572 #define CP0SC_PA 9 573 #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA) 574 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA) 575 #define CP0SC_AM 4 576 #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM) 577 #define CP0SC_AM_UK 0ULL 578 #define CP0SC_AM_MK 1ULL 579 #define CP0SC_AM_MSK 2ULL 580 #define CP0SC_AM_MUSK 3ULL 581 #define CP0SC_AM_MUSUK 4ULL 582 #define CP0SC_AM_USK 5ULL 583 #define CP0SC_AM_UUSK 7ULL 584 #define CP0SC_EU 3 585 #define CP0SC_EU_MASK (1ULL << CP0SC_EU) 586 #define CP0SC_C 0 587 #define CP0SC_C_MASK (0x7ULL << CP0SC_C) 588 #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ 589 CP0SC_PA_MASK) 590 #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ 591 CP0SC_PA_1GMASK) 592 #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16)) 593 #define CP0SC1_XAM 59 594 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM) 595 #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK) 596 #define CP0SC2_XR 56 597 #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR) 598 #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK) 599 target_ulong CP0_PWBase; 600 target_ulong CP0_PWField; 601 #if defined(TARGET_MIPS64) 602 #define CP0PF_BDI 32 /* 37..32 */ 603 #define CP0PF_GDI 24 /* 29..24 */ 604 #define CP0PF_UDI 18 /* 23..18 */ 605 #define CP0PF_MDI 12 /* 17..12 */ 606 #define CP0PF_PTI 6 /* 11..6 */ 607 #define CP0PF_PTEI 0 /* 5..0 */ 608 #else 609 #define CP0PF_GDW 24 /* 29..24 */ 610 #define CP0PF_UDW 18 /* 23..18 */ 611 #define CP0PF_MDW 12 /* 17..12 */ 612 #define CP0PF_PTW 6 /* 11..6 */ 613 #define CP0PF_PTEW 0 /* 5..0 */ 614 #endif 615 target_ulong CP0_PWSize; 616 #if defined(TARGET_MIPS64) 617 #define CP0PS_BDW 32 /* 37..32 */ 618 #endif 619 #define CP0PS_PS 30 620 #define CP0PS_GDW 24 /* 29..24 */ 621 #define CP0PS_UDW 18 /* 23..18 */ 622 #define CP0PS_MDW 12 /* 17..12 */ 623 #define CP0PS_PTW 6 /* 11..6 */ 624 #define CP0PS_PTEW 0 /* 5..0 */ 625 /* 626 * CP0 Register 6 627 */ 628 int32_t CP0_Wired; 629 int32_t CP0_PWCtl; 630 #define CP0PC_PWEN 31 631 #if defined(TARGET_MIPS64) 632 #define CP0PC_PWDIREXT 30 633 #define CP0PC_XK 28 634 #define CP0PC_XS 27 635 #define CP0PC_XU 26 636 #endif 637 #define CP0PC_DPH 7 638 #define CP0PC_HUGEPG 6 639 #define CP0PC_PSN 0 /* 5..0 */ 640 int32_t CP0_SRSConf0_rw_bitmask; 641 int32_t CP0_SRSConf0; 642 #define CP0SRSC0_M 31 643 #define CP0SRSC0_SRS3 20 644 #define CP0SRSC0_SRS2 10 645 #define CP0SRSC0_SRS1 0 646 int32_t CP0_SRSConf1_rw_bitmask; 647 int32_t CP0_SRSConf1; 648 #define CP0SRSC1_M 31 649 #define CP0SRSC1_SRS6 20 650 #define CP0SRSC1_SRS5 10 651 #define CP0SRSC1_SRS4 0 652 int32_t CP0_SRSConf2_rw_bitmask; 653 int32_t CP0_SRSConf2; 654 #define CP0SRSC2_M 31 655 #define CP0SRSC2_SRS9 20 656 #define CP0SRSC2_SRS8 10 657 #define CP0SRSC2_SRS7 0 658 int32_t CP0_SRSConf3_rw_bitmask; 659 int32_t CP0_SRSConf3; 660 #define CP0SRSC3_M 31 661 #define CP0SRSC3_SRS12 20 662 #define CP0SRSC3_SRS11 10 663 #define CP0SRSC3_SRS10 0 664 int32_t CP0_SRSConf4_rw_bitmask; 665 int32_t CP0_SRSConf4; 666 #define CP0SRSC4_SRS15 20 667 #define CP0SRSC4_SRS14 10 668 #define CP0SRSC4_SRS13 0 669 /* 670 * CP0 Register 7 671 */ 672 int32_t CP0_HWREna; 673 /* 674 * CP0 Register 8 675 */ 676 target_ulong CP0_BadVAddr; 677 uint32_t CP0_BadInstr; 678 uint32_t CP0_BadInstrP; 679 uint32_t CP0_BadInstrX; 680 /* 681 * CP0 Register 9 682 */ 683 int32_t CP0_Count; 684 uint32_t CP0_SAARI; 685 #define CP0SAARI_TARGET 0 /* 5..0 */ 686 uint64_t CP0_SAAR[2]; 687 #define CP0SAAR_BASE 12 /* 43..12 */ 688 #define CP0SAAR_SIZE 1 /* 5..1 */ 689 #define CP0SAAR_EN 0 690 /* 691 * CP0 Register 10 692 */ 693 target_ulong CP0_EntryHi; 694 #define CP0EnHi_EHINV 10 695 target_ulong CP0_EntryHi_ASID_mask; 696 /* 697 * CP0 Register 11 698 */ 699 int32_t CP0_Compare; 700 /* 701 * CP0 Register 12 702 */ 703 int32_t CP0_Status; 704 #define CP0St_CU3 31 705 #define CP0St_CU2 30 706 #define CP0St_CU1 29 707 #define CP0St_CU0 28 708 #define CP0St_RP 27 709 #define CP0St_FR 26 710 #define CP0St_RE 25 711 #define CP0St_MX 24 712 #define CP0St_PX 23 713 #define CP0St_BEV 22 714 #define CP0St_TS 21 715 #define CP0St_SR 20 716 #define CP0St_NMI 19 717 #define CP0St_IM 8 718 #define CP0St_KX 7 719 #define CP0St_SX 6 720 #define CP0St_UX 5 721 #define CP0St_KSU 3 722 #define CP0St_ERL 2 723 #define CP0St_EXL 1 724 #define CP0St_IE 0 725 int32_t CP0_IntCtl; 726 #define CP0IntCtl_IPTI 29 727 #define CP0IntCtl_IPPCI 26 728 #define CP0IntCtl_VS 5 729 int32_t CP0_SRSCtl; 730 #define CP0SRSCtl_HSS 26 731 #define CP0SRSCtl_EICSS 18 732 #define CP0SRSCtl_ESS 12 733 #define CP0SRSCtl_PSS 6 734 #define CP0SRSCtl_CSS 0 735 int32_t CP0_SRSMap; 736 #define CP0SRSMap_SSV7 28 737 #define CP0SRSMap_SSV6 24 738 #define CP0SRSMap_SSV5 20 739 #define CP0SRSMap_SSV4 16 740 #define CP0SRSMap_SSV3 12 741 #define CP0SRSMap_SSV2 8 742 #define CP0SRSMap_SSV1 4 743 #define CP0SRSMap_SSV0 0 744 /* 745 * CP0 Register 13 746 */ 747 int32_t CP0_Cause; 748 #define CP0Ca_BD 31 749 #define CP0Ca_TI 30 750 #define CP0Ca_CE 28 751 #define CP0Ca_DC 27 752 #define CP0Ca_PCI 26 753 #define CP0Ca_IV 23 754 #define CP0Ca_WP 22 755 #define CP0Ca_IP 8 756 #define CP0Ca_IP_mask 0x0000FF00 757 #define CP0Ca_EC 2 758 /* 759 * CP0 Register 14 760 */ 761 target_ulong CP0_EPC; 762 /* 763 * CP0 Register 15 764 */ 765 int32_t CP0_PRid; 766 target_ulong CP0_EBase; 767 target_ulong CP0_EBaseWG_rw_bitmask; 768 #define CP0EBase_WG 11 769 target_ulong CP0_CMGCRBase; 770 /* 771 * CP0 Register 16 772 */ 773 int32_t CP0_Config0; 774 #define CP0C0_M 31 775 #define CP0C0_K23 28 /* 30..28 */ 776 #define CP0C0_KU 25 /* 27..25 */ 777 #define CP0C0_MDU 20 778 #define CP0C0_MM 18 779 #define CP0C0_BM 16 780 #define CP0C0_Impl 16 /* 24..16 */ 781 #define CP0C0_BE 15 782 #define CP0C0_AT 13 /* 14..13 */ 783 #define CP0C0_AR 10 /* 12..10 */ 784 #define CP0C0_MT 7 /* 9..7 */ 785 #define CP0C0_VI 3 786 #define CP0C0_K0 0 /* 2..0 */ 787 int32_t CP0_Config1; 788 #define CP0C1_M 31 789 #define CP0C1_MMU 25 /* 30..25 */ 790 #define CP0C1_IS 22 /* 24..22 */ 791 #define CP0C1_IL 19 /* 21..19 */ 792 #define CP0C1_IA 16 /* 18..16 */ 793 #define CP0C1_DS 13 /* 15..13 */ 794 #define CP0C1_DL 10 /* 12..10 */ 795 #define CP0C1_DA 7 /* 9..7 */ 796 #define CP0C1_C2 6 797 #define CP0C1_MD 5 798 #define CP0C1_PC 4 799 #define CP0C1_WR 3 800 #define CP0C1_CA 2 801 #define CP0C1_EP 1 802 #define CP0C1_FP 0 803 int32_t CP0_Config2; 804 #define CP0C2_M 31 805 #define CP0C2_TU 28 /* 30..28 */ 806 #define CP0C2_TS 24 /* 27..24 */ 807 #define CP0C2_TL 20 /* 23..20 */ 808 #define CP0C2_TA 16 /* 19..16 */ 809 #define CP0C2_SU 12 /* 15..12 */ 810 #define CP0C2_SS 8 /* 11..8 */ 811 #define CP0C2_SL 4 /* 7..4 */ 812 #define CP0C2_SA 0 /* 3..0 */ 813 int32_t CP0_Config3; 814 #define CP0C3_M 31 815 #define CP0C3_BPG 30 816 #define CP0C3_CMGCR 29 817 #define CP0C3_MSAP 28 818 #define CP0C3_BP 27 819 #define CP0C3_BI 26 820 #define CP0C3_SC 25 821 #define CP0C3_PW 24 822 #define CP0C3_VZ 23 823 #define CP0C3_IPLV 21 /* 22..21 */ 824 #define CP0C3_MMAR 18 /* 20..18 */ 825 #define CP0C3_MCU 17 826 #define CP0C3_ISA_ON_EXC 16 827 #define CP0C3_ISA 14 /* 15..14 */ 828 #define CP0C3_ULRI 13 829 #define CP0C3_RXI 12 830 #define CP0C3_DSP2P 11 831 #define CP0C3_DSPP 10 832 #define CP0C3_CTXTC 9 833 #define CP0C3_ITL 8 834 #define CP0C3_LPA 7 835 #define CP0C3_VEIC 6 836 #define CP0C3_VInt 5 837 #define CP0C3_SP 4 838 #define CP0C3_CDMM 3 839 #define CP0C3_MT 2 840 #define CP0C3_SM 1 841 #define CP0C3_TL 0 842 int32_t CP0_Config4; 843 int32_t CP0_Config4_rw_bitmask; 844 #define CP0C4_M 31 845 #define CP0C4_IE 29 /* 30..29 */ 846 #define CP0C4_AE 28 847 #define CP0C4_VTLBSizeExt 24 /* 27..24 */ 848 #define CP0C4_KScrExist 16 849 #define CP0C4_MMUExtDef 14 850 #define CP0C4_FTLBPageSize 8 /* 12..8 */ 851 /* bit layout if MMUExtDef=1 */ 852 #define CP0C4_MMUSizeExt 0 /* 7..0 */ 853 /* bit layout if MMUExtDef=2 */ 854 #define CP0C4_FTLBWays 4 /* 7..4 */ 855 #define CP0C4_FTLBSets 0 /* 3..0 */ 856 int32_t CP0_Config5; 857 int32_t CP0_Config5_rw_bitmask; 858 #define CP0C5_M 31 859 #define CP0C5_K 30 860 #define CP0C5_CV 29 861 #define CP0C5_EVA 28 862 #define CP0C5_MSAEn 27 863 #define CP0C5_PMJ 23 /* 25..23 */ 864 #define CP0C5_WR2 22 865 #define CP0C5_NMS 21 866 #define CP0C5_ULS 20 867 #define CP0C5_XPA 19 868 #define CP0C5_CRCP 18 869 #define CP0C5_MI 17 870 #define CP0C5_GI 15 /* 16..15 */ 871 #define CP0C5_CA2 14 872 #define CP0C5_XNP 13 873 #define CP0C5_DEC 11 874 #define CP0C5_L2C 10 875 #define CP0C5_UFE 9 876 #define CP0C5_FRE 8 877 #define CP0C5_VP 7 878 #define CP0C5_SBRI 6 879 #define CP0C5_MVH 5 880 #define CP0C5_LLB 4 881 #define CP0C5_MRP 3 882 #define CP0C5_UFR 2 883 #define CP0C5_NFExists 0 884 int32_t CP0_Config6; 885 int32_t CP0_Config7; 886 uint64_t CP0_LLAddr; 887 uint64_t CP0_MAAR[MIPS_MAAR_MAX]; 888 int32_t CP0_MAARI; 889 /* XXX: Maybe make LLAddr per-TC? */ 890 /* 891 * CP0 Register 17 892 */ 893 target_ulong lladdr; /* LL virtual address compared against SC */ 894 target_ulong llval; 895 uint64_t llval_wp; 896 uint32_t llnewval_wp; 897 uint64_t CP0_LLAddr_rw_bitmask; 898 int CP0_LLAddr_shift; 899 /* 900 * CP0 Register 18 901 */ 902 target_ulong CP0_WatchLo[8]; 903 /* 904 * CP0 Register 19 905 */ 906 int32_t CP0_WatchHi[8]; 907 #define CP0WH_ASID 16 908 /* 909 * CP0 Register 20 910 */ 911 target_ulong CP0_XContext; 912 int32_t CP0_Framemask; 913 /* 914 * CP0 Register 23 915 */ 916 int32_t CP0_Debug; 917 #define CP0DB_DBD 31 918 #define CP0DB_DM 30 919 #define CP0DB_LSNM 28 920 #define CP0DB_Doze 27 921 #define CP0DB_Halt 26 922 #define CP0DB_CNT 25 923 #define CP0DB_IBEP 24 924 #define CP0DB_DBEP 21 925 #define CP0DB_IEXI 20 926 #define CP0DB_VER 15 927 #define CP0DB_DEC 10 928 #define CP0DB_SSt 8 929 #define CP0DB_DINT 5 930 #define CP0DB_DIB 4 931 #define CP0DB_DDBS 3 932 #define CP0DB_DDBL 2 933 #define CP0DB_DBp 1 934 #define CP0DB_DSS 0 935 /* 936 * CP0 Register 24 937 */ 938 target_ulong CP0_DEPC; 939 /* 940 * CP0 Register 25 941 */ 942 int32_t CP0_Performance0; 943 /* 944 * CP0 Register 26 945 */ 946 int32_t CP0_ErrCtl; 947 #define CP0EC_WST 29 948 #define CP0EC_SPR 28 949 #define CP0EC_ITC 26 950 /* 951 * CP0 Register 28 952 */ 953 uint64_t CP0_TagLo; 954 int32_t CP0_DataLo; 955 /* 956 * CP0 Register 29 957 */ 958 int32_t CP0_TagHi; 959 int32_t CP0_DataHi; 960 /* 961 * CP0 Register 30 962 */ 963 target_ulong CP0_ErrorEPC; 964 /* 965 * CP0 Register 31 966 */ 967 int32_t CP0_DESAVE; 968 969 /* We waste some space so we can handle shadow registers like TCs. */ 970 TCState tcs[MIPS_SHADOW_SET_MAX]; 971 CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; 972 /* QEMU */ 973 int error_code; 974 #define EXCP_TLB_NOMATCH 0x1 975 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ 976 uint32_t hflags; /* CPU State */ 977 /* TMASK defines different execution modes */ 978 #define MIPS_HFLAG_TMASK 0x1F5807FF 979 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ 980 /* 981 * The KSU flags must be the lowest bits in hflags. The flag order 982 * must be the same as defined for CP0 Status. This allows to use 983 * the bits as the value of mmu_idx. 984 */ 985 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ 986 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ 987 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ 988 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ 989 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ 990 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ 991 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ 992 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ 993 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ 994 /* 995 * True if the MIPS IV COP1X instructions can be used. This also 996 * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S 997 * and RSQRT.D. 998 */ 999 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ 1000 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ 1001 #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ 1002 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ 1003 #define MIPS_HFLAG_M16_SHIFT 10 1004 /* 1005 * If translation is interrupted between the branch instruction and 1006 * the delay slot, record what type of branch it is so that we can 1007 * resume translation properly. It might be possible to reduce 1008 * this from three bits to two. 1009 */ 1010 #define MIPS_HFLAG_BMASK_BASE 0x803800 1011 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ 1012 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ 1013 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ 1014 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ 1015 /* Extra flags about the current pending branch. */ 1016 #define MIPS_HFLAG_BMASK_EXT 0x7C000 1017 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ 1018 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ 1019 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ 1020 #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */ 1021 #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */ 1022 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) 1023 /* MIPS DSP resources access. */ 1024 #define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */ 1025 #define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */ 1026 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */ 1027 /* Extra flag about HWREna register. */ 1028 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ 1029 #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */ 1030 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */ 1031 #define MIPS_HFLAG_MSA 0x1000000 1032 #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */ 1033 #define MIPS_HFLAG_ELPA 0x4000000 1034 #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */ 1035 #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */ 1036 target_ulong btarget; /* Jump / branch target */ 1037 target_ulong bcond; /* Branch condition (if needed) */ 1038 1039 int SYNCI_Step; /* Address step size for SYNCI */ 1040 int CCRes; /* Cycle count resolution/divisor */ 1041 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ 1042 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ 1043 uint64_t insn_flags; /* Supported instruction set */ 1044 int saarp; 1045 1046 /* Fields up to this point are cleared by a CPU reset */ 1047 struct {} end_reset_fields; 1048 1049 CPU_COMMON 1050 1051 /* Fields from here on are preserved across CPU reset. */ 1052 CPUMIPSMVPContext *mvp; 1053 #if !defined(CONFIG_USER_ONLY) 1054 CPUMIPSTLBContext *tlb; 1055 #endif 1056 1057 const mips_def_t *cpu_model; 1058 void *irq[8]; 1059 QEMUTimer *timer; /* Internal timer */ 1060 struct MIPSITUState *itu; 1061 MemoryRegion *itc_tag; /* ITC Configuration Tags */ 1062 target_ulong exception_base; /* ExceptionBase input to the core */ 1063 }; 1064 1065 /** 1066 * MIPSCPU: 1067 * @env: #CPUMIPSState 1068 * 1069 * A MIPS CPU. 1070 */ 1071 struct MIPSCPU { 1072 /*< private >*/ 1073 CPUState parent_obj; 1074 /*< public >*/ 1075 1076 CPUMIPSState env; 1077 }; 1078 1079 static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) 1080 { 1081 return container_of(env, MIPSCPU, env); 1082 } 1083 1084 #define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e)) 1085 1086 #define ENV_OFFSET offsetof(MIPSCPU, env) 1087 1088 void mips_cpu_list(void); 1089 1090 #define cpu_signal_handler cpu_mips_signal_handler 1091 #define cpu_list mips_cpu_list 1092 1093 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); 1094 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); 1095 1096 /* 1097 * MMU modes definitions. We carefully match the indices with our 1098 * hflags layout. 1099 */ 1100 #define MMU_MODE0_SUFFIX _kernel 1101 #define MMU_MODE1_SUFFIX _super 1102 #define MMU_MODE2_SUFFIX _user 1103 #define MMU_MODE3_SUFFIX _error 1104 #define MMU_USER_IDX 2 1105 1106 static inline int hflags_mmu_index(uint32_t hflags) 1107 { 1108 if (hflags & MIPS_HFLAG_ERL) { 1109 return 3; /* ERL */ 1110 } else { 1111 return hflags & MIPS_HFLAG_KSU; 1112 } 1113 } 1114 1115 static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) 1116 { 1117 return hflags_mmu_index(env->hflags); 1118 } 1119 1120 #include "exec/cpu-all.h" 1121 1122 /* 1123 * Memory access type : 1124 * may be needed for precise access rights control and precise exceptions. 1125 */ 1126 enum { 1127 /* 1 bit to define user level / supervisor access */ 1128 ACCESS_USER = 0x00, 1129 ACCESS_SUPER = 0x01, 1130 /* 1 bit to indicate direction */ 1131 ACCESS_STORE = 0x02, 1132 /* Type of instruction that generated the access */ 1133 ACCESS_CODE = 0x10, /* Code fetch access */ 1134 ACCESS_INT = 0x20, /* Integer load/store access */ 1135 ACCESS_FLOAT = 0x30, /* floating point load/store access */ 1136 }; 1137 1138 /* Exceptions */ 1139 enum { 1140 EXCP_NONE = -1, 1141 EXCP_RESET = 0, 1142 EXCP_SRESET, 1143 EXCP_DSS, 1144 EXCP_DINT, 1145 EXCP_DDBL, 1146 EXCP_DDBS, 1147 EXCP_NMI, 1148 EXCP_MCHECK, 1149 EXCP_EXT_INTERRUPT, /* 8 */ 1150 EXCP_DFWATCH, 1151 EXCP_DIB, 1152 EXCP_IWATCH, 1153 EXCP_AdEL, 1154 EXCP_AdES, 1155 EXCP_TLBF, 1156 EXCP_IBE, 1157 EXCP_DBp, /* 16 */ 1158 EXCP_SYSCALL, 1159 EXCP_BREAK, 1160 EXCP_CpU, 1161 EXCP_RI, 1162 EXCP_OVERFLOW, 1163 EXCP_TRAP, 1164 EXCP_FPE, 1165 EXCP_DWATCH, /* 24 */ 1166 EXCP_LTLBL, 1167 EXCP_TLBL, 1168 EXCP_TLBS, 1169 EXCP_DBE, 1170 EXCP_THREAD, 1171 EXCP_MDMX, 1172 EXCP_C2E, 1173 EXCP_CACHE, /* 32 */ 1174 EXCP_DSPDIS, 1175 EXCP_MSADIS, 1176 EXCP_MSAFPE, 1177 EXCP_TLBXI, 1178 EXCP_TLBRI, 1179 1180 EXCP_LAST = EXCP_TLBRI, 1181 }; 1182 1183 /* 1184 * This is an internally generated WAKE request line. 1185 * It is driven by the CPU itself. Raised when the MT 1186 * block wants to wake a VPE from an inactive state and 1187 * cleared when VPE goes from active to inactive. 1188 */ 1189 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 1190 1191 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); 1192 1193 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU 1194 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX 1195 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU 1196 1197 bool cpu_supports_cps_smp(const char *cpu_type); 1198 bool cpu_supports_isa(const char *cpu_type, uint64_t isa); 1199 void cpu_set_exception_base(int vp_index, target_ulong address); 1200 1201 /* mips_int.c */ 1202 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); 1203 1204 /* mips_itu.c */ 1205 void itc_reconfigure(struct MIPSITUState *tag); 1206 1207 /* helper.c */ 1208 target_ulong exception_resume_pc(CPUMIPSState *env); 1209 1210 static inline void restore_snan_bit_mode(CPUMIPSState *env) 1211 { 1212 set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, 1213 &env->active_fpu.fp_status); 1214 } 1215 1216 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, 1217 target_ulong *cs_base, uint32_t *flags) 1218 { 1219 *pc = env->active_tc.PC; 1220 *cs_base = 0; 1221 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | 1222 MIPS_HFLAG_HWRENA_ULR); 1223 } 1224 1225 #endif /* MIPS_CPU_H */ 1226