1 #ifndef MIPS_CPU_H 2 #define MIPS_CPU_H 3 4 #include "cpu-qom.h" 5 #include "exec/cpu-defs.h" 6 #include "fpu/softfloat-types.h" 7 #include "hw/clock.h" 8 #include "mips-defs.h" 9 10 #define TCG_GUEST_DEFAULT_MO (0) 11 12 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; 13 14 /* MSA Context */ 15 #define MSA_WRLEN (128) 16 17 typedef union wr_t wr_t; 18 union wr_t { 19 int8_t b[MSA_WRLEN / 8]; 20 int16_t h[MSA_WRLEN / 16]; 21 int32_t w[MSA_WRLEN / 32]; 22 int64_t d[MSA_WRLEN / 64]; 23 }; 24 25 typedef union fpr_t fpr_t; 26 union fpr_t { 27 float64 fd; /* ieee double precision */ 28 float32 fs[2];/* ieee single precision */ 29 uint64_t d; /* binary double fixed-point */ 30 uint32_t w[2]; /* binary single fixed-point */ 31 /* FPU/MSA register mapping is not tested on big-endian hosts. */ 32 wr_t wr; /* vector data */ 33 }; 34 /* 35 *define FP_ENDIAN_IDX to access the same location 36 * in the fpr_t union regardless of the host endianness 37 */ 38 #if defined(HOST_WORDS_BIGENDIAN) 39 # define FP_ENDIAN_IDX 1 40 #else 41 # define FP_ENDIAN_IDX 0 42 #endif 43 44 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; 45 struct CPUMIPSFPUContext { 46 /* Floating point registers */ 47 fpr_t fpr[32]; 48 float_status fp_status; 49 /* fpu implementation/revision register (fir) */ 50 uint32_t fcr0; 51 #define FCR0_FREP 29 52 #define FCR0_UFRP 28 53 #define FCR0_HAS2008 23 54 #define FCR0_F64 22 55 #define FCR0_L 21 56 #define FCR0_W 20 57 #define FCR0_3D 19 58 #define FCR0_PS 18 59 #define FCR0_D 17 60 #define FCR0_S 16 61 #define FCR0_PRID 8 62 #define FCR0_REV 0 63 /* fcsr */ 64 uint32_t fcr31_rw_bitmask; 65 uint32_t fcr31; 66 #define FCR31_FS 24 67 #define FCR31_ABS2008 19 68 #define FCR31_NAN2008 18 69 #define SET_FP_COND(num, env) do { ((env).fcr31) |= \ 70 ((num) ? (1 << ((num) + 24)) : \ 71 (1 << 23)); \ 72 } while (0) 73 #define CLEAR_FP_COND(num, env) do { ((env).fcr31) &= \ 74 ~((num) ? (1 << ((num) + 24)) : \ 75 (1 << 23)); \ 76 } while (0) 77 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \ 78 (((env).fcr31 >> 23) & 0x1)) 79 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) 80 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 81 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) 82 #define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \ 83 ((v & 0x3f) << 12); \ 84 } while (0) 85 #define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \ 86 ((v & 0x1f) << 7); \ 87 } while (0) 88 #define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 2)) | \ 89 ((v & 0x1f) << 2); \ 90 } while (0) 91 #define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 2); } while (0) 92 #define FP_INEXACT 1 93 #define FP_UNDERFLOW 2 94 #define FP_OVERFLOW 4 95 #define FP_DIV0 8 96 #define FP_INVALID 16 97 #define FP_UNIMPLEMENTED 32 98 }; 99 100 #define TARGET_INSN_START_EXTRA_WORDS 2 101 102 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; 103 struct CPUMIPSMVPContext { 104 int32_t CP0_MVPControl; 105 #define CP0MVPCo_CPA 3 106 #define CP0MVPCo_STLB 2 107 #define CP0MVPCo_VPC 1 108 #define CP0MVPCo_EVP 0 109 int32_t CP0_MVPConf0; 110 #define CP0MVPC0_M 31 111 #define CP0MVPC0_TLBS 29 112 #define CP0MVPC0_GS 28 113 #define CP0MVPC0_PCP 27 114 #define CP0MVPC0_PTLBE 16 115 #define CP0MVPC0_TCA 15 116 #define CP0MVPC0_PVPE 10 117 #define CP0MVPC0_PTC 0 118 int32_t CP0_MVPConf1; 119 #define CP0MVPC1_CIM 31 120 #define CP0MVPC1_CIF 30 121 #define CP0MVPC1_PCX 20 122 #define CP0MVPC1_PCP2 10 123 #define CP0MVPC1_PCP1 0 124 }; 125 126 typedef struct mips_def_t mips_def_t; 127 128 #define MIPS_SHADOW_SET_MAX 16 129 #define MIPS_TC_MAX 5 130 #define MIPS_FPU_MAX 1 131 #define MIPS_DSP_ACC 4 132 #define MIPS_KSCRATCH_NUM 6 133 #define MIPS_MAAR_MAX 16 /* Must be an even number. */ 134 135 136 /* 137 * Summary of CP0 registers 138 * ======================== 139 * 140 * 141 * Register 0 Register 1 Register 2 Register 3 142 * ---------- ---------- ---------- ---------- 143 * 144 * 0 Index Random EntryLo0 EntryLo1 145 * 1 MVPControl VPEControl TCStatus GlobalNumber 146 * 2 MVPConf0 VPEConf0 TCBind 147 * 3 MVPConf1 VPEConf1 TCRestart 148 * 4 VPControl YQMask TCHalt 149 * 5 VPESchedule TCContext 150 * 6 VPEScheFBack TCSchedule 151 * 7 VPEOpt TCScheFBack TCOpt 152 * 153 * 154 * Register 4 Register 5 Register 6 Register 7 155 * ---------- ---------- ---------- ---------- 156 * 157 * 0 Context PageMask Wired HWREna 158 * 1 ContextConfig PageGrain SRSConf0 159 * 2 UserLocal SegCtl0 SRSConf1 160 * 3 XContextConfig SegCtl1 SRSConf2 161 * 4 DebugContextID SegCtl2 SRSConf3 162 * 5 MemoryMapID PWBase SRSConf4 163 * 6 PWField PWCtl 164 * 7 PWSize 165 * 166 * 167 * Register 8 Register 9 Register 10 Register 11 168 * ---------- ---------- ----------- ----------- 169 * 170 * 0 BadVAddr Count EntryHi Compare 171 * 1 BadInstr 172 * 2 BadInstrP 173 * 3 BadInstrX 174 * 4 GuestCtl1 GuestCtl0Ext 175 * 5 GuestCtl2 176 * 6 SAARI GuestCtl3 177 * 7 SAAR 178 * 179 * 180 * Register 12 Register 13 Register 14 Register 15 181 * ----------- ----------- ----------- ----------- 182 * 183 * 0 Status Cause EPC PRId 184 * 1 IntCtl EBase 185 * 2 SRSCtl NestedEPC CDMMBase 186 * 3 SRSMap CMGCRBase 187 * 4 View_IPL View_RIPL BEVVA 188 * 5 SRSMap2 NestedExc 189 * 6 GuestCtl0 190 * 7 GTOffset 191 * 192 * 193 * Register 16 Register 17 Register 18 Register 19 194 * ----------- ----------- ----------- ----------- 195 * 196 * 0 Config LLAddr WatchLo0 WatchHi 197 * 1 Config1 MAAR WatchLo1 WatchHi 198 * 2 Config2 MAARI WatchLo2 WatchHi 199 * 3 Config3 WatchLo3 WatchHi 200 * 4 Config4 WatchLo4 WatchHi 201 * 5 Config5 WatchLo5 WatchHi 202 * 6 Config6 WatchLo6 WatchHi 203 * 7 Config7 WatchLo7 WatchHi 204 * 205 * 206 * Register 20 Register 21 Register 22 Register 23 207 * ----------- ----------- ----------- ----------- 208 * 209 * 0 XContext Debug 210 * 1 TraceControl 211 * 2 TraceControl2 212 * 3 UserTraceData1 213 * 4 TraceIBPC 214 * 5 TraceDBPC 215 * 6 Debug2 216 * 7 217 * 218 * 219 * Register 24 Register 25 Register 26 Register 27 220 * ----------- ----------- ----------- ----------- 221 * 222 * 0 DEPC PerfCnt ErrCtl CacheErr 223 * 1 PerfCnt 224 * 2 TraceControl3 PerfCnt 225 * 3 UserTraceData2 PerfCnt 226 * 4 PerfCnt 227 * 5 PerfCnt 228 * 6 PerfCnt 229 * 7 PerfCnt 230 * 231 * 232 * Register 28 Register 29 Register 30 Register 31 233 * ----------- ----------- ----------- ----------- 234 * 235 * 0 DataLo DataHi ErrorEPC DESAVE 236 * 1 TagLo TagHi 237 * 2 DataLo1 DataHi1 KScratch<n> 238 * 3 TagLo1 TagHi1 KScratch<n> 239 * 4 DataLo2 DataHi2 KScratch<n> 240 * 5 TagLo2 TagHi2 KScratch<n> 241 * 6 DataLo3 DataHi3 KScratch<n> 242 * 7 TagLo3 TagHi3 KScratch<n> 243 * 244 */ 245 #define CP0_REGISTER_00 0 246 #define CP0_REGISTER_01 1 247 #define CP0_REGISTER_02 2 248 #define CP0_REGISTER_03 3 249 #define CP0_REGISTER_04 4 250 #define CP0_REGISTER_05 5 251 #define CP0_REGISTER_06 6 252 #define CP0_REGISTER_07 7 253 #define CP0_REGISTER_08 8 254 #define CP0_REGISTER_09 9 255 #define CP0_REGISTER_10 10 256 #define CP0_REGISTER_11 11 257 #define CP0_REGISTER_12 12 258 #define CP0_REGISTER_13 13 259 #define CP0_REGISTER_14 14 260 #define CP0_REGISTER_15 15 261 #define CP0_REGISTER_16 16 262 #define CP0_REGISTER_17 17 263 #define CP0_REGISTER_18 18 264 #define CP0_REGISTER_19 19 265 #define CP0_REGISTER_20 20 266 #define CP0_REGISTER_21 21 267 #define CP0_REGISTER_22 22 268 #define CP0_REGISTER_23 23 269 #define CP0_REGISTER_24 24 270 #define CP0_REGISTER_25 25 271 #define CP0_REGISTER_26 26 272 #define CP0_REGISTER_27 27 273 #define CP0_REGISTER_28 28 274 #define CP0_REGISTER_29 29 275 #define CP0_REGISTER_30 30 276 #define CP0_REGISTER_31 31 277 278 279 /* CP0 Register 00 */ 280 #define CP0_REG00__INDEX 0 281 #define CP0_REG00__MVPCONTROL 1 282 #define CP0_REG00__MVPCONF0 2 283 #define CP0_REG00__MVPCONF1 3 284 #define CP0_REG00__VPCONTROL 4 285 /* CP0 Register 01 */ 286 #define CP0_REG01__RANDOM 0 287 #define CP0_REG01__VPECONTROL 1 288 #define CP0_REG01__VPECONF0 2 289 #define CP0_REG01__VPECONF1 3 290 #define CP0_REG01__YQMASK 4 291 #define CP0_REG01__VPESCHEDULE 5 292 #define CP0_REG01__VPESCHEFBACK 6 293 #define CP0_REG01__VPEOPT 7 294 /* CP0 Register 02 */ 295 #define CP0_REG02__ENTRYLO0 0 296 #define CP0_REG02__TCSTATUS 1 297 #define CP0_REG02__TCBIND 2 298 #define CP0_REG02__TCRESTART 3 299 #define CP0_REG02__TCHALT 4 300 #define CP0_REG02__TCCONTEXT 5 301 #define CP0_REG02__TCSCHEDULE 6 302 #define CP0_REG02__TCSCHEFBACK 7 303 /* CP0 Register 03 */ 304 #define CP0_REG03__ENTRYLO1 0 305 #define CP0_REG03__GLOBALNUM 1 306 #define CP0_REG03__TCOPT 7 307 /* CP0 Register 04 */ 308 #define CP0_REG04__CONTEXT 0 309 #define CP0_REG04__CONTEXTCONFIG 1 310 #define CP0_REG04__USERLOCAL 2 311 #define CP0_REG04__XCONTEXTCONFIG 3 312 #define CP0_REG04__DBGCONTEXTID 4 313 #define CP0_REG04__MMID 5 314 /* CP0 Register 05 */ 315 #define CP0_REG05__PAGEMASK 0 316 #define CP0_REG05__PAGEGRAIN 1 317 #define CP0_REG05__SEGCTL0 2 318 #define CP0_REG05__SEGCTL1 3 319 #define CP0_REG05__SEGCTL2 4 320 #define CP0_REG05__PWBASE 5 321 #define CP0_REG05__PWFIELD 6 322 #define CP0_REG05__PWSIZE 7 323 /* CP0 Register 06 */ 324 #define CP0_REG06__WIRED 0 325 #define CP0_REG06__SRSCONF0 1 326 #define CP0_REG06__SRSCONF1 2 327 #define CP0_REG06__SRSCONF2 3 328 #define CP0_REG06__SRSCONF3 4 329 #define CP0_REG06__SRSCONF4 5 330 #define CP0_REG06__PWCTL 6 331 /* CP0 Register 07 */ 332 #define CP0_REG07__HWRENA 0 333 /* CP0 Register 08 */ 334 #define CP0_REG08__BADVADDR 0 335 #define CP0_REG08__BADINSTR 1 336 #define CP0_REG08__BADINSTRP 2 337 #define CP0_REG08__BADINSTRX 3 338 /* CP0 Register 09 */ 339 #define CP0_REG09__COUNT 0 340 #define CP0_REG09__SAARI 6 341 #define CP0_REG09__SAAR 7 342 /* CP0 Register 10 */ 343 #define CP0_REG10__ENTRYHI 0 344 #define CP0_REG10__GUESTCTL1 4 345 #define CP0_REG10__GUESTCTL2 5 346 #define CP0_REG10__GUESTCTL3 6 347 /* CP0 Register 11 */ 348 #define CP0_REG11__COMPARE 0 349 #define CP0_REG11__GUESTCTL0EXT 4 350 /* CP0 Register 12 */ 351 #define CP0_REG12__STATUS 0 352 #define CP0_REG12__INTCTL 1 353 #define CP0_REG12__SRSCTL 2 354 #define CP0_REG12__SRSMAP 3 355 #define CP0_REG12__VIEW_IPL 4 356 #define CP0_REG12__SRSMAP2 5 357 #define CP0_REG12__GUESTCTL0 6 358 #define CP0_REG12__GTOFFSET 7 359 /* CP0 Register 13 */ 360 #define CP0_REG13__CAUSE 0 361 #define CP0_REG13__VIEW_RIPL 4 362 #define CP0_REG13__NESTEDEXC 5 363 /* CP0 Register 14 */ 364 #define CP0_REG14__EPC 0 365 #define CP0_REG14__NESTEDEPC 2 366 /* CP0 Register 15 */ 367 #define CP0_REG15__PRID 0 368 #define CP0_REG15__EBASE 1 369 #define CP0_REG15__CDMMBASE 2 370 #define CP0_REG15__CMGCRBASE 3 371 #define CP0_REG15__BEVVA 4 372 /* CP0 Register 16 */ 373 #define CP0_REG16__CONFIG 0 374 #define CP0_REG16__CONFIG1 1 375 #define CP0_REG16__CONFIG2 2 376 #define CP0_REG16__CONFIG3 3 377 #define CP0_REG16__CONFIG4 4 378 #define CP0_REG16__CONFIG5 5 379 #define CP0_REG16__CONFIG6 6 380 #define CP0_REG16__CONFIG7 7 381 /* CP0 Register 17 */ 382 #define CP0_REG17__LLADDR 0 383 #define CP0_REG17__MAAR 1 384 #define CP0_REG17__MAARI 2 385 /* CP0 Register 18 */ 386 #define CP0_REG18__WATCHLO0 0 387 #define CP0_REG18__WATCHLO1 1 388 #define CP0_REG18__WATCHLO2 2 389 #define CP0_REG18__WATCHLO3 3 390 #define CP0_REG18__WATCHLO4 4 391 #define CP0_REG18__WATCHLO5 5 392 #define CP0_REG18__WATCHLO6 6 393 #define CP0_REG18__WATCHLO7 7 394 /* CP0 Register 19 */ 395 #define CP0_REG19__WATCHHI0 0 396 #define CP0_REG19__WATCHHI1 1 397 #define CP0_REG19__WATCHHI2 2 398 #define CP0_REG19__WATCHHI3 3 399 #define CP0_REG19__WATCHHI4 4 400 #define CP0_REG19__WATCHHI5 5 401 #define CP0_REG19__WATCHHI6 6 402 #define CP0_REG19__WATCHHI7 7 403 /* CP0 Register 20 */ 404 #define CP0_REG20__XCONTEXT 0 405 /* CP0 Register 21 */ 406 /* CP0 Register 22 */ 407 /* CP0 Register 23 */ 408 #define CP0_REG23__DEBUG 0 409 #define CP0_REG23__TRACECONTROL 1 410 #define CP0_REG23__TRACECONTROL2 2 411 #define CP0_REG23__USERTRACEDATA1 3 412 #define CP0_REG23__TRACEIBPC 4 413 #define CP0_REG23__TRACEDBPC 5 414 #define CP0_REG23__DEBUG2 6 415 /* CP0 Register 24 */ 416 #define CP0_REG24__DEPC 0 417 /* CP0 Register 25 */ 418 #define CP0_REG25__PERFCTL0 0 419 #define CP0_REG25__PERFCNT0 1 420 #define CP0_REG25__PERFCTL1 2 421 #define CP0_REG25__PERFCNT1 3 422 #define CP0_REG25__PERFCTL2 4 423 #define CP0_REG25__PERFCNT2 5 424 #define CP0_REG25__PERFCTL3 6 425 #define CP0_REG25__PERFCNT3 7 426 /* CP0 Register 26 */ 427 #define CP0_REG26__ERRCTL 0 428 /* CP0 Register 27 */ 429 #define CP0_REG27__CACHERR 0 430 /* CP0 Register 28 */ 431 #define CP0_REG28__TAGLO 0 432 #define CP0_REG28__DATALO 1 433 #define CP0_REG28__TAGLO1 2 434 #define CP0_REG28__DATALO1 3 435 #define CP0_REG28__TAGLO2 4 436 #define CP0_REG28__DATALO2 5 437 #define CP0_REG28__TAGLO3 6 438 #define CP0_REG28__DATALO3 7 439 /* CP0 Register 29 */ 440 #define CP0_REG29__TAGHI 0 441 #define CP0_REG29__DATAHI 1 442 #define CP0_REG29__TAGHI1 2 443 #define CP0_REG29__DATAHI1 3 444 #define CP0_REG29__TAGHI2 4 445 #define CP0_REG29__DATAHI2 5 446 #define CP0_REG29__TAGHI3 6 447 #define CP0_REG29__DATAHI3 7 448 /* CP0 Register 30 */ 449 #define CP0_REG30__ERROREPC 0 450 /* CP0 Register 31 */ 451 #define CP0_REG31__DESAVE 0 452 #define CP0_REG31__KSCRATCH1 2 453 #define CP0_REG31__KSCRATCH2 3 454 #define CP0_REG31__KSCRATCH3 4 455 #define CP0_REG31__KSCRATCH4 5 456 #define CP0_REG31__KSCRATCH5 6 457 #define CP0_REG31__KSCRATCH6 7 458 459 460 typedef struct TCState TCState; 461 struct TCState { 462 target_ulong gpr[32]; 463 #if defined(TARGET_MIPS64) 464 /* 465 * For CPUs using 128-bit GPR registers, we put the lower halves in gpr[]) 466 * and the upper halves in gpr_hi[]. 467 */ 468 uint64_t gpr_hi[32]; 469 #endif /* TARGET_MIPS64 */ 470 target_ulong PC; 471 target_ulong HI[MIPS_DSP_ACC]; 472 target_ulong LO[MIPS_DSP_ACC]; 473 target_ulong ACX[MIPS_DSP_ACC]; 474 target_ulong DSPControl; 475 int32_t CP0_TCStatus; 476 #define CP0TCSt_TCU3 31 477 #define CP0TCSt_TCU2 30 478 #define CP0TCSt_TCU1 29 479 #define CP0TCSt_TCU0 28 480 #define CP0TCSt_TMX 27 481 #define CP0TCSt_RNST 23 482 #define CP0TCSt_TDS 21 483 #define CP0TCSt_DT 20 484 #define CP0TCSt_DA 15 485 #define CP0TCSt_A 13 486 #define CP0TCSt_TKSU 11 487 #define CP0TCSt_IXMT 10 488 #define CP0TCSt_TASID 0 489 int32_t CP0_TCBind; 490 #define CP0TCBd_CurTC 21 491 #define CP0TCBd_TBE 17 492 #define CP0TCBd_CurVPE 0 493 target_ulong CP0_TCHalt; 494 target_ulong CP0_TCContext; 495 target_ulong CP0_TCSchedule; 496 target_ulong CP0_TCScheFBack; 497 int32_t CP0_Debug_tcstatus; 498 target_ulong CP0_UserLocal; 499 500 int32_t msacsr; 501 502 #define MSACSR_FS 24 503 #define MSACSR_FS_MASK (1 << MSACSR_FS) 504 #define MSACSR_NX 18 505 #define MSACSR_NX_MASK (1 << MSACSR_NX) 506 #define MSACSR_CEF 2 507 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF) 508 #define MSACSR_RM 0 509 #define MSACSR_RM_MASK (0x3 << MSACSR_RM) 510 #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \ 511 MSACSR_FS_MASK) 512 513 float_status msa_fp_status; 514 515 #define NUMBER_OF_MXU_REGISTERS 16 516 target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; 517 target_ulong mxu_cr; 518 #define MXU_CR_LC 31 519 #define MXU_CR_RC 30 520 #define MXU_CR_BIAS 2 521 #define MXU_CR_RD_EN 1 522 #define MXU_CR_MXU_EN 0 523 524 }; 525 526 struct MIPSITUState; 527 typedef struct CPUArchState { 528 TCState active_tc; 529 CPUMIPSFPUContext active_fpu; 530 531 uint32_t current_tc; 532 uint32_t current_fpu; 533 534 uint32_t SEGBITS; 535 uint32_t PABITS; 536 #if defined(TARGET_MIPS64) 537 # define PABITS_BASE 36 538 #else 539 # define PABITS_BASE 32 540 #endif 541 target_ulong SEGMask; 542 uint64_t PAMask; 543 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1) 544 545 int32_t msair; 546 #define MSAIR_ProcID 8 547 #define MSAIR_Rev 0 548 549 /* 550 * CP0 Register 0 551 */ 552 int32_t CP0_Index; 553 /* CP0_MVP* are per MVP registers. */ 554 int32_t CP0_VPControl; 555 #define CP0VPCtl_DIS 0 556 /* 557 * CP0 Register 1 558 */ 559 int32_t CP0_Random; 560 int32_t CP0_VPEControl; 561 #define CP0VPECo_YSI 21 562 #define CP0VPECo_GSI 20 563 #define CP0VPECo_EXCPT 16 564 #define CP0VPECo_TE 15 565 #define CP0VPECo_TargTC 0 566 int32_t CP0_VPEConf0; 567 #define CP0VPEC0_M 31 568 #define CP0VPEC0_XTC 21 569 #define CP0VPEC0_TCS 19 570 #define CP0VPEC0_SCS 18 571 #define CP0VPEC0_DSC 17 572 #define CP0VPEC0_ICS 16 573 #define CP0VPEC0_MVP 1 574 #define CP0VPEC0_VPA 0 575 int32_t CP0_VPEConf1; 576 #define CP0VPEC1_NCX 20 577 #define CP0VPEC1_NCP2 10 578 #define CP0VPEC1_NCP1 0 579 target_ulong CP0_YQMask; 580 target_ulong CP0_VPESchedule; 581 target_ulong CP0_VPEScheFBack; 582 int32_t CP0_VPEOpt; 583 #define CP0VPEOpt_IWX7 15 584 #define CP0VPEOpt_IWX6 14 585 #define CP0VPEOpt_IWX5 13 586 #define CP0VPEOpt_IWX4 12 587 #define CP0VPEOpt_IWX3 11 588 #define CP0VPEOpt_IWX2 10 589 #define CP0VPEOpt_IWX1 9 590 #define CP0VPEOpt_IWX0 8 591 #define CP0VPEOpt_DWX7 7 592 #define CP0VPEOpt_DWX6 6 593 #define CP0VPEOpt_DWX5 5 594 #define CP0VPEOpt_DWX4 4 595 #define CP0VPEOpt_DWX3 3 596 #define CP0VPEOpt_DWX2 2 597 #define CP0VPEOpt_DWX1 1 598 #define CP0VPEOpt_DWX0 0 599 /* 600 * CP0 Register 2 601 */ 602 uint64_t CP0_EntryLo0; 603 /* 604 * CP0 Register 3 605 */ 606 uint64_t CP0_EntryLo1; 607 #if defined(TARGET_MIPS64) 608 # define CP0EnLo_RI 63 609 # define CP0EnLo_XI 62 610 #else 611 # define CP0EnLo_RI 31 612 # define CP0EnLo_XI 30 613 #endif 614 int32_t CP0_GlobalNumber; 615 #define CP0GN_VPId 0 616 /* 617 * CP0 Register 4 618 */ 619 target_ulong CP0_Context; 620 int32_t CP0_MemoryMapID; 621 /* 622 * CP0 Register 5 623 */ 624 int32_t CP0_PageMask; 625 #define CP0PM_MASK 13 626 int32_t CP0_PageGrain_rw_bitmask; 627 int32_t CP0_PageGrain; 628 #define CP0PG_RIE 31 629 #define CP0PG_XIE 30 630 #define CP0PG_ELPA 29 631 #define CP0PG_IEC 27 632 target_ulong CP0_SegCtl0; 633 target_ulong CP0_SegCtl1; 634 target_ulong CP0_SegCtl2; 635 #define CP0SC_PA 9 636 #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA) 637 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA) 638 #define CP0SC_AM 4 639 #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM) 640 #define CP0SC_AM_UK 0ULL 641 #define CP0SC_AM_MK 1ULL 642 #define CP0SC_AM_MSK 2ULL 643 #define CP0SC_AM_MUSK 3ULL 644 #define CP0SC_AM_MUSUK 4ULL 645 #define CP0SC_AM_USK 5ULL 646 #define CP0SC_AM_UUSK 7ULL 647 #define CP0SC_EU 3 648 #define CP0SC_EU_MASK (1ULL << CP0SC_EU) 649 #define CP0SC_C 0 650 #define CP0SC_C_MASK (0x7ULL << CP0SC_C) 651 #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ 652 CP0SC_PA_MASK) 653 #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ 654 CP0SC_PA_1GMASK) 655 #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16)) 656 #define CP0SC1_XAM 59 657 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM) 658 #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK) 659 #define CP0SC2_XR 56 660 #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR) 661 #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK) 662 target_ulong CP0_PWBase; 663 target_ulong CP0_PWField; 664 #if defined(TARGET_MIPS64) 665 #define CP0PF_BDI 32 /* 37..32 */ 666 #define CP0PF_GDI 24 /* 29..24 */ 667 #define CP0PF_UDI 18 /* 23..18 */ 668 #define CP0PF_MDI 12 /* 17..12 */ 669 #define CP0PF_PTI 6 /* 11..6 */ 670 #define CP0PF_PTEI 0 /* 5..0 */ 671 #else 672 #define CP0PF_GDW 24 /* 29..24 */ 673 #define CP0PF_UDW 18 /* 23..18 */ 674 #define CP0PF_MDW 12 /* 17..12 */ 675 #define CP0PF_PTW 6 /* 11..6 */ 676 #define CP0PF_PTEW 0 /* 5..0 */ 677 #endif 678 target_ulong CP0_PWSize; 679 #if defined(TARGET_MIPS64) 680 #define CP0PS_BDW 32 /* 37..32 */ 681 #endif 682 #define CP0PS_PS 30 683 #define CP0PS_GDW 24 /* 29..24 */ 684 #define CP0PS_UDW 18 /* 23..18 */ 685 #define CP0PS_MDW 12 /* 17..12 */ 686 #define CP0PS_PTW 6 /* 11..6 */ 687 #define CP0PS_PTEW 0 /* 5..0 */ 688 /* 689 * CP0 Register 6 690 */ 691 int32_t CP0_Wired; 692 int32_t CP0_PWCtl; 693 #define CP0PC_PWEN 31 694 #if defined(TARGET_MIPS64) 695 #define CP0PC_PWDIREXT 30 696 #define CP0PC_XK 28 697 #define CP0PC_XS 27 698 #define CP0PC_XU 26 699 #endif 700 #define CP0PC_DPH 7 701 #define CP0PC_HUGEPG 6 702 #define CP0PC_PSN 0 /* 5..0 */ 703 int32_t CP0_SRSConf0_rw_bitmask; 704 int32_t CP0_SRSConf0; 705 #define CP0SRSC0_M 31 706 #define CP0SRSC0_SRS3 20 707 #define CP0SRSC0_SRS2 10 708 #define CP0SRSC0_SRS1 0 709 int32_t CP0_SRSConf1_rw_bitmask; 710 int32_t CP0_SRSConf1; 711 #define CP0SRSC1_M 31 712 #define CP0SRSC1_SRS6 20 713 #define CP0SRSC1_SRS5 10 714 #define CP0SRSC1_SRS4 0 715 int32_t CP0_SRSConf2_rw_bitmask; 716 int32_t CP0_SRSConf2; 717 #define CP0SRSC2_M 31 718 #define CP0SRSC2_SRS9 20 719 #define CP0SRSC2_SRS8 10 720 #define CP0SRSC2_SRS7 0 721 int32_t CP0_SRSConf3_rw_bitmask; 722 int32_t CP0_SRSConf3; 723 #define CP0SRSC3_M 31 724 #define CP0SRSC3_SRS12 20 725 #define CP0SRSC3_SRS11 10 726 #define CP0SRSC3_SRS10 0 727 int32_t CP0_SRSConf4_rw_bitmask; 728 int32_t CP0_SRSConf4; 729 #define CP0SRSC4_SRS15 20 730 #define CP0SRSC4_SRS14 10 731 #define CP0SRSC4_SRS13 0 732 /* 733 * CP0 Register 7 734 */ 735 int32_t CP0_HWREna; 736 /* 737 * CP0 Register 8 738 */ 739 target_ulong CP0_BadVAddr; 740 uint32_t CP0_BadInstr; 741 uint32_t CP0_BadInstrP; 742 uint32_t CP0_BadInstrX; 743 /* 744 * CP0 Register 9 745 */ 746 int32_t CP0_Count; 747 uint32_t CP0_SAARI; 748 #define CP0SAARI_TARGET 0 /* 5..0 */ 749 uint64_t CP0_SAAR[2]; 750 #define CP0SAAR_BASE 12 /* 43..12 */ 751 #define CP0SAAR_SIZE 1 /* 5..1 */ 752 #define CP0SAAR_EN 0 753 /* 754 * CP0 Register 10 755 */ 756 target_ulong CP0_EntryHi; 757 #define CP0EnHi_EHINV 10 758 target_ulong CP0_EntryHi_ASID_mask; 759 /* 760 * CP0 Register 11 761 */ 762 int32_t CP0_Compare; 763 /* 764 * CP0 Register 12 765 */ 766 int32_t CP0_Status; 767 #define CP0St_CU3 31 768 #define CP0St_CU2 30 769 #define CP0St_CU1 29 770 #define CP0St_CU0 28 771 #define CP0St_RP 27 772 #define CP0St_FR 26 773 #define CP0St_RE 25 774 #define CP0St_MX 24 775 #define CP0St_PX 23 776 #define CP0St_BEV 22 777 #define CP0St_TS 21 778 #define CP0St_SR 20 779 #define CP0St_NMI 19 780 #define CP0St_IM 8 781 #define CP0St_KX 7 782 #define CP0St_SX 6 783 #define CP0St_UX 5 784 #define CP0St_KSU 3 785 #define CP0St_ERL 2 786 #define CP0St_EXL 1 787 #define CP0St_IE 0 788 int32_t CP0_IntCtl; 789 #define CP0IntCtl_IPTI 29 790 #define CP0IntCtl_IPPCI 26 791 #define CP0IntCtl_VS 5 792 int32_t CP0_SRSCtl; 793 #define CP0SRSCtl_HSS 26 794 #define CP0SRSCtl_EICSS 18 795 #define CP0SRSCtl_ESS 12 796 #define CP0SRSCtl_PSS 6 797 #define CP0SRSCtl_CSS 0 798 int32_t CP0_SRSMap; 799 #define CP0SRSMap_SSV7 28 800 #define CP0SRSMap_SSV6 24 801 #define CP0SRSMap_SSV5 20 802 #define CP0SRSMap_SSV4 16 803 #define CP0SRSMap_SSV3 12 804 #define CP0SRSMap_SSV2 8 805 #define CP0SRSMap_SSV1 4 806 #define CP0SRSMap_SSV0 0 807 /* 808 * CP0 Register 13 809 */ 810 int32_t CP0_Cause; 811 #define CP0Ca_BD 31 812 #define CP0Ca_TI 30 813 #define CP0Ca_CE 28 814 #define CP0Ca_DC 27 815 #define CP0Ca_PCI 26 816 #define CP0Ca_IV 23 817 #define CP0Ca_WP 22 818 #define CP0Ca_IP 8 819 #define CP0Ca_IP_mask 0x0000FF00 820 #define CP0Ca_EC 2 821 /* 822 * CP0 Register 14 823 */ 824 target_ulong CP0_EPC; 825 /* 826 * CP0 Register 15 827 */ 828 int32_t CP0_PRid; 829 target_ulong CP0_EBase; 830 target_ulong CP0_EBaseWG_rw_bitmask; 831 #define CP0EBase_WG 11 832 target_ulong CP0_CMGCRBase; 833 /* 834 * CP0 Register 16 (after Release 1) 835 */ 836 int32_t CP0_Config0; 837 #define CP0C0_M 31 838 #define CP0C0_K23 28 /* 30..28 */ 839 #define CP0C0_KU 25 /* 27..25 */ 840 #define CP0C0_MDU 20 841 #define CP0C0_MM 18 842 #define CP0C0_BM 16 843 #define CP0C0_Impl 16 /* 24..16 */ 844 #define CP0C0_BE 15 845 #define CP0C0_AT 13 /* 14..13 */ 846 #define CP0C0_AR 10 /* 12..10 */ 847 #define CP0C0_MT 7 /* 9..7 */ 848 #define CP0C0_VI 3 849 #define CP0C0_K0 0 /* 2..0 */ 850 #define CP0C0_AR_LENGTH 3 851 /* 852 * CP0 Register 16 (before Release 1) 853 */ 854 #define CP0C0_Impl 16 /* 24..16 */ 855 #define CP0C0_IC 9 /* 11..9 */ 856 #define CP0C0_DC 6 /* 8..6 */ 857 #define CP0C0_IB 5 858 #define CP0C0_DB 4 859 int32_t CP0_Config1; 860 #define CP0C1_M 31 861 #define CP0C1_MMU 25 /* 30..25 */ 862 #define CP0C1_IS 22 /* 24..22 */ 863 #define CP0C1_IL 19 /* 21..19 */ 864 #define CP0C1_IA 16 /* 18..16 */ 865 #define CP0C1_DS 13 /* 15..13 */ 866 #define CP0C1_DL 10 /* 12..10 */ 867 #define CP0C1_DA 7 /* 9..7 */ 868 #define CP0C1_C2 6 869 #define CP0C1_MD 5 870 #define CP0C1_PC 4 871 #define CP0C1_WR 3 872 #define CP0C1_CA 2 873 #define CP0C1_EP 1 874 #define CP0C1_FP 0 875 int32_t CP0_Config2; 876 #define CP0C2_M 31 877 #define CP0C2_TU 28 /* 30..28 */ 878 #define CP0C2_TS 24 /* 27..24 */ 879 #define CP0C2_TL 20 /* 23..20 */ 880 #define CP0C2_TA 16 /* 19..16 */ 881 #define CP0C2_SU 12 /* 15..12 */ 882 #define CP0C2_SS 8 /* 11..8 */ 883 #define CP0C2_SL 4 /* 7..4 */ 884 #define CP0C2_SA 0 /* 3..0 */ 885 int32_t CP0_Config3; 886 #define CP0C3_M 31 887 #define CP0C3_BPG 30 888 #define CP0C3_CMGCR 29 889 #define CP0C3_MSAP 28 890 #define CP0C3_BP 27 891 #define CP0C3_BI 26 892 #define CP0C3_SC 25 893 #define CP0C3_PW 24 894 #define CP0C3_VZ 23 895 #define CP0C3_IPLV 21 /* 22..21 */ 896 #define CP0C3_MMAR 18 /* 20..18 */ 897 #define CP0C3_MCU 17 898 #define CP0C3_ISA_ON_EXC 16 899 #define CP0C3_ISA 14 /* 15..14 */ 900 #define CP0C3_ULRI 13 901 #define CP0C3_RXI 12 902 #define CP0C3_DSP2P 11 903 #define CP0C3_DSPP 10 904 #define CP0C3_CTXTC 9 905 #define CP0C3_ITL 8 906 #define CP0C3_LPA 7 907 #define CP0C3_VEIC 6 908 #define CP0C3_VInt 5 909 #define CP0C3_SP 4 910 #define CP0C3_CDMM 3 911 #define CP0C3_MT 2 912 #define CP0C3_SM 1 913 #define CP0C3_TL 0 914 int32_t CP0_Config4; 915 int32_t CP0_Config4_rw_bitmask; 916 #define CP0C4_M 31 917 #define CP0C4_IE 29 /* 30..29 */ 918 #define CP0C4_AE 28 919 #define CP0C4_VTLBSizeExt 24 /* 27..24 */ 920 #define CP0C4_KScrExist 16 921 #define CP0C4_MMUExtDef 14 922 #define CP0C4_FTLBPageSize 8 /* 12..8 */ 923 /* bit layout if MMUExtDef=1 */ 924 #define CP0C4_MMUSizeExt 0 /* 7..0 */ 925 /* bit layout if MMUExtDef=2 */ 926 #define CP0C4_FTLBWays 4 /* 7..4 */ 927 #define CP0C4_FTLBSets 0 /* 3..0 */ 928 int32_t CP0_Config5; 929 int32_t CP0_Config5_rw_bitmask; 930 #define CP0C5_M 31 931 #define CP0C5_K 30 932 #define CP0C5_CV 29 933 #define CP0C5_EVA 28 934 #define CP0C5_MSAEn 27 935 #define CP0C5_PMJ 23 /* 25..23 */ 936 #define CP0C5_WR2 22 937 #define CP0C5_NMS 21 938 #define CP0C5_ULS 20 939 #define CP0C5_XPA 19 940 #define CP0C5_CRCP 18 941 #define CP0C5_MI 17 942 #define CP0C5_GI 15 /* 16..15 */ 943 #define CP0C5_CA2 14 944 #define CP0C5_XNP 13 945 #define CP0C5_DEC 11 946 #define CP0C5_L2C 10 947 #define CP0C5_UFE 9 948 #define CP0C5_FRE 8 949 #define CP0C5_VP 7 950 #define CP0C5_SBRI 6 951 #define CP0C5_MVH 5 952 #define CP0C5_LLB 4 953 #define CP0C5_MRP 3 954 #define CP0C5_UFR 2 955 #define CP0C5_NFExists 0 956 int32_t CP0_Config6; 957 int32_t CP0_Config6_rw_bitmask; 958 #define CP0C6_BPPASS 31 959 #define CP0C6_KPOS 24 960 #define CP0C6_KE 23 961 #define CP0C6_VTLBONLY 22 962 #define CP0C6_LASX 21 963 #define CP0C6_SSEN 20 964 #define CP0C6_DISDRTIME 19 965 #define CP0C6_PIXNUEN 18 966 #define CP0C6_SCRAND 17 967 #define CP0C6_LLEXCEN 16 968 #define CP0C6_DISVC 15 969 #define CP0C6_VCLRU 14 970 #define CP0C6_DCLRU 13 971 #define CP0C6_PIXUEN 12 972 #define CP0C6_DISBLKLYEN 11 973 #define CP0C6_UMEMUALEN 10 974 #define CP0C6_SFBEN 8 975 #define CP0C6_FLTINT 7 976 #define CP0C6_VLTINT 6 977 #define CP0C6_DISBTB 5 978 #define CP0C6_STPREFCTL 2 979 #define CP0C6_INSTPREF 1 980 #define CP0C6_DATAPREF 0 981 int32_t CP0_Config7; 982 int64_t CP0_Config7_rw_bitmask; 983 #define CP0C7_NAPCGEN 2 984 #define CP0C7_UNIMUEN 1 985 #define CP0C7_VFPUCGEN 0 986 uint64_t CP0_LLAddr; 987 uint64_t CP0_MAAR[MIPS_MAAR_MAX]; 988 int32_t CP0_MAARI; 989 /* XXX: Maybe make LLAddr per-TC? */ 990 /* 991 * CP0 Register 17 992 */ 993 target_ulong lladdr; /* LL virtual address compared against SC */ 994 target_ulong llval; 995 uint64_t llval_wp; 996 uint32_t llnewval_wp; 997 uint64_t CP0_LLAddr_rw_bitmask; 998 int CP0_LLAddr_shift; 999 /* 1000 * CP0 Register 18 1001 */ 1002 target_ulong CP0_WatchLo[8]; 1003 /* 1004 * CP0 Register 19 1005 */ 1006 uint64_t CP0_WatchHi[8]; 1007 #define CP0WH_ASID 16 1008 /* 1009 * CP0 Register 20 1010 */ 1011 target_ulong CP0_XContext; 1012 int32_t CP0_Framemask; 1013 /* 1014 * CP0 Register 23 1015 */ 1016 int32_t CP0_Debug; 1017 #define CP0DB_DBD 31 1018 #define CP0DB_DM 30 1019 #define CP0DB_LSNM 28 1020 #define CP0DB_Doze 27 1021 #define CP0DB_Halt 26 1022 #define CP0DB_CNT 25 1023 #define CP0DB_IBEP 24 1024 #define CP0DB_DBEP 21 1025 #define CP0DB_IEXI 20 1026 #define CP0DB_VER 15 1027 #define CP0DB_DEC 10 1028 #define CP0DB_SSt 8 1029 #define CP0DB_DINT 5 1030 #define CP0DB_DIB 4 1031 #define CP0DB_DDBS 3 1032 #define CP0DB_DDBL 2 1033 #define CP0DB_DBp 1 1034 #define CP0DB_DSS 0 1035 /* 1036 * CP0 Register 24 1037 */ 1038 target_ulong CP0_DEPC; 1039 /* 1040 * CP0 Register 25 1041 */ 1042 int32_t CP0_Performance0; 1043 /* 1044 * CP0 Register 26 1045 */ 1046 int32_t CP0_ErrCtl; 1047 #define CP0EC_WST 29 1048 #define CP0EC_SPR 28 1049 #define CP0EC_ITC 26 1050 /* 1051 * CP0 Register 28 1052 */ 1053 uint64_t CP0_TagLo; 1054 int32_t CP0_DataLo; 1055 /* 1056 * CP0 Register 29 1057 */ 1058 int32_t CP0_TagHi; 1059 int32_t CP0_DataHi; 1060 /* 1061 * CP0 Register 30 1062 */ 1063 target_ulong CP0_ErrorEPC; 1064 /* 1065 * CP0 Register 31 1066 */ 1067 int32_t CP0_DESAVE; 1068 target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; 1069 1070 /* We waste some space so we can handle shadow registers like TCs. */ 1071 TCState tcs[MIPS_SHADOW_SET_MAX]; 1072 CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; 1073 /* QEMU */ 1074 int error_code; 1075 #define EXCP_TLB_NOMATCH 0x1 1076 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ 1077 uint32_t hflags; /* CPU State */ 1078 /* TMASK defines different execution modes */ 1079 #define MIPS_HFLAG_TMASK 0x1F5807FF 1080 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ 1081 /* 1082 * The KSU flags must be the lowest bits in hflags. The flag order 1083 * must be the same as defined for CP0 Status. This allows to use 1084 * the bits as the value of mmu_idx. 1085 */ 1086 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ 1087 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ 1088 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ 1089 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ 1090 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ 1091 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ 1092 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ 1093 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ 1094 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ 1095 /* 1096 * True if the MIPS IV COP1X instructions can be used. This also 1097 * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S 1098 * and RSQRT.D. 1099 */ 1100 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ 1101 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ 1102 #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ 1103 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ 1104 #define MIPS_HFLAG_M16_SHIFT 10 1105 /* 1106 * If translation is interrupted between the branch instruction and 1107 * the delay slot, record what type of branch it is so that we can 1108 * resume translation properly. It might be possible to reduce 1109 * this from three bits to two. 1110 */ 1111 #define MIPS_HFLAG_BMASK_BASE 0x803800 1112 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ 1113 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ 1114 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ 1115 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ 1116 /* Extra flags about the current pending branch. */ 1117 #define MIPS_HFLAG_BMASK_EXT 0x7C000 1118 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ 1119 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ 1120 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ 1121 #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */ 1122 #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */ 1123 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) 1124 /* MIPS DSP resources access. */ 1125 #define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */ 1126 #define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */ 1127 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */ 1128 /* Extra flag about HWREna register. */ 1129 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ 1130 #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */ 1131 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */ 1132 #define MIPS_HFLAG_MSA 0x1000000 1133 #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */ 1134 #define MIPS_HFLAG_ELPA 0x4000000 1135 #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */ 1136 #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */ 1137 target_ulong btarget; /* Jump / branch target */ 1138 target_ulong bcond; /* Branch condition (if needed) */ 1139 1140 int SYNCI_Step; /* Address step size for SYNCI */ 1141 int CCRes; /* Cycle count resolution/divisor */ 1142 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ 1143 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ 1144 uint64_t insn_flags; /* Supported instruction set */ 1145 int saarp; 1146 1147 /* Fields up to this point are cleared by a CPU reset */ 1148 struct {} end_reset_fields; 1149 1150 /* Fields from here on are preserved across CPU reset. */ 1151 CPUMIPSMVPContext *mvp; 1152 #if !defined(CONFIG_USER_ONLY) 1153 CPUMIPSTLBContext *tlb; 1154 void *irq[8]; 1155 struct MIPSITUState *itu; 1156 MemoryRegion *itc_tag; /* ITC Configuration Tags */ 1157 #endif 1158 1159 const mips_def_t *cpu_model; 1160 QEMUTimer *timer; /* Internal timer */ 1161 target_ulong exception_base; /* ExceptionBase input to the core */ 1162 uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */ 1163 } CPUMIPSState; 1164 1165 /** 1166 * MIPSCPU: 1167 * @env: #CPUMIPSState 1168 * @clock: this CPU input clock (may be connected 1169 * to an output clock from another device). 1170 * 1171 * A MIPS CPU. 1172 */ 1173 struct ArchCPU { 1174 /*< private >*/ 1175 CPUState parent_obj; 1176 /*< public >*/ 1177 1178 Clock *clock; 1179 CPUNegativeOffsetState neg; 1180 CPUMIPSState env; 1181 }; 1182 1183 1184 void mips_cpu_list(void); 1185 1186 #define cpu_list mips_cpu_list 1187 1188 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); 1189 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); 1190 1191 /* 1192 * MMU modes definitions. We carefully match the indices with our 1193 * hflags layout. 1194 */ 1195 #define MMU_USER_IDX 2 1196 1197 static inline int hflags_mmu_index(uint32_t hflags) 1198 { 1199 if (hflags & MIPS_HFLAG_ERL) { 1200 return 3; /* ERL */ 1201 } else { 1202 return hflags & MIPS_HFLAG_KSU; 1203 } 1204 } 1205 1206 static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) 1207 { 1208 return hflags_mmu_index(env->hflags); 1209 } 1210 1211 #include "exec/cpu-all.h" 1212 1213 /* Exceptions */ 1214 enum { 1215 EXCP_NONE = -1, 1216 EXCP_RESET = 0, 1217 EXCP_SRESET, 1218 EXCP_DSS, 1219 EXCP_DINT, 1220 EXCP_DDBL, 1221 EXCP_DDBS, 1222 EXCP_NMI, 1223 EXCP_MCHECK, 1224 EXCP_EXT_INTERRUPT, /* 8 */ 1225 EXCP_DFWATCH, 1226 EXCP_DIB, 1227 EXCP_IWATCH, 1228 EXCP_AdEL, 1229 EXCP_AdES, 1230 EXCP_TLBF, 1231 EXCP_IBE, 1232 EXCP_DBp, /* 16 */ 1233 EXCP_SYSCALL, 1234 EXCP_BREAK, 1235 EXCP_CpU, 1236 EXCP_RI, 1237 EXCP_OVERFLOW, 1238 EXCP_TRAP, 1239 EXCP_FPE, 1240 EXCP_DWATCH, /* 24 */ 1241 EXCP_LTLBL, 1242 EXCP_TLBL, 1243 EXCP_TLBS, 1244 EXCP_DBE, 1245 EXCP_THREAD, 1246 EXCP_MDMX, 1247 EXCP_C2E, 1248 EXCP_CACHE, /* 32 */ 1249 EXCP_DSPDIS, 1250 EXCP_MSADIS, 1251 EXCP_MSAFPE, 1252 EXCP_TLBXI, 1253 EXCP_TLBRI, 1254 1255 EXCP_LAST = EXCP_TLBRI, 1256 }; 1257 1258 /* 1259 * This is an internally generated WAKE request line. 1260 * It is driven by the CPU itself. Raised when the MT 1261 * block wants to wake a VPE from an inactive state and 1262 * cleared when VPE goes from active to inactive. 1263 */ 1264 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 1265 1266 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU 1267 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX 1268 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU 1269 1270 bool cpu_type_supports_cps_smp(const char *cpu_type); 1271 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); 1272 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); 1273 1274 /* Check presence of MSA implementation */ 1275 static inline bool ase_msa_available(CPUMIPSState *env) 1276 { 1277 return env->CP0_Config3 & (1 << CP0C3_MSAP); 1278 } 1279 1280 /* Check presence of multi-threading ASE implementation */ 1281 static inline bool ase_mt_available(CPUMIPSState *env) 1282 { 1283 return env->CP0_Config3 & (1 << CP0C3_MT); 1284 } 1285 1286 static inline bool cpu_type_is_64bit(const char *cpu_type) 1287 { 1288 return cpu_type_supports_isa(cpu_type, CPU_MIPS64); 1289 } 1290 1291 void cpu_set_exception_base(int vp_index, target_ulong address); 1292 1293 /* addr.c */ 1294 uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr); 1295 uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); 1296 1297 uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr); 1298 uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr); 1299 uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr); 1300 bool mips_um_ksegs_enabled(void); 1301 void mips_um_ksegs_enable(void); 1302 1303 #if !defined(CONFIG_USER_ONLY) 1304 1305 /* mips_int.c */ 1306 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); 1307 1308 /* mips_itu.c */ 1309 void itc_reconfigure(struct MIPSITUState *tag); 1310 1311 #endif /* !CONFIG_USER_ONLY */ 1312 1313 /* helper.c */ 1314 target_ulong exception_resume_pc(CPUMIPSState *env); 1315 1316 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, 1317 target_ulong *cs_base, uint32_t *flags) 1318 { 1319 *pc = env->active_tc.PC; 1320 *cs_base = 0; 1321 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | 1322 MIPS_HFLAG_HWRENA_ULR); 1323 } 1324 1325 /** 1326 * mips_cpu_create_with_clock: 1327 * @typename: a MIPS CPU type. 1328 * @cpu_refclk: this cpu input clock (an output clock of another device) 1329 * 1330 * Instantiates a MIPS CPU, set the input clock of the CPU to @cpu_refclk, 1331 * then realizes the CPU. 1332 * 1333 * Returns: A #CPUState or %NULL if an error occurred. 1334 */ 1335 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk); 1336 1337 #endif /* MIPS_CPU_H */ 1338