xref: /openbmc/qemu/target/mips/cpu.h (revision 36df75a0)
1 #ifndef MIPS_CPU_H
2 #define MIPS_CPU_H
3 
4 #include "cpu-qom.h"
5 #include "exec/cpu-defs.h"
6 #ifndef CONFIG_USER_ONLY
7 #include "exec/memory.h"
8 #endif
9 #include "fpu/softfloat-types.h"
10 #include "hw/clock.h"
11 #include "mips-defs.h"
12 
13 #define TCG_GUEST_DEFAULT_MO (0)
14 
15 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
16 
17 /* MSA Context */
18 #define MSA_WRLEN (128)
19 
20 typedef union wr_t wr_t;
21 union wr_t {
22     int8_t  b[MSA_WRLEN / 8];
23     int16_t h[MSA_WRLEN / 16];
24     int32_t w[MSA_WRLEN / 32];
25     int64_t d[MSA_WRLEN / 64];
26 };
27 
28 typedef union fpr_t fpr_t;
29 union fpr_t {
30     float64  fd;   /* ieee double precision */
31     float32  fs[2];/* ieee single precision */
32     uint64_t d;    /* binary double fixed-point */
33     uint32_t w[2]; /* binary single fixed-point */
34 /* FPU/MSA register mapping is not tested on big-endian hosts. */
35     wr_t     wr;   /* vector data */
36 };
37 /*
38  *define FP_ENDIAN_IDX to access the same location
39  * in the fpr_t union regardless of the host endianness
40  */
41 #if HOST_BIG_ENDIAN
42 #  define FP_ENDIAN_IDX 1
43 #else
44 #  define FP_ENDIAN_IDX 0
45 #endif
46 
47 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
48 struct CPUMIPSFPUContext {
49     /* Floating point registers */
50     fpr_t fpr[32];
51     float_status fp_status;
52     /* fpu implementation/revision register (fir) */
53     uint32_t fcr0;
54 #define FCR0_FREP 29
55 #define FCR0_UFRP 28
56 #define FCR0_HAS2008 23
57 #define FCR0_F64 22
58 #define FCR0_L 21
59 #define FCR0_W 20
60 #define FCR0_3D 19
61 #define FCR0_PS 18
62 #define FCR0_D 17
63 #define FCR0_S 16
64 #define FCR0_PRID 8
65 #define FCR0_REV 0
66     /* fcsr */
67     uint32_t fcr31_rw_bitmask;
68     uint32_t fcr31;
69 #define FCR31_FS 24
70 #define FCR31_ABS2008 19
71 #define FCR31_NAN2008 18
72 #define SET_FP_COND(num, env)     do { ((env).fcr31) |=                 \
73                                        ((num) ? (1 << ((num) + 24)) :   \
74                                                 (1 << 23));             \
75                                      } while (0)
76 #define CLEAR_FP_COND(num, env)   do { ((env).fcr31) &=                 \
77                                        ~((num) ? (1 << ((num) + 24)) :  \
78                                                  (1 << 23));            \
79                                      } while (0)
80 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) |        \
81                                  (((env).fcr31 >> 23) & 0x1))
82 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
83 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
84 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
85 #define SET_FP_CAUSE(reg, v)      do { (reg) = ((reg) & ~(0x3f << 12)) | \
86                                                ((v & 0x3f) << 12);       \
87                                      } while (0)
88 #define SET_FP_ENABLE(reg, v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | \
89                                                ((v & 0x1f) << 7);        \
90                                      } while (0)
91 #define SET_FP_FLAGS(reg, v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | \
92                                                ((v & 0x1f) << 2);        \
93                                      } while (0)
94 #define UPDATE_FP_FLAGS(reg, v)   do { (reg) |= ((v & 0x1f) << 2); } while (0)
95 #define FP_INEXACT        1
96 #define FP_UNDERFLOW      2
97 #define FP_OVERFLOW       4
98 #define FP_DIV0           8
99 #define FP_INVALID        16
100 #define FP_UNIMPLEMENTED  32
101 };
102 
103 #define TARGET_INSN_START_EXTRA_WORDS 2
104 
105 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
106 struct CPUMIPSMVPContext {
107     int32_t CP0_MVPControl;
108 #define CP0MVPCo_CPA    3
109 #define CP0MVPCo_STLB   2
110 #define CP0MVPCo_VPC    1
111 #define CP0MVPCo_EVP    0
112     int32_t CP0_MVPConf0;
113 #define CP0MVPC0_M      31
114 #define CP0MVPC0_TLBS   29
115 #define CP0MVPC0_GS     28
116 #define CP0MVPC0_PCP    27
117 #define CP0MVPC0_PTLBE  16
118 #define CP0MVPC0_TCA    15
119 #define CP0MVPC0_PVPE   10
120 #define CP0MVPC0_PTC    0
121     int32_t CP0_MVPConf1;
122 #define CP0MVPC1_CIM    31
123 #define CP0MVPC1_CIF    30
124 #define CP0MVPC1_PCX    20
125 #define CP0MVPC1_PCP2   10
126 #define CP0MVPC1_PCP1   0
127 };
128 
129 typedef struct mips_def_t mips_def_t;
130 
131 #define MIPS_SHADOW_SET_MAX 16
132 #define MIPS_TC_MAX 5
133 #define MIPS_FPU_MAX 1
134 #define MIPS_DSP_ACC 4
135 #define MIPS_KSCRATCH_NUM 6
136 #define MIPS_MAAR_MAX 16 /* Must be an even number. */
137 
138 
139 /*
140  *     Summary of CP0 registers
141  *     ========================
142  *
143  *
144  *     Register 0        Register 1        Register 2        Register 3
145  *     ----------        ----------        ----------        ----------
146  *
147  * 0   Index             Random            EntryLo0          EntryLo1
148  * 1   MVPControl        VPEControl        TCStatus          GlobalNumber
149  * 2   MVPConf0          VPEConf0          TCBind
150  * 3   MVPConf1          VPEConf1          TCRestart
151  * 4   VPControl         YQMask            TCHalt
152  * 5                     VPESchedule       TCContext
153  * 6                     VPEScheFBack      TCSchedule
154  * 7                     VPEOpt            TCScheFBack       TCOpt
155  *
156  *
157  *     Register 4        Register 5        Register 6        Register 7
158  *     ----------        ----------        ----------        ----------
159  *
160  * 0   Context           PageMask          Wired             HWREna
161  * 1   ContextConfig     PageGrain         SRSConf0
162  * 2   UserLocal         SegCtl0           SRSConf1
163  * 3   XContextConfig    SegCtl1           SRSConf2
164  * 4   DebugContextID    SegCtl2           SRSConf3
165  * 5   MemoryMapID       PWBase            SRSConf4
166  * 6                     PWField           PWCtl
167  * 7                     PWSize
168  *
169  *
170  *     Register 8        Register 9        Register 10       Register 11
171  *     ----------        ----------        -----------       -----------
172  *
173  * 0   BadVAddr          Count             EntryHi           Compare
174  * 1   BadInstr
175  * 2   BadInstrP
176  * 3   BadInstrX
177  * 4                                       GuestCtl1         GuestCtl0Ext
178  * 5                                       GuestCtl2
179  * 6                     SAARI             GuestCtl3
180  * 7                     SAAR
181  *
182  *
183  *     Register 12       Register 13       Register 14       Register 15
184  *     -----------       -----------       -----------       -----------
185  *
186  * 0   Status            Cause             EPC               PRId
187  * 1   IntCtl                                                EBase
188  * 2   SRSCtl                              NestedEPC         CDMMBase
189  * 3   SRSMap                                                CMGCRBase
190  * 4   View_IPL          View_RIPL                           BEVVA
191  * 5   SRSMap2           NestedExc
192  * 6   GuestCtl0
193  * 7   GTOffset
194  *
195  *
196  *     Register 16       Register 17       Register 18       Register 19
197  *     -----------       -----------       -----------       -----------
198  *
199  * 0   Config            LLAddr            WatchLo0          WatchHi
200  * 1   Config1           MAAR              WatchLo1          WatchHi
201  * 2   Config2           MAARI             WatchLo2          WatchHi
202  * 3   Config3                             WatchLo3          WatchHi
203  * 4   Config4                             WatchLo4          WatchHi
204  * 5   Config5                             WatchLo5          WatchHi
205  * 6   Config6                             WatchLo6          WatchHi
206  * 7   Config7                             WatchLo7          WatchHi
207  *
208  *
209  *     Register 20       Register 21       Register 22       Register 23
210  *     -----------       -----------       -----------       -----------
211  *
212  * 0   XContext                                              Debug
213  * 1                                                         TraceControl
214  * 2                                                         TraceControl2
215  * 3                                                         UserTraceData1
216  * 4                                                         TraceIBPC
217  * 5                                                         TraceDBPC
218  * 6                                                         Debug2
219  * 7
220  *
221  *
222  *     Register 24       Register 25       Register 26       Register 27
223  *     -----------       -----------       -----------       -----------
224  *
225  * 0   DEPC              PerfCnt            ErrCtl          CacheErr
226  * 1                     PerfCnt
227  * 2   TraceControl3     PerfCnt
228  * 3   UserTraceData2    PerfCnt
229  * 4                     PerfCnt
230  * 5                     PerfCnt
231  * 6                     PerfCnt
232  * 7                     PerfCnt
233  *
234  *
235  *     Register 28       Register 29       Register 30       Register 31
236  *     -----------       -----------       -----------       -----------
237  *
238  * 0   DataLo            DataHi            ErrorEPC          DESAVE
239  * 1   TagLo             TagHi
240  * 2   DataLo1           DataHi1                             KScratch<n>
241  * 3   TagLo1            TagHi1                              KScratch<n>
242  * 4   DataLo2           DataHi2                             KScratch<n>
243  * 5   TagLo2            TagHi2                              KScratch<n>
244  * 6   DataLo3           DataHi3                             KScratch<n>
245  * 7   TagLo3            TagHi3                              KScratch<n>
246  *
247  */
248 #define CP0_REGISTER_00     0
249 #define CP0_REGISTER_01     1
250 #define CP0_REGISTER_02     2
251 #define CP0_REGISTER_03     3
252 #define CP0_REGISTER_04     4
253 #define CP0_REGISTER_05     5
254 #define CP0_REGISTER_06     6
255 #define CP0_REGISTER_07     7
256 #define CP0_REGISTER_08     8
257 #define CP0_REGISTER_09     9
258 #define CP0_REGISTER_10    10
259 #define CP0_REGISTER_11    11
260 #define CP0_REGISTER_12    12
261 #define CP0_REGISTER_13    13
262 #define CP0_REGISTER_14    14
263 #define CP0_REGISTER_15    15
264 #define CP0_REGISTER_16    16
265 #define CP0_REGISTER_17    17
266 #define CP0_REGISTER_18    18
267 #define CP0_REGISTER_19    19
268 #define CP0_REGISTER_20    20
269 #define CP0_REGISTER_21    21
270 #define CP0_REGISTER_22    22
271 #define CP0_REGISTER_23    23
272 #define CP0_REGISTER_24    24
273 #define CP0_REGISTER_25    25
274 #define CP0_REGISTER_26    26
275 #define CP0_REGISTER_27    27
276 #define CP0_REGISTER_28    28
277 #define CP0_REGISTER_29    29
278 #define CP0_REGISTER_30    30
279 #define CP0_REGISTER_31    31
280 
281 
282 /* CP0 Register 00 */
283 #define CP0_REG00__INDEX           0
284 #define CP0_REG00__MVPCONTROL      1
285 #define CP0_REG00__MVPCONF0        2
286 #define CP0_REG00__MVPCONF1        3
287 #define CP0_REG00__VPCONTROL       4
288 /* CP0 Register 01 */
289 #define CP0_REG01__RANDOM          0
290 #define CP0_REG01__VPECONTROL      1
291 #define CP0_REG01__VPECONF0        2
292 #define CP0_REG01__VPECONF1        3
293 #define CP0_REG01__YQMASK          4
294 #define CP0_REG01__VPESCHEDULE     5
295 #define CP0_REG01__VPESCHEFBACK    6
296 #define CP0_REG01__VPEOPT          7
297 /* CP0 Register 02 */
298 #define CP0_REG02__ENTRYLO0        0
299 #define CP0_REG02__TCSTATUS        1
300 #define CP0_REG02__TCBIND          2
301 #define CP0_REG02__TCRESTART       3
302 #define CP0_REG02__TCHALT          4
303 #define CP0_REG02__TCCONTEXT       5
304 #define CP0_REG02__TCSCHEDULE      6
305 #define CP0_REG02__TCSCHEFBACK     7
306 /* CP0 Register 03 */
307 #define CP0_REG03__ENTRYLO1        0
308 #define CP0_REG03__GLOBALNUM       1
309 #define CP0_REG03__TCOPT           7
310 /* CP0 Register 04 */
311 #define CP0_REG04__CONTEXT         0
312 #define CP0_REG04__CONTEXTCONFIG   1
313 #define CP0_REG04__USERLOCAL       2
314 #define CP0_REG04__XCONTEXTCONFIG  3
315 #define CP0_REG04__DBGCONTEXTID    4
316 #define CP0_REG04__MMID            5
317 /* CP0 Register 05 */
318 #define CP0_REG05__PAGEMASK        0
319 #define CP0_REG05__PAGEGRAIN       1
320 #define CP0_REG05__SEGCTL0         2
321 #define CP0_REG05__SEGCTL1         3
322 #define CP0_REG05__SEGCTL2         4
323 #define CP0_REG05__PWBASE          5
324 #define CP0_REG05__PWFIELD         6
325 #define CP0_REG05__PWSIZE          7
326 /* CP0 Register 06 */
327 #define CP0_REG06__WIRED           0
328 #define CP0_REG06__SRSCONF0        1
329 #define CP0_REG06__SRSCONF1        2
330 #define CP0_REG06__SRSCONF2        3
331 #define CP0_REG06__SRSCONF3        4
332 #define CP0_REG06__SRSCONF4        5
333 #define CP0_REG06__PWCTL           6
334 /* CP0 Register 07 */
335 #define CP0_REG07__HWRENA          0
336 /* CP0 Register 08 */
337 #define CP0_REG08__BADVADDR        0
338 #define CP0_REG08__BADINSTR        1
339 #define CP0_REG08__BADINSTRP       2
340 #define CP0_REG08__BADINSTRX       3
341 /* CP0 Register 09 */
342 #define CP0_REG09__COUNT           0
343 #define CP0_REG09__SAARI           6
344 #define CP0_REG09__SAAR            7
345 /* CP0 Register 10 */
346 #define CP0_REG10__ENTRYHI         0
347 #define CP0_REG10__GUESTCTL1       4
348 #define CP0_REG10__GUESTCTL2       5
349 #define CP0_REG10__GUESTCTL3       6
350 /* CP0 Register 11 */
351 #define CP0_REG11__COMPARE         0
352 #define CP0_REG11__GUESTCTL0EXT    4
353 /* CP0 Register 12 */
354 #define CP0_REG12__STATUS          0
355 #define CP0_REG12__INTCTL          1
356 #define CP0_REG12__SRSCTL          2
357 #define CP0_REG12__SRSMAP          3
358 #define CP0_REG12__VIEW_IPL        4
359 #define CP0_REG12__SRSMAP2         5
360 #define CP0_REG12__GUESTCTL0       6
361 #define CP0_REG12__GTOFFSET        7
362 /* CP0 Register 13 */
363 #define CP0_REG13__CAUSE           0
364 #define CP0_REG13__VIEW_RIPL       4
365 #define CP0_REG13__NESTEDEXC       5
366 /* CP0 Register 14 */
367 #define CP0_REG14__EPC             0
368 #define CP0_REG14__NESTEDEPC       2
369 /* CP0 Register 15 */
370 #define CP0_REG15__PRID            0
371 #define CP0_REG15__EBASE           1
372 #define CP0_REG15__CDMMBASE        2
373 #define CP0_REG15__CMGCRBASE       3
374 #define CP0_REG15__BEVVA           4
375 /* CP0 Register 16 */
376 #define CP0_REG16__CONFIG          0
377 #define CP0_REG16__CONFIG1         1
378 #define CP0_REG16__CONFIG2         2
379 #define CP0_REG16__CONFIG3         3
380 #define CP0_REG16__CONFIG4         4
381 #define CP0_REG16__CONFIG5         5
382 #define CP0_REG16__CONFIG6         6
383 #define CP0_REG16__CONFIG7         7
384 /* CP0 Register 17 */
385 #define CP0_REG17__LLADDR          0
386 #define CP0_REG17__MAAR            1
387 #define CP0_REG17__MAARI           2
388 /* CP0 Register 18 */
389 #define CP0_REG18__WATCHLO0        0
390 #define CP0_REG18__WATCHLO1        1
391 #define CP0_REG18__WATCHLO2        2
392 #define CP0_REG18__WATCHLO3        3
393 #define CP0_REG18__WATCHLO4        4
394 #define CP0_REG18__WATCHLO5        5
395 #define CP0_REG18__WATCHLO6        6
396 #define CP0_REG18__WATCHLO7        7
397 /* CP0 Register 19 */
398 #define CP0_REG19__WATCHHI0        0
399 #define CP0_REG19__WATCHHI1        1
400 #define CP0_REG19__WATCHHI2        2
401 #define CP0_REG19__WATCHHI3        3
402 #define CP0_REG19__WATCHHI4        4
403 #define CP0_REG19__WATCHHI5        5
404 #define CP0_REG19__WATCHHI6        6
405 #define CP0_REG19__WATCHHI7        7
406 /* CP0 Register 20 */
407 #define CP0_REG20__XCONTEXT        0
408 /* CP0 Register 21 */
409 /* CP0 Register 22 */
410 /* CP0 Register 23 */
411 #define CP0_REG23__DEBUG           0
412 #define CP0_REG23__TRACECONTROL    1
413 #define CP0_REG23__TRACECONTROL2   2
414 #define CP0_REG23__USERTRACEDATA1  3
415 #define CP0_REG23__TRACEIBPC       4
416 #define CP0_REG23__TRACEDBPC       5
417 #define CP0_REG23__DEBUG2          6
418 /* CP0 Register 24 */
419 #define CP0_REG24__DEPC            0
420 /* CP0 Register 25 */
421 #define CP0_REG25__PERFCTL0        0
422 #define CP0_REG25__PERFCNT0        1
423 #define CP0_REG25__PERFCTL1        2
424 #define CP0_REG25__PERFCNT1        3
425 #define CP0_REG25__PERFCTL2        4
426 #define CP0_REG25__PERFCNT2        5
427 #define CP0_REG25__PERFCTL3        6
428 #define CP0_REG25__PERFCNT3        7
429 /* CP0 Register 26 */
430 #define CP0_REG26__ERRCTL          0
431 /* CP0 Register 27 */
432 #define CP0_REG27__CACHERR         0
433 /* CP0 Register 28 */
434 #define CP0_REG28__TAGLO           0
435 #define CP0_REG28__DATALO          1
436 #define CP0_REG28__TAGLO1          2
437 #define CP0_REG28__DATALO1         3
438 #define CP0_REG28__TAGLO2          4
439 #define CP0_REG28__DATALO2         5
440 #define CP0_REG28__TAGLO3          6
441 #define CP0_REG28__DATALO3         7
442 /* CP0 Register 29 */
443 #define CP0_REG29__TAGHI           0
444 #define CP0_REG29__DATAHI          1
445 #define CP0_REG29__TAGHI1          2
446 #define CP0_REG29__DATAHI1         3
447 #define CP0_REG29__TAGHI2          4
448 #define CP0_REG29__DATAHI2         5
449 #define CP0_REG29__TAGHI3          6
450 #define CP0_REG29__DATAHI3         7
451 /* CP0 Register 30 */
452 #define CP0_REG30__ERROREPC        0
453 /* CP0 Register 31 */
454 #define CP0_REG31__DESAVE          0
455 #define CP0_REG31__KSCRATCH1       2
456 #define CP0_REG31__KSCRATCH2       3
457 #define CP0_REG31__KSCRATCH3       4
458 #define CP0_REG31__KSCRATCH4       5
459 #define CP0_REG31__KSCRATCH5       6
460 #define CP0_REG31__KSCRATCH6       7
461 
462 
463 typedef struct TCState TCState;
464 struct TCState {
465     target_ulong gpr[32];
466 #if defined(TARGET_MIPS64)
467     /*
468      * For CPUs using 128-bit GPR registers, we put the lower halves in gpr[])
469      * and the upper halves in gpr_hi[].
470      */
471     uint64_t gpr_hi[32];
472 #endif /* TARGET_MIPS64 */
473     target_ulong PC;
474     target_ulong HI[MIPS_DSP_ACC];
475     target_ulong LO[MIPS_DSP_ACC];
476     target_ulong ACX[MIPS_DSP_ACC];
477     target_ulong DSPControl;
478     int32_t CP0_TCStatus;
479 #define CP0TCSt_TCU3    31
480 #define CP0TCSt_TCU2    30
481 #define CP0TCSt_TCU1    29
482 #define CP0TCSt_TCU0    28
483 #define CP0TCSt_TMX     27
484 #define CP0TCSt_RNST    23
485 #define CP0TCSt_TDS     21
486 #define CP0TCSt_DT      20
487 #define CP0TCSt_DA      15
488 #define CP0TCSt_A       13
489 #define CP0TCSt_TKSU    11
490 #define CP0TCSt_IXMT    10
491 #define CP0TCSt_TASID   0
492     int32_t CP0_TCBind;
493 #define CP0TCBd_CurTC   21
494 #define CP0TCBd_TBE     17
495 #define CP0TCBd_CurVPE  0
496     target_ulong CP0_TCHalt;
497     target_ulong CP0_TCContext;
498     target_ulong CP0_TCSchedule;
499     target_ulong CP0_TCScheFBack;
500     int32_t CP0_Debug_tcstatus;
501     target_ulong CP0_UserLocal;
502 
503     int32_t msacsr;
504 
505 #define MSACSR_FS       24
506 #define MSACSR_FS_MASK  (1 << MSACSR_FS)
507 #define MSACSR_NX       18
508 #define MSACSR_NX_MASK  (1 << MSACSR_NX)
509 #define MSACSR_CEF      2
510 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
511 #define MSACSR_RM       0
512 #define MSACSR_RM_MASK  (0x3 << MSACSR_RM)
513 #define MSACSR_MASK     (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
514         MSACSR_FS_MASK)
515 
516     float_status msa_fp_status;
517 
518 #define NUMBER_OF_MXU_REGISTERS 16
519     target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
520     target_ulong mxu_cr;
521 #define MXU_CR_LC       31
522 #define MXU_CR_RC       30
523 #define MXU_CR_BIAS     2
524 #define MXU_CR_RD_EN    1
525 #define MXU_CR_MXU_EN   0
526 
527 };
528 
529 struct MIPSITUState;
530 typedef struct CPUArchState {
531     TCState active_tc;
532     CPUMIPSFPUContext active_fpu;
533 
534     uint32_t current_tc;
535     uint32_t current_fpu;
536 
537     uint32_t SEGBITS;
538     uint32_t PABITS;
539 #if defined(TARGET_MIPS64)
540 # define PABITS_BASE 36
541 #else
542 # define PABITS_BASE 32
543 #endif
544     target_ulong SEGMask;
545     uint64_t PAMask;
546 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
547 
548     int32_t msair;
549 #define MSAIR_ProcID    8
550 #define MSAIR_Rev       0
551 
552 /*
553  * CP0 Register 0
554  */
555     int32_t CP0_Index;
556     /* CP0_MVP* are per MVP registers. */
557     int32_t CP0_VPControl;
558 #define CP0VPCtl_DIS    0
559 /*
560  * CP0 Register 1
561  */
562     int32_t CP0_Random;
563     int32_t CP0_VPEControl;
564 #define CP0VPECo_YSI    21
565 #define CP0VPECo_GSI    20
566 #define CP0VPECo_EXCPT  16
567 #define CP0VPECo_TE     15
568 #define CP0VPECo_TargTC 0
569     int32_t CP0_VPEConf0;
570 #define CP0VPEC0_M      31
571 #define CP0VPEC0_XTC    21
572 #define CP0VPEC0_TCS    19
573 #define CP0VPEC0_SCS    18
574 #define CP0VPEC0_DSC    17
575 #define CP0VPEC0_ICS    16
576 #define CP0VPEC0_MVP    1
577 #define CP0VPEC0_VPA    0
578     int32_t CP0_VPEConf1;
579 #define CP0VPEC1_NCX    20
580 #define CP0VPEC1_NCP2   10
581 #define CP0VPEC1_NCP1   0
582     target_ulong CP0_YQMask;
583     target_ulong CP0_VPESchedule;
584     target_ulong CP0_VPEScheFBack;
585     int32_t CP0_VPEOpt;
586 #define CP0VPEOpt_IWX7  15
587 #define CP0VPEOpt_IWX6  14
588 #define CP0VPEOpt_IWX5  13
589 #define CP0VPEOpt_IWX4  12
590 #define CP0VPEOpt_IWX3  11
591 #define CP0VPEOpt_IWX2  10
592 #define CP0VPEOpt_IWX1  9
593 #define CP0VPEOpt_IWX0  8
594 #define CP0VPEOpt_DWX7  7
595 #define CP0VPEOpt_DWX6  6
596 #define CP0VPEOpt_DWX5  5
597 #define CP0VPEOpt_DWX4  4
598 #define CP0VPEOpt_DWX3  3
599 #define CP0VPEOpt_DWX2  2
600 #define CP0VPEOpt_DWX1  1
601 #define CP0VPEOpt_DWX0  0
602 /*
603  * CP0 Register 2
604  */
605     uint64_t CP0_EntryLo0;
606 /*
607  * CP0 Register 3
608  */
609     uint64_t CP0_EntryLo1;
610 #if defined(TARGET_MIPS64)
611 # define CP0EnLo_RI 63
612 # define CP0EnLo_XI 62
613 #else
614 # define CP0EnLo_RI 31
615 # define CP0EnLo_XI 30
616 #endif
617     int32_t CP0_GlobalNumber;
618 #define CP0GN_VPId 0
619 /*
620  * CP0 Register 4
621  */
622     target_ulong CP0_Context;
623     int32_t CP0_MemoryMapID;
624 /*
625  * CP0 Register 5
626  */
627     int32_t CP0_PageMask;
628 #define CP0PM_MASK 13
629     int32_t CP0_PageGrain_rw_bitmask;
630     int32_t CP0_PageGrain;
631 #define CP0PG_RIE 31
632 #define CP0PG_XIE 30
633 #define CP0PG_ELPA 29
634 #define CP0PG_IEC 27
635     target_ulong CP0_SegCtl0;
636     target_ulong CP0_SegCtl1;
637     target_ulong CP0_SegCtl2;
638 #define CP0SC_PA        9
639 #define CP0SC_PA_MASK   (0x7FULL << CP0SC_PA)
640 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA)
641 #define CP0SC_AM        4
642 #define CP0SC_AM_MASK   (0x7ULL << CP0SC_AM)
643 #define CP0SC_AM_UK     0ULL
644 #define CP0SC_AM_MK     1ULL
645 #define CP0SC_AM_MSK    2ULL
646 #define CP0SC_AM_MUSK   3ULL
647 #define CP0SC_AM_MUSUK  4ULL
648 #define CP0SC_AM_USK    5ULL
649 #define CP0SC_AM_UUSK   7ULL
650 #define CP0SC_EU        3
651 #define CP0SC_EU_MASK   (1ULL << CP0SC_EU)
652 #define CP0SC_C         0
653 #define CP0SC_C_MASK    (0x7ULL << CP0SC_C)
654 #define CP0SC_MASK      (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
655                          CP0SC_PA_MASK)
656 #define CP0SC_1GMASK    (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
657                          CP0SC_PA_1GMASK)
658 #define CP0SC0_MASK     (CP0SC_MASK | (CP0SC_MASK << 16))
659 #define CP0SC1_XAM      59
660 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM)
661 #define CP0SC1_MASK     (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK)
662 #define CP0SC2_XR       56
663 #define CP0SC2_XR_MASK  (0xFFULL << CP0SC2_XR)
664 #define CP0SC2_MASK     (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
665     target_ulong CP0_PWBase;
666     target_ulong CP0_PWField;
667 #if defined(TARGET_MIPS64)
668 #define CP0PF_BDI  32    /* 37..32 */
669 #define CP0PF_GDI  24    /* 29..24 */
670 #define CP0PF_UDI  18    /* 23..18 */
671 #define CP0PF_MDI  12    /* 17..12 */
672 #define CP0PF_PTI  6     /* 11..6  */
673 #define CP0PF_PTEI 0     /*  5..0  */
674 #else
675 #define CP0PF_GDW  24    /* 29..24 */
676 #define CP0PF_UDW  18    /* 23..18 */
677 #define CP0PF_MDW  12    /* 17..12 */
678 #define CP0PF_PTW  6     /* 11..6  */
679 #define CP0PF_PTEW 0     /*  5..0  */
680 #endif
681     target_ulong CP0_PWSize;
682 #if defined(TARGET_MIPS64)
683 #define CP0PS_BDW  32    /* 37..32 */
684 #endif
685 #define CP0PS_PS   30
686 #define CP0PS_GDW  24    /* 29..24 */
687 #define CP0PS_UDW  18    /* 23..18 */
688 #define CP0PS_MDW  12    /* 17..12 */
689 #define CP0PS_PTW  6     /* 11..6  */
690 #define CP0PS_PTEW 0     /*  5..0  */
691 /*
692  * CP0 Register 6
693  */
694     int32_t CP0_Wired;
695     int32_t CP0_PWCtl;
696 #define CP0PC_PWEN      31
697 #if defined(TARGET_MIPS64)
698 #define CP0PC_PWDIREXT  30
699 #define CP0PC_XK        28
700 #define CP0PC_XS        27
701 #define CP0PC_XU        26
702 #endif
703 #define CP0PC_DPH       7
704 #define CP0PC_HUGEPG    6
705 #define CP0PC_PSN       0     /*  5..0  */
706     int32_t CP0_SRSConf0_rw_bitmask;
707     int32_t CP0_SRSConf0;
708 #define CP0SRSC0_M      31
709 #define CP0SRSC0_SRS3   20
710 #define CP0SRSC0_SRS2   10
711 #define CP0SRSC0_SRS1   0
712     int32_t CP0_SRSConf1_rw_bitmask;
713     int32_t CP0_SRSConf1;
714 #define CP0SRSC1_M      31
715 #define CP0SRSC1_SRS6   20
716 #define CP0SRSC1_SRS5   10
717 #define CP0SRSC1_SRS4   0
718     int32_t CP0_SRSConf2_rw_bitmask;
719     int32_t CP0_SRSConf2;
720 #define CP0SRSC2_M      31
721 #define CP0SRSC2_SRS9   20
722 #define CP0SRSC2_SRS8   10
723 #define CP0SRSC2_SRS7   0
724     int32_t CP0_SRSConf3_rw_bitmask;
725     int32_t CP0_SRSConf3;
726 #define CP0SRSC3_M      31
727 #define CP0SRSC3_SRS12  20
728 #define CP0SRSC3_SRS11  10
729 #define CP0SRSC3_SRS10  0
730     int32_t CP0_SRSConf4_rw_bitmask;
731     int32_t CP0_SRSConf4;
732 #define CP0SRSC4_SRS15  20
733 #define CP0SRSC4_SRS14  10
734 #define CP0SRSC4_SRS13  0
735 /*
736  * CP0 Register 7
737  */
738     int32_t CP0_HWREna;
739 /*
740  * CP0 Register 8
741  */
742     target_ulong CP0_BadVAddr;
743     uint32_t CP0_BadInstr;
744     uint32_t CP0_BadInstrP;
745     uint32_t CP0_BadInstrX;
746 /*
747  * CP0 Register 9
748  */
749     int32_t CP0_Count;
750     uint32_t CP0_SAARI;
751 #define CP0SAARI_TARGET 0    /*  5..0  */
752     uint64_t CP0_SAAR[2];
753 #define CP0SAAR_BASE    12   /* 43..12 */
754 #define CP0SAAR_SIZE    1    /*  5..1  */
755 #define CP0SAAR_EN      0
756 /*
757  * CP0 Register 10
758  */
759     target_ulong CP0_EntryHi;
760 #define CP0EnHi_EHINV 10
761     target_ulong CP0_EntryHi_ASID_mask;
762 /*
763  * CP0 Register 11
764  */
765     int32_t CP0_Compare;
766 /*
767  * CP0 Register 12
768  */
769     int32_t CP0_Status;
770 #define CP0St_CU3   31
771 #define CP0St_CU2   30
772 #define CP0St_CU1   29
773 #define CP0St_CU0   28
774 #define CP0St_RP    27
775 #define CP0St_FR    26
776 #define CP0St_RE    25
777 #define CP0St_MX    24
778 #define CP0St_PX    23
779 #define CP0St_BEV   22
780 #define CP0St_TS    21
781 #define CP0St_SR    20
782 #define CP0St_NMI   19
783 #define CP0St_IM    8
784 #define CP0St_KX    7
785 #define CP0St_SX    6
786 #define CP0St_UX    5
787 #define CP0St_KSU   3
788 #define CP0St_ERL   2
789 #define CP0St_EXL   1
790 #define CP0St_IE    0
791     int32_t CP0_IntCtl;
792 #define CP0IntCtl_IPTI 29
793 #define CP0IntCtl_IPPCI 26
794 #define CP0IntCtl_VS 5
795     int32_t CP0_SRSCtl;
796 #define CP0SRSCtl_HSS 26
797 #define CP0SRSCtl_EICSS 18
798 #define CP0SRSCtl_ESS 12
799 #define CP0SRSCtl_PSS 6
800 #define CP0SRSCtl_CSS 0
801     int32_t CP0_SRSMap;
802 #define CP0SRSMap_SSV7 28
803 #define CP0SRSMap_SSV6 24
804 #define CP0SRSMap_SSV5 20
805 #define CP0SRSMap_SSV4 16
806 #define CP0SRSMap_SSV3 12
807 #define CP0SRSMap_SSV2 8
808 #define CP0SRSMap_SSV1 4
809 #define CP0SRSMap_SSV0 0
810 /*
811  * CP0 Register 13
812  */
813     int32_t CP0_Cause;
814 #define CP0Ca_BD   31
815 #define CP0Ca_TI   30
816 #define CP0Ca_CE   28
817 #define CP0Ca_DC   27
818 #define CP0Ca_PCI  26
819 #define CP0Ca_IV   23
820 #define CP0Ca_WP   22
821 #define CP0Ca_IP    8
822 #define CP0Ca_IP_mask 0x0000FF00
823 #define CP0Ca_EC    2
824 /*
825  * CP0 Register 14
826  */
827     target_ulong CP0_EPC;
828 /*
829  * CP0 Register 15
830  */
831     int32_t CP0_PRid;
832     target_ulong CP0_EBase;
833     target_ulong CP0_EBaseWG_rw_bitmask;
834 #define CP0EBase_WG 11
835     target_ulong CP0_CMGCRBase;
836 /*
837  * CP0 Register 16 (after Release 1)
838  */
839     int32_t CP0_Config0;
840 #define CP0C0_M    31
841 #define CP0C0_K23  28    /* 30..28 */
842 #define CP0C0_KU   25    /* 27..25 */
843 #define CP0C0_MDU  20
844 #define CP0C0_MM   18
845 #define CP0C0_BM   16
846 #define CP0C0_Impl 16    /* 24..16 */
847 #define CP0C0_BE   15
848 #define CP0C0_AT   13    /* 14..13 */
849 #define CP0C0_AR   10    /* 12..10 */
850 #define CP0C0_MT   7     /*  9..7  */
851 #define CP0C0_VI   3
852 #define CP0C0_K0   0     /*  2..0  */
853 #define CP0C0_AR_LENGTH 3
854 /*
855  * CP0 Register 16 (before Release 1)
856  */
857 #define CP0C0_Impl 16    /* 24..16 */
858 #define CP0C0_IC   9     /* 11..9 */
859 #define CP0C0_DC   6     /*  8..6 */
860 #define CP0C0_IB   5
861 #define CP0C0_DB   4
862     int32_t CP0_Config1;
863 #define CP0C1_M    31
864 #define CP0C1_MMU  25    /* 30..25 */
865 #define CP0C1_IS   22    /* 24..22 */
866 #define CP0C1_IL   19    /* 21..19 */
867 #define CP0C1_IA   16    /* 18..16 */
868 #define CP0C1_DS   13    /* 15..13 */
869 #define CP0C1_DL   10    /* 12..10 */
870 #define CP0C1_DA   7     /*  9..7  */
871 #define CP0C1_C2   6
872 #define CP0C1_MD   5
873 #define CP0C1_PC   4
874 #define CP0C1_WR   3
875 #define CP0C1_CA   2
876 #define CP0C1_EP   1
877 #define CP0C1_FP   0
878     int32_t CP0_Config2;
879 #define CP0C2_M    31
880 #define CP0C2_TU   28    /* 30..28 */
881 #define CP0C2_TS   24    /* 27..24 */
882 #define CP0C2_TL   20    /* 23..20 */
883 #define CP0C2_TA   16    /* 19..16 */
884 #define CP0C2_SU   12    /* 15..12 */
885 #define CP0C2_SS   8     /* 11..8  */
886 #define CP0C2_SL   4     /*  7..4  */
887 #define CP0C2_SA   0     /*  3..0  */
888     int32_t CP0_Config3;
889 #define CP0C3_M            31
890 #define CP0C3_BPG          30
891 #define CP0C3_CMGCR        29
892 #define CP0C3_MSAP         28
893 #define CP0C3_BP           27
894 #define CP0C3_BI           26
895 #define CP0C3_SC           25
896 #define CP0C3_PW           24
897 #define CP0C3_VZ           23
898 #define CP0C3_IPLV         21    /* 22..21 */
899 #define CP0C3_MMAR         18    /* 20..18 */
900 #define CP0C3_MCU          17
901 #define CP0C3_ISA_ON_EXC   16
902 #define CP0C3_ISA          14    /* 15..14 */
903 #define CP0C3_ULRI         13
904 #define CP0C3_RXI          12
905 #define CP0C3_DSP2P        11
906 #define CP0C3_DSPP         10
907 #define CP0C3_CTXTC        9
908 #define CP0C3_ITL          8
909 #define CP0C3_LPA          7
910 #define CP0C3_VEIC         6
911 #define CP0C3_VInt         5
912 #define CP0C3_SP           4
913 #define CP0C3_CDMM         3
914 #define CP0C3_MT           2
915 #define CP0C3_SM           1
916 #define CP0C3_TL           0
917     int32_t CP0_Config4;
918     int32_t CP0_Config4_rw_bitmask;
919 #define CP0C4_M            31
920 #define CP0C4_IE           29    /* 30..29 */
921 #define CP0C4_AE           28
922 #define CP0C4_VTLBSizeExt  24    /* 27..24 */
923 #define CP0C4_KScrExist    16
924 #define CP0C4_MMUExtDef    14
925 #define CP0C4_FTLBPageSize 8     /* 12..8  */
926 /* bit layout if MMUExtDef=1 */
927 #define CP0C4_MMUSizeExt   0     /*  7..0  */
928 /* bit layout if MMUExtDef=2 */
929 #define CP0C4_FTLBWays     4     /*  7..4  */
930 #define CP0C4_FTLBSets     0     /*  3..0  */
931     int32_t CP0_Config5;
932     int32_t CP0_Config5_rw_bitmask;
933 #define CP0C5_M            31
934 #define CP0C5_K            30
935 #define CP0C5_CV           29
936 #define CP0C5_EVA          28
937 #define CP0C5_MSAEn        27
938 #define CP0C5_PMJ          23    /* 25..23 */
939 #define CP0C5_WR2          22
940 #define CP0C5_NMS          21
941 #define CP0C5_ULS          20
942 #define CP0C5_XPA          19
943 #define CP0C5_CRCP         18
944 #define CP0C5_MI           17
945 #define CP0C5_GI           15    /* 16..15 */
946 #define CP0C5_CA2          14
947 #define CP0C5_XNP          13
948 #define CP0C5_DEC          11
949 #define CP0C5_L2C          10
950 #define CP0C5_UFE          9
951 #define CP0C5_FRE          8
952 #define CP0C5_VP           7
953 #define CP0C5_SBRI         6
954 #define CP0C5_MVH          5
955 #define CP0C5_LLB          4
956 #define CP0C5_MRP          3
957 #define CP0C5_UFR          2
958 #define CP0C5_NFExists     0
959     int32_t CP0_Config6;
960     int32_t CP0_Config6_rw_bitmask;
961 #define CP0C6_BPPASS          31
962 #define CP0C6_KPOS            24
963 #define CP0C6_KE              23
964 #define CP0C6_VTLBONLY        22
965 #define CP0C6_LASX            21
966 #define CP0C6_SSEN            20
967 #define CP0C6_DISDRTIME       19
968 #define CP0C6_PIXNUEN         18
969 #define CP0C6_SCRAND          17
970 #define CP0C6_LLEXCEN         16
971 #define CP0C6_DISVC           15
972 #define CP0C6_VCLRU           14
973 #define CP0C6_DCLRU           13
974 #define CP0C6_PIXUEN          12
975 #define CP0C6_DISBLKLYEN      11
976 #define CP0C6_UMEMUALEN       10
977 #define CP0C6_SFBEN           8
978 #define CP0C6_FLTINT          7
979 #define CP0C6_VLTINT          6
980 #define CP0C6_DISBTB          5
981 #define CP0C6_STPREFCTL       2
982 #define CP0C6_INSTPREF        1
983 #define CP0C6_DATAPREF        0
984     int32_t CP0_Config7;
985     int64_t CP0_Config7_rw_bitmask;
986 #define CP0C7_WII          31
987 #define CP0C7_NAPCGEN       2
988 #define CP0C7_UNIMUEN       1
989 #define CP0C7_VFPUCGEN      0
990     uint64_t CP0_LLAddr;
991     uint64_t CP0_MAAR[MIPS_MAAR_MAX];
992     int32_t CP0_MAARI;
993     /* XXX: Maybe make LLAddr per-TC? */
994 /*
995  * CP0 Register 17
996  */
997     target_ulong lladdr; /* LL virtual address compared against SC */
998     target_ulong llval;
999     uint64_t llval_wp;
1000     uint32_t llnewval_wp;
1001     uint64_t CP0_LLAddr_rw_bitmask;
1002     int CP0_LLAddr_shift;
1003 /*
1004  * CP0 Register 18
1005  */
1006     target_ulong CP0_WatchLo[8];
1007 /*
1008  * CP0 Register 19
1009  */
1010     uint64_t CP0_WatchHi[8];
1011 #define CP0WH_ASID 16
1012 #define CP0WH_M    31
1013 /*
1014  * CP0 Register 20
1015  */
1016     target_ulong CP0_XContext;
1017     int32_t CP0_Framemask;
1018 /*
1019  * CP0 Register 23
1020  */
1021     int32_t CP0_Debug;
1022 #define CP0DB_DBD  31
1023 #define CP0DB_DM   30
1024 #define CP0DB_LSNM 28
1025 #define CP0DB_Doze 27
1026 #define CP0DB_Halt 26
1027 #define CP0DB_CNT  25
1028 #define CP0DB_IBEP 24
1029 #define CP0DB_DBEP 21
1030 #define CP0DB_IEXI 20
1031 #define CP0DB_VER  15
1032 #define CP0DB_DEC  10
1033 #define CP0DB_SSt  8
1034 #define CP0DB_DINT 5
1035 #define CP0DB_DIB  4
1036 #define CP0DB_DDBS 3
1037 #define CP0DB_DDBL 2
1038 #define CP0DB_DBp  1
1039 #define CP0DB_DSS  0
1040 /*
1041  * CP0 Register 24
1042  */
1043     target_ulong CP0_DEPC;
1044 /*
1045  * CP0 Register 25
1046  */
1047     int32_t CP0_Performance0;
1048 /*
1049  * CP0 Register 26
1050  */
1051     int32_t CP0_ErrCtl;
1052 #define CP0EC_WST 29
1053 #define CP0EC_SPR 28
1054 #define CP0EC_ITC 26
1055 /*
1056  * CP0 Register 28
1057  */
1058     uint64_t CP0_TagLo;
1059     int32_t CP0_DataLo;
1060 /*
1061  * CP0 Register 29
1062  */
1063     int32_t CP0_TagHi;
1064     int32_t CP0_DataHi;
1065 /*
1066  * CP0 Register 30
1067  */
1068     target_ulong CP0_ErrorEPC;
1069 /*
1070  * CP0 Register 31
1071  */
1072     int32_t CP0_DESAVE;
1073     target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
1074 /*
1075  * Loongson CSR CPUCFG registers
1076  */
1077     uint32_t lcsr_cpucfg1;
1078 #define CPUCFG1_FP     0
1079 #define CPUCFG1_FPREV  1
1080 #define CPUCFG1_MMI    4
1081 #define CPUCFG1_MSA1   5
1082 #define CPUCFG1_MSA2   6
1083 #define CPUCFG1_LSLDR0 16
1084 #define CPUCFG1_LSPERF 17
1085 #define CPUCFG1_LSPERFX 18
1086 #define CPUCFG1_LSSYNCI 19
1087 #define CPUCFG1_LLEXC   20
1088 #define CPUCFG1_SCRAND  21
1089 #define CPUCFG1_MUALP   25
1090 #define CPUCFG1_KMUALEN 26
1091 #define CPUCFG1_ITLBT   27
1092 #define CPUCFG1_SFBP    29
1093 #define CPUCFG1_CDMAP   30
1094     uint32_t lcsr_cpucfg2;
1095 #define CPUCFG2_LEXT1   0
1096 #define CPUCFG2_LEXT2   1
1097 #define CPUCFG2_LEXT3   2
1098 #define CPUCFG2_LSPW    3
1099 #define CPUCFG2_LCSRP   27
1100 #define CPUCFG2_LDISBLIKELY 28
1101 
1102     /* We waste some space so we can handle shadow registers like TCs. */
1103     TCState tcs[MIPS_SHADOW_SET_MAX];
1104     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
1105     /* QEMU */
1106     int error_code;
1107 #define EXCP_TLB_NOMATCH   0x1
1108 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
1109     uint32_t hflags;    /* CPU State */
1110     /* TMASK defines different execution modes */
1111 #define MIPS_HFLAG_TMASK  0x3F5807FF
1112 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
1113     /*
1114      * The KSU flags must be the lowest bits in hflags. The flag order
1115      * must be the same as defined for CP0 Status. This allows to use
1116      * the bits as the value of mmu_idx.
1117      */
1118 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
1119 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
1120 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
1121 #define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
1122 #define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
1123 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
1124 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
1125 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
1126 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
1127     /*
1128      * True if the MIPS IV COP1X instructions can be used.  This also
1129      * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
1130      * and RSQRT.D.
1131      */
1132 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
1133 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
1134 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
1135 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
1136 #define MIPS_HFLAG_M16_SHIFT 10
1137     /*
1138      * If translation is interrupted between the branch instruction and
1139      * the delay slot, record what type of branch it is so that we can
1140      * resume translation properly.  It might be possible to reduce
1141      * this from three bits to two.
1142      */
1143 #define MIPS_HFLAG_BMASK_BASE  0x803800
1144 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
1145 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
1146 #define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
1147 #define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
1148     /* Extra flags about the current pending branch.  */
1149 #define MIPS_HFLAG_BMASK_EXT 0x7C000
1150 #define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
1151 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
1152 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
1153 #define MIPS_HFLAG_BDS_STRICT  0x20000 /* Strict delay slot size */
1154 #define MIPS_HFLAG_BX     0x40000 /* branch exchanges execution mode    */
1155 #define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
1156     /* MIPS DSP resources access. */
1157 #define MIPS_HFLAG_DSP    0x080000   /* Enable access to DSP resources.    */
1158 #define MIPS_HFLAG_DSP_R2 0x100000   /* Enable access to DSP R2 resources. */
1159 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */
1160     /* Extra flag about HWREna register. */
1161 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
1162 #define MIPS_HFLAG_SBRI  0x400000 /* R6 SDBBP causes RI excpt. in user mode */
1163 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot                   */
1164 #define MIPS_HFLAG_MSA   0x1000000
1165 #define MIPS_HFLAG_FRE   0x2000000 /* FRE enabled */
1166 #define MIPS_HFLAG_ELPA  0x4000000
1167 #define MIPS_HFLAG_ITC_CACHE  0x8000000 /* CACHE instr. operates on ITC tag */
1168 #define MIPS_HFLAG_ERL   0x10000000 /* error level flag */
1169     target_ulong btarget;        /* Jump / branch target               */
1170     target_ulong bcond;          /* Branch condition (if needed)       */
1171 
1172     int SYNCI_Step; /* Address step size for SYNCI */
1173     int CCRes; /* Cycle count resolution/divisor */
1174     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
1175     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
1176     uint64_t insn_flags; /* Supported instruction set */
1177     int saarp;
1178 
1179     /* Fields up to this point are cleared by a CPU reset */
1180     struct {} end_reset_fields;
1181 
1182     /* Fields from here on are preserved across CPU reset. */
1183     CPUMIPSMVPContext *mvp;
1184 #if !defined(CONFIG_USER_ONLY)
1185     CPUMIPSTLBContext *tlb;
1186     void *irq[8];
1187     struct MIPSITUState *itu;
1188     MemoryRegion *itc_tag; /* ITC Configuration Tags */
1189 
1190     /* Loongson IOCSR memory */
1191     struct {
1192         AddressSpace as;
1193         MemoryRegion mr;
1194     } iocsr;
1195 #endif
1196 
1197     const mips_def_t *cpu_model;
1198     QEMUTimer *timer; /* Internal timer */
1199     Clock *count_clock; /* CP0_Count clock */
1200     target_ulong exception_base; /* ExceptionBase input to the core */
1201 } CPUMIPSState;
1202 
1203 /**
1204  * MIPSCPU:
1205  * @env: #CPUMIPSState
1206  * @clock: this CPU input clock (may be connected
1207  *         to an output clock from another device).
1208  *
1209  * A MIPS CPU.
1210  */
1211 struct ArchCPU {
1212     /*< private >*/
1213     CPUState parent_obj;
1214     /*< public >*/
1215 
1216     Clock *clock;
1217     Clock *count_div; /* Divider for CP0_Count clock */
1218     CPUNegativeOffsetState neg;
1219     CPUMIPSState env;
1220 };
1221 
1222 
1223 void mips_cpu_list(void);
1224 
1225 #define cpu_list mips_cpu_list
1226 
1227 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
1228 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
1229 
1230 /*
1231  * MMU modes definitions. We carefully match the indices with our
1232  * hflags layout.
1233  */
1234 #define MMU_USER_IDX 2
1235 
1236 static inline int hflags_mmu_index(uint32_t hflags)
1237 {
1238     if (hflags & MIPS_HFLAG_ERL) {
1239         return 3; /* ERL */
1240     } else {
1241         return hflags & MIPS_HFLAG_KSU;
1242     }
1243 }
1244 
1245 static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
1246 {
1247     return hflags_mmu_index(env->hflags);
1248 }
1249 
1250 #include "exec/cpu-all.h"
1251 
1252 /* Exceptions */
1253 enum {
1254     EXCP_NONE          = -1,
1255     EXCP_RESET         = 0,
1256     EXCP_SRESET,
1257     EXCP_DSS,
1258     EXCP_DINT,
1259     EXCP_DDBL,
1260     EXCP_DDBS,
1261     EXCP_NMI,
1262     EXCP_MCHECK,
1263     EXCP_EXT_INTERRUPT, /* 8 */
1264     EXCP_DFWATCH,
1265     EXCP_DIB,
1266     EXCP_IWATCH,
1267     EXCP_AdEL,
1268     EXCP_AdES,
1269     EXCP_TLBF,
1270     EXCP_IBE,
1271     EXCP_DBp, /* 16 */
1272     EXCP_SYSCALL,
1273     EXCP_BREAK,
1274     EXCP_CpU,
1275     EXCP_RI,
1276     EXCP_OVERFLOW,
1277     EXCP_TRAP,
1278     EXCP_FPE,
1279     EXCP_DWATCH, /* 24 */
1280     EXCP_LTLBL,
1281     EXCP_TLBL,
1282     EXCP_TLBS,
1283     EXCP_DBE,
1284     EXCP_THREAD,
1285     EXCP_MDMX,
1286     EXCP_C2E,
1287     EXCP_CACHE, /* 32 */
1288     EXCP_DSPDIS,
1289     EXCP_MSADIS,
1290     EXCP_MSAFPE,
1291     EXCP_TLBXI,
1292     EXCP_TLBRI,
1293     EXCP_SEMIHOST,
1294 
1295     EXCP_LAST = EXCP_SEMIHOST,
1296 };
1297 
1298 /*
1299  * This is an internally generated WAKE request line.
1300  * It is driven by the CPU itself. Raised when the MT
1301  * block wants to wake a VPE from an inactive state and
1302  * cleared when VPE goes from active to inactive.
1303  */
1304 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
1305 
1306 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
1307 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
1308 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
1309 
1310 bool cpu_type_supports_cps_smp(const char *cpu_type);
1311 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask);
1312 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa);
1313 
1314 /* Check presence of MSA implementation */
1315 static inline bool ase_msa_available(CPUMIPSState *env)
1316 {
1317     return env->CP0_Config3 & (1 << CP0C3_MSAP);
1318 }
1319 
1320 /* Check presence of Loongson CSR instructions */
1321 static inline bool ase_lcsr_available(CPUMIPSState *env)
1322 {
1323     return env->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP);
1324 }
1325 
1326 /* Check presence of multi-threading ASE implementation */
1327 static inline bool ase_mt_available(CPUMIPSState *env)
1328 {
1329     return env->CP0_Config3 & (1 << CP0C3_MT);
1330 }
1331 
1332 static inline bool cpu_type_is_64bit(const char *cpu_type)
1333 {
1334     return cpu_type_supports_isa(cpu_type, CPU_MIPS64);
1335 }
1336 
1337 void cpu_set_exception_base(int vp_index, target_ulong address);
1338 
1339 /* addr.c */
1340 uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
1341 uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
1342 
1343 uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr);
1344 uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr);
1345 
1346 #if !defined(CONFIG_USER_ONLY)
1347 
1348 /* mips_int.c */
1349 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
1350 
1351 /* mips_itu.c */
1352 void itc_reconfigure(struct MIPSITUState *tag);
1353 
1354 #endif /* !CONFIG_USER_ONLY */
1355 
1356 /* helper.c */
1357 target_ulong exception_resume_pc(CPUMIPSState *env);
1358 
1359 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc,
1360                                         uint64_t *cs_base, uint32_t *flags)
1361 {
1362     *pc = env->active_tc.PC;
1363     *cs_base = 0;
1364     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
1365                             MIPS_HFLAG_HWRENA_ULR);
1366 }
1367 
1368 /**
1369  * mips_cpu_create_with_clock:
1370  * @typename: a MIPS CPU type.
1371  * @cpu_refclk: this cpu input clock (an output clock of another device)
1372  *
1373  * Instantiates a MIPS CPU, set the input clock of the CPU to @cpu_refclk,
1374  * then realizes the CPU.
1375  *
1376  * Returns: A #CPUState or %NULL if an error occurred.
1377  */
1378 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk);
1379 
1380 #endif /* MIPS_CPU_H */
1381