1 #ifndef MIPS_CPU_H 2 #define MIPS_CPU_H 3 4 #define ALIGNED_ONLY 5 6 #include "qemu-common.h" 7 #include "cpu-qom.h" 8 #include "exec/cpu-defs.h" 9 #include "fpu/softfloat.h" 10 #include "mips-defs.h" 11 12 #define TCG_GUEST_DEFAULT_MO (0) 13 14 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; 15 16 /* MSA Context */ 17 #define MSA_WRLEN (128) 18 19 typedef union wr_t wr_t; 20 union wr_t { 21 int8_t b[MSA_WRLEN / 8]; 22 int16_t h[MSA_WRLEN / 16]; 23 int32_t w[MSA_WRLEN / 32]; 24 int64_t d[MSA_WRLEN / 64]; 25 }; 26 27 typedef union fpr_t fpr_t; 28 union fpr_t { 29 float64 fd; /* ieee double precision */ 30 float32 fs[2];/* ieee single precision */ 31 uint64_t d; /* binary double fixed-point */ 32 uint32_t w[2]; /* binary single fixed-point */ 33 /* FPU/MSA register mapping is not tested on big-endian hosts. */ 34 wr_t wr; /* vector data */ 35 }; 36 /* 37 *define FP_ENDIAN_IDX to access the same location 38 * in the fpr_t union regardless of the host endianness 39 */ 40 #if defined(HOST_WORDS_BIGENDIAN) 41 # define FP_ENDIAN_IDX 1 42 #else 43 # define FP_ENDIAN_IDX 0 44 #endif 45 46 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; 47 struct CPUMIPSFPUContext { 48 /* Floating point registers */ 49 fpr_t fpr[32]; 50 float_status fp_status; 51 /* fpu implementation/revision register (fir) */ 52 uint32_t fcr0; 53 #define FCR0_FREP 29 54 #define FCR0_UFRP 28 55 #define FCR0_HAS2008 23 56 #define FCR0_F64 22 57 #define FCR0_L 21 58 #define FCR0_W 20 59 #define FCR0_3D 19 60 #define FCR0_PS 18 61 #define FCR0_D 17 62 #define FCR0_S 16 63 #define FCR0_PRID 8 64 #define FCR0_REV 0 65 /* fcsr */ 66 uint32_t fcr31_rw_bitmask; 67 uint32_t fcr31; 68 #define FCR31_FS 24 69 #define FCR31_ABS2008 19 70 #define FCR31_NAN2008 18 71 #define SET_FP_COND(num, env) do { ((env).fcr31) |= \ 72 ((num) ? (1 << ((num) + 24)) : \ 73 (1 << 23)); \ 74 } while (0) 75 #define CLEAR_FP_COND(num, env) do { ((env).fcr31) &= \ 76 ~((num) ? (1 << ((num) + 24)) : \ 77 (1 << 23)); \ 78 } while (0) 79 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \ 80 (((env).fcr31 >> 23) & 0x1)) 81 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) 82 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 83 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) 84 #define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \ 85 ((v & 0x3f) << 12); \ 86 } while (0) 87 #define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \ 88 ((v & 0x1f) << 7); \ 89 } while (0) 90 #define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 2)) | \ 91 ((v & 0x1f) << 2); \ 92 } while (0) 93 #define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 2); } while (0) 94 #define FP_INEXACT 1 95 #define FP_UNDERFLOW 2 96 #define FP_OVERFLOW 4 97 #define FP_DIV0 8 98 #define FP_INVALID 16 99 #define FP_UNIMPLEMENTED 32 100 }; 101 102 #define TARGET_INSN_START_EXTRA_WORDS 2 103 104 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; 105 struct CPUMIPSMVPContext { 106 int32_t CP0_MVPControl; 107 #define CP0MVPCo_CPA 3 108 #define CP0MVPCo_STLB 2 109 #define CP0MVPCo_VPC 1 110 #define CP0MVPCo_EVP 0 111 int32_t CP0_MVPConf0; 112 #define CP0MVPC0_M 31 113 #define CP0MVPC0_TLBS 29 114 #define CP0MVPC0_GS 28 115 #define CP0MVPC0_PCP 27 116 #define CP0MVPC0_PTLBE 16 117 #define CP0MVPC0_TCA 15 118 #define CP0MVPC0_PVPE 10 119 #define CP0MVPC0_PTC 0 120 int32_t CP0_MVPConf1; 121 #define CP0MVPC1_CIM 31 122 #define CP0MVPC1_CIF 30 123 #define CP0MVPC1_PCX 20 124 #define CP0MVPC1_PCP2 10 125 #define CP0MVPC1_PCP1 0 126 }; 127 128 typedef struct mips_def_t mips_def_t; 129 130 #define MIPS_SHADOW_SET_MAX 16 131 #define MIPS_TC_MAX 5 132 #define MIPS_FPU_MAX 1 133 #define MIPS_DSP_ACC 4 134 #define MIPS_KSCRATCH_NUM 6 135 #define MIPS_MAAR_MAX 16 /* Must be an even number. */ 136 137 138 /* 139 * Summary of CP0 registers 140 * ======================== 141 * 142 * 143 * Register 0 Register 1 Register 2 Register 3 144 * ---------- ---------- ---------- ---------- 145 * 146 * 0 Index Random EntryLo0 EntryLo1 147 * 1 MVPControl VPEControl TCStatus GlobalNumber 148 * 2 MVPConf0 VPEConf0 TCBind 149 * 3 MVPConf1 VPEConf1 TCRestart 150 * 4 VPControl YQMask TCHalt 151 * 5 VPESchedule TCContext 152 * 6 VPEScheFBack TCSchedule 153 * 7 VPEOpt TCScheFBack TCOpt 154 * 155 * 156 * Register 4 Register 5 Register 6 Register 7 157 * ---------- ---------- ---------- ---------- 158 * 159 * 0 Context PageMask Wired HWREna 160 * 1 ContextConfig PageGrain SRSConf0 161 * 2 UserLocal SegCtl0 SRSConf1 162 * 3 XContextConfig SegCtl1 SRSConf2 163 * 4 DebugContextID SegCtl2 SRSConf3 164 * 5 MemoryMapID PWBase SRSConf4 165 * 6 PWField PWCtl 166 * 7 PWSize 167 * 168 * 169 * Register 8 Register 9 Register 10 Register 11 170 * ---------- ---------- ----------- ----------- 171 * 172 * 0 BadVAddr Count EntryHi Compare 173 * 1 BadInstr 174 * 2 BadInstrP 175 * 3 BadInstrX 176 * 4 GuestCtl1 GuestCtl0Ext 177 * 5 GuestCtl2 178 * 6 SAARI GuestCtl3 179 * 7 SAAR 180 * 181 * 182 * Register 12 Register 13 Register 14 Register 15 183 * ----------- ----------- ----------- ----------- 184 * 185 * 0 Status Cause EPC PRId 186 * 1 IntCtl EBase 187 * 2 SRSCtl NestedEPC CDMMBase 188 * 3 SRSMap CMGCRBase 189 * 4 View_IPL View_RIPL BEVVA 190 * 5 SRSMap2 NestedExc 191 * 6 GuestCtl0 192 * 7 GTOffset 193 * 194 * 195 * Register 16 Register 17 Register 18 Register 19 196 * ----------- ----------- ----------- ----------- 197 * 198 * 0 Config LLAddr WatchLo WatchHi 199 * 1 Config1 MAAR WatchLo WatchHi 200 * 2 Config2 MAARI WatchLo WatchHi 201 * 3 Config3 WatchLo WatchHi 202 * 4 Config4 WatchLo WatchHi 203 * 5 Config5 WatchLo WatchHi 204 * 6 WatchLo WatchHi 205 * 7 WatchLo WatchHi 206 * 207 * 208 * Register 20 Register 21 Register 22 Register 23 209 * ----------- ----------- ----------- ----------- 210 * 211 * 0 XContext Debug 212 * 1 TraceControl 213 * 2 TraceControl2 214 * 3 UserTraceData1 215 * 4 TraceIBPC 216 * 5 TraceDBPC 217 * 6 Debug2 218 * 7 219 * 220 * 221 * Register 24 Register 25 Register 26 Register 27 222 * ----------- ----------- ----------- ----------- 223 * 224 * 0 DEPC PerfCnt ErrCtl CacheErr 225 * 1 PerfCnt 226 * 2 TraceControl3 PerfCnt 227 * 3 UserTraceData2 PerfCnt 228 * 4 PerfCnt 229 * 5 PerfCnt 230 * 6 PerfCnt 231 * 7 PerfCnt 232 * 233 * 234 * Register 28 Register 29 Register 30 Register 31 235 * ----------- ----------- ----------- ----------- 236 * 237 * 0 DataLo DataHi ErrorEPC DESAVE 238 * 1 TagLo TagHi 239 * 2 DataLo DataHi KScratch<n> 240 * 3 TagLo TagHi KScratch<n> 241 * 4 DataLo DataHi KScratch<n> 242 * 5 TagLo TagHi KScratch<n> 243 * 6 DataLo DataHi KScratch<n> 244 * 7 TagLo TagHi KScratch<n> 245 * 246 */ 247 #define CP0_REGISTER_00 0 248 #define CP0_REGISTER_01 1 249 #define CP0_REGISTER_02 2 250 #define CP0_REGISTER_03 3 251 #define CP0_REGISTER_04 4 252 #define CP0_REGISTER_05 5 253 #define CP0_REGISTER_06 6 254 #define CP0_REGISTER_07 7 255 #define CP0_REGISTER_08 8 256 #define CP0_REGISTER_09 9 257 #define CP0_REGISTER_10 10 258 #define CP0_REGISTER_11 11 259 #define CP0_REGISTER_12 12 260 #define CP0_REGISTER_13 13 261 #define CP0_REGISTER_14 14 262 #define CP0_REGISTER_15 15 263 #define CP0_REGISTER_16 16 264 #define CP0_REGISTER_17 17 265 #define CP0_REGISTER_18 18 266 #define CP0_REGISTER_19 19 267 #define CP0_REGISTER_20 20 268 #define CP0_REGISTER_21 21 269 #define CP0_REGISTER_22 22 270 #define CP0_REGISTER_23 23 271 #define CP0_REGISTER_24 24 272 #define CP0_REGISTER_25 25 273 #define CP0_REGISTER_26 26 274 #define CP0_REGISTER_27 27 275 #define CP0_REGISTER_28 28 276 #define CP0_REGISTER_29 29 277 #define CP0_REGISTER_30 30 278 #define CP0_REGISTER_31 31 279 280 281 /* CP0 Register 00 */ 282 #define CP0_REG00__INDEX 0 283 #define CP0_REG00__VPCONTROL 4 284 /* CP0 Register 01 */ 285 /* CP0 Register 02 */ 286 #define CP0_REG02__ENTRYLO0 0 287 /* CP0 Register 03 */ 288 #define CP0_REG03__ENTRYLO1 0 289 #define CP0_REG03__GLOBALNUM 1 290 /* CP0 Register 04 */ 291 #define CP0_REG04__CONTEXT 0 292 #define CP0_REG04__USERLOCAL 2 293 #define CP0_REG04__DBGCONTEXTID 4 294 #define CP0_REG00__MMID 5 295 /* CP0 Register 05 */ 296 #define CP0_REG05__PAGEMASK 0 297 #define CP0_REG05__PAGEGRAIN 1 298 /* CP0 Register 06 */ 299 #define CP0_REG06__WIRED 0 300 /* CP0 Register 07 */ 301 #define CP0_REG07__HWRENA 0 302 /* CP0 Register 08 */ 303 #define CP0_REG08__BADVADDR 0 304 #define CP0_REG08__BADINSTR 1 305 #define CP0_REG08__BADINSTRP 2 306 /* CP0 Register 09 */ 307 #define CP0_REG09__COUNT 0 308 #define CP0_REG09__SAARI 6 309 #define CP0_REG09__SAAR 7 310 /* CP0 Register 10 */ 311 #define CP0_REG10__ENTRYHI 0 312 #define CP0_REG10__GUESTCTL1 4 313 #define CP0_REG10__GUESTCTL2 5 314 /* CP0 Register 11 */ 315 #define CP0_REG11__COMPARE 0 316 #define CP0_REG11__GUESTCTL0EXT 4 317 /* CP0 Register 12 */ 318 #define CP0_REG12__STATUS 0 319 #define CP0_REG12__INTCTL 1 320 #define CP0_REG12__SRSCTL 2 321 #define CP0_REG12__GUESTCTL0 6 322 #define CP0_REG12__GTOFFSET 7 323 /* CP0 Register 13 */ 324 #define CP0_REG13__CAUSE 0 325 /* CP0 Register 14 */ 326 #define CP0_REG14__EPC 0 327 /* CP0 Register 15 */ 328 #define CP0_REG15__PRID 0 329 #define CP0_REG15__EBASE 1 330 #define CP0_REG15__CDMMBASE 2 331 #define CP0_REG15__CMGCRBASE 3 332 /* CP0 Register 16 */ 333 #define CP0_REG16__CONFIG 0 334 #define CP0_REG16__CONFIG1 1 335 #define CP0_REG16__CONFIG2 2 336 #define CP0_REG16__CONFIG3 3 337 #define CP0_REG16__CONFIG4 4 338 #define CP0_REG16__CONFIG5 5 339 #define CP0_REG00__CONFIG7 7 340 /* CP0 Register 17 */ 341 #define CP0_REG17__LLADDR 0 342 #define CP0_REG17__MAAR 1 343 #define CP0_REG17__MAARI 2 344 /* CP0 Register 18 */ 345 #define CP0_REG18__WATCHLO0 0 346 #define CP0_REG18__WATCHLO1 1 347 #define CP0_REG18__WATCHLO2 2 348 #define CP0_REG18__WATCHLO3 3 349 /* CP0 Register 19 */ 350 #define CP0_REG19__WATCHHI0 0 351 #define CP0_REG19__WATCHHI1 1 352 #define CP0_REG19__WATCHHI2 2 353 #define CP0_REG19__WATCHHI3 3 354 /* CP0 Register 20 */ 355 #define CP0_REG20__XCONTEXT 0 356 /* CP0 Register 21 */ 357 /* CP0 Register 22 */ 358 /* CP0 Register 23 */ 359 #define CP0_REG23__DEBUG 0 360 /* CP0 Register 24 */ 361 #define CP0_REG24__DEPC 0 362 /* CP0 Register 25 */ 363 #define CP0_REG25__PERFCTL0 0 364 #define CP0_REG25__PERFCNT0 1 365 #define CP0_REG25__PERFCTL1 2 366 #define CP0_REG25__PERFCNT1 3 367 #define CP0_REG25__PERFCTL2 4 368 #define CP0_REG25__PERFCNT2 5 369 #define CP0_REG25__PERFCTL3 6 370 #define CP0_REG25__PERFCNT3 7 371 /* CP0 Register 26 */ 372 #define CP0_REG00__ERRCTL 0 373 /* CP0 Register 27 */ 374 #define CP0_REG27__CACHERR 0 375 /* CP0 Register 28 */ 376 #define CP0_REG28__ITAGLO 0 377 #define CP0_REG28__IDATALO 1 378 #define CP0_REG28__DTAGLO 2 379 #define CP0_REG28__DDATALO 3 380 /* CP0 Register 29 */ 381 #define CP0_REG29__IDATAHI 1 382 #define CP0_REG29__DDATAHI 3 383 /* CP0 Register 30 */ 384 #define CP0_REG30__ERROREPC 0 385 /* CP0 Register 31 */ 386 #define CP0_REG31__DESAVE 0 387 #define CP0_REG31__KSCRATCH1 2 388 #define CP0_REG31__KSCRATCH2 3 389 #define CP0_REG31__KSCRATCH3 4 390 #define CP0_REG31__KSCRATCH4 5 391 #define CP0_REG31__KSCRATCH5 6 392 #define CP0_REG31__KSCRATCH6 7 393 394 395 typedef struct TCState TCState; 396 struct TCState { 397 target_ulong gpr[32]; 398 target_ulong PC; 399 target_ulong HI[MIPS_DSP_ACC]; 400 target_ulong LO[MIPS_DSP_ACC]; 401 target_ulong ACX[MIPS_DSP_ACC]; 402 target_ulong DSPControl; 403 int32_t CP0_TCStatus; 404 #define CP0TCSt_TCU3 31 405 #define CP0TCSt_TCU2 30 406 #define CP0TCSt_TCU1 29 407 #define CP0TCSt_TCU0 28 408 #define CP0TCSt_TMX 27 409 #define CP0TCSt_RNST 23 410 #define CP0TCSt_TDS 21 411 #define CP0TCSt_DT 20 412 #define CP0TCSt_DA 15 413 #define CP0TCSt_A 13 414 #define CP0TCSt_TKSU 11 415 #define CP0TCSt_IXMT 10 416 #define CP0TCSt_TASID 0 417 int32_t CP0_TCBind; 418 #define CP0TCBd_CurTC 21 419 #define CP0TCBd_TBE 17 420 #define CP0TCBd_CurVPE 0 421 target_ulong CP0_TCHalt; 422 target_ulong CP0_TCContext; 423 target_ulong CP0_TCSchedule; 424 target_ulong CP0_TCScheFBack; 425 int32_t CP0_Debug_tcstatus; 426 target_ulong CP0_UserLocal; 427 428 int32_t msacsr; 429 430 #define MSACSR_FS 24 431 #define MSACSR_FS_MASK (1 << MSACSR_FS) 432 #define MSACSR_NX 18 433 #define MSACSR_NX_MASK (1 << MSACSR_NX) 434 #define MSACSR_CEF 2 435 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF) 436 #define MSACSR_RM 0 437 #define MSACSR_RM_MASK (0x3 << MSACSR_RM) 438 #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \ 439 MSACSR_FS_MASK) 440 441 float_status msa_fp_status; 442 443 /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */ 444 uint64_t mmr[32]; 445 446 #define NUMBER_OF_MXU_REGISTERS 16 447 target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; 448 target_ulong mxu_cr; 449 #define MXU_CR_LC 31 450 #define MXU_CR_RC 30 451 #define MXU_CR_BIAS 2 452 #define MXU_CR_RD_EN 1 453 #define MXU_CR_MXU_EN 0 454 455 }; 456 457 struct MIPSITUState; 458 typedef struct CPUMIPSState CPUMIPSState; 459 struct CPUMIPSState { 460 TCState active_tc; 461 CPUMIPSFPUContext active_fpu; 462 463 uint32_t current_tc; 464 uint32_t current_fpu; 465 466 uint32_t SEGBITS; 467 uint32_t PABITS; 468 #if defined(TARGET_MIPS64) 469 # define PABITS_BASE 36 470 #else 471 # define PABITS_BASE 32 472 #endif 473 target_ulong SEGMask; 474 uint64_t PAMask; 475 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1) 476 477 int32_t msair; 478 #define MSAIR_ProcID 8 479 #define MSAIR_Rev 0 480 481 /* 482 * CP0 Register 0 483 */ 484 int32_t CP0_Index; 485 /* CP0_MVP* are per MVP registers. */ 486 int32_t CP0_VPControl; 487 #define CP0VPCtl_DIS 0 488 /* 489 * CP0 Register 1 490 */ 491 int32_t CP0_Random; 492 int32_t CP0_VPEControl; 493 #define CP0VPECo_YSI 21 494 #define CP0VPECo_GSI 20 495 #define CP0VPECo_EXCPT 16 496 #define CP0VPECo_TE 15 497 #define CP0VPECo_TargTC 0 498 int32_t CP0_VPEConf0; 499 #define CP0VPEC0_M 31 500 #define CP0VPEC0_XTC 21 501 #define CP0VPEC0_TCS 19 502 #define CP0VPEC0_SCS 18 503 #define CP0VPEC0_DSC 17 504 #define CP0VPEC0_ICS 16 505 #define CP0VPEC0_MVP 1 506 #define CP0VPEC0_VPA 0 507 int32_t CP0_VPEConf1; 508 #define CP0VPEC1_NCX 20 509 #define CP0VPEC1_NCP2 10 510 #define CP0VPEC1_NCP1 0 511 target_ulong CP0_YQMask; 512 target_ulong CP0_VPESchedule; 513 target_ulong CP0_VPEScheFBack; 514 int32_t CP0_VPEOpt; 515 #define CP0VPEOpt_IWX7 15 516 #define CP0VPEOpt_IWX6 14 517 #define CP0VPEOpt_IWX5 13 518 #define CP0VPEOpt_IWX4 12 519 #define CP0VPEOpt_IWX3 11 520 #define CP0VPEOpt_IWX2 10 521 #define CP0VPEOpt_IWX1 9 522 #define CP0VPEOpt_IWX0 8 523 #define CP0VPEOpt_DWX7 7 524 #define CP0VPEOpt_DWX6 6 525 #define CP0VPEOpt_DWX5 5 526 #define CP0VPEOpt_DWX4 4 527 #define CP0VPEOpt_DWX3 3 528 #define CP0VPEOpt_DWX2 2 529 #define CP0VPEOpt_DWX1 1 530 #define CP0VPEOpt_DWX0 0 531 /* 532 * CP0 Register 2 533 */ 534 uint64_t CP0_EntryLo0; 535 /* 536 * CP0 Register 3 537 */ 538 uint64_t CP0_EntryLo1; 539 #if defined(TARGET_MIPS64) 540 # define CP0EnLo_RI 63 541 # define CP0EnLo_XI 62 542 #else 543 # define CP0EnLo_RI 31 544 # define CP0EnLo_XI 30 545 #endif 546 int32_t CP0_GlobalNumber; 547 #define CP0GN_VPId 0 548 /* 549 * CP0 Register 4 550 */ 551 target_ulong CP0_Context; 552 target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; 553 int32_t CP0_MemoryMapID; 554 /* 555 * CP0 Register 5 556 */ 557 int32_t CP0_PageMask; 558 int32_t CP0_PageGrain_rw_bitmask; 559 int32_t CP0_PageGrain; 560 #define CP0PG_RIE 31 561 #define CP0PG_XIE 30 562 #define CP0PG_ELPA 29 563 #define CP0PG_IEC 27 564 target_ulong CP0_SegCtl0; 565 target_ulong CP0_SegCtl1; 566 target_ulong CP0_SegCtl2; 567 #define CP0SC_PA 9 568 #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA) 569 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA) 570 #define CP0SC_AM 4 571 #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM) 572 #define CP0SC_AM_UK 0ULL 573 #define CP0SC_AM_MK 1ULL 574 #define CP0SC_AM_MSK 2ULL 575 #define CP0SC_AM_MUSK 3ULL 576 #define CP0SC_AM_MUSUK 4ULL 577 #define CP0SC_AM_USK 5ULL 578 #define CP0SC_AM_UUSK 7ULL 579 #define CP0SC_EU 3 580 #define CP0SC_EU_MASK (1ULL << CP0SC_EU) 581 #define CP0SC_C 0 582 #define CP0SC_C_MASK (0x7ULL << CP0SC_C) 583 #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ 584 CP0SC_PA_MASK) 585 #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ 586 CP0SC_PA_1GMASK) 587 #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16)) 588 #define CP0SC1_XAM 59 589 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM) 590 #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK) 591 #define CP0SC2_XR 56 592 #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR) 593 #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK) 594 target_ulong CP0_PWBase; 595 target_ulong CP0_PWField; 596 #if defined(TARGET_MIPS64) 597 #define CP0PF_BDI 32 /* 37..32 */ 598 #define CP0PF_GDI 24 /* 29..24 */ 599 #define CP0PF_UDI 18 /* 23..18 */ 600 #define CP0PF_MDI 12 /* 17..12 */ 601 #define CP0PF_PTI 6 /* 11..6 */ 602 #define CP0PF_PTEI 0 /* 5..0 */ 603 #else 604 #define CP0PF_GDW 24 /* 29..24 */ 605 #define CP0PF_UDW 18 /* 23..18 */ 606 #define CP0PF_MDW 12 /* 17..12 */ 607 #define CP0PF_PTW 6 /* 11..6 */ 608 #define CP0PF_PTEW 0 /* 5..0 */ 609 #endif 610 target_ulong CP0_PWSize; 611 #if defined(TARGET_MIPS64) 612 #define CP0PS_BDW 32 /* 37..32 */ 613 #endif 614 #define CP0PS_PS 30 615 #define CP0PS_GDW 24 /* 29..24 */ 616 #define CP0PS_UDW 18 /* 23..18 */ 617 #define CP0PS_MDW 12 /* 17..12 */ 618 #define CP0PS_PTW 6 /* 11..6 */ 619 #define CP0PS_PTEW 0 /* 5..0 */ 620 /* 621 * CP0 Register 6 622 */ 623 int32_t CP0_Wired; 624 int32_t CP0_PWCtl; 625 #define CP0PC_PWEN 31 626 #if defined(TARGET_MIPS64) 627 #define CP0PC_PWDIREXT 30 628 #define CP0PC_XK 28 629 #define CP0PC_XS 27 630 #define CP0PC_XU 26 631 #endif 632 #define CP0PC_DPH 7 633 #define CP0PC_HUGEPG 6 634 #define CP0PC_PSN 0 /* 5..0 */ 635 int32_t CP0_SRSConf0_rw_bitmask; 636 int32_t CP0_SRSConf0; 637 #define CP0SRSC0_M 31 638 #define CP0SRSC0_SRS3 20 639 #define CP0SRSC0_SRS2 10 640 #define CP0SRSC0_SRS1 0 641 int32_t CP0_SRSConf1_rw_bitmask; 642 int32_t CP0_SRSConf1; 643 #define CP0SRSC1_M 31 644 #define CP0SRSC1_SRS6 20 645 #define CP0SRSC1_SRS5 10 646 #define CP0SRSC1_SRS4 0 647 int32_t CP0_SRSConf2_rw_bitmask; 648 int32_t CP0_SRSConf2; 649 #define CP0SRSC2_M 31 650 #define CP0SRSC2_SRS9 20 651 #define CP0SRSC2_SRS8 10 652 #define CP0SRSC2_SRS7 0 653 int32_t CP0_SRSConf3_rw_bitmask; 654 int32_t CP0_SRSConf3; 655 #define CP0SRSC3_M 31 656 #define CP0SRSC3_SRS12 20 657 #define CP0SRSC3_SRS11 10 658 #define CP0SRSC3_SRS10 0 659 int32_t CP0_SRSConf4_rw_bitmask; 660 int32_t CP0_SRSConf4; 661 #define CP0SRSC4_SRS15 20 662 #define CP0SRSC4_SRS14 10 663 #define CP0SRSC4_SRS13 0 664 /* 665 * CP0 Register 7 666 */ 667 int32_t CP0_HWREna; 668 /* 669 * CP0 Register 8 670 */ 671 target_ulong CP0_BadVAddr; 672 uint32_t CP0_BadInstr; 673 uint32_t CP0_BadInstrP; 674 uint32_t CP0_BadInstrX; 675 /* 676 * CP0 Register 9 677 */ 678 int32_t CP0_Count; 679 uint32_t CP0_SAARI; 680 #define CP0SAARI_TARGET 0 /* 5..0 */ 681 uint64_t CP0_SAAR[2]; 682 #define CP0SAAR_BASE 12 /* 43..12 */ 683 #define CP0SAAR_SIZE 1 /* 5..1 */ 684 #define CP0SAAR_EN 0 685 /* 686 * CP0 Register 10 687 */ 688 target_ulong CP0_EntryHi; 689 #define CP0EnHi_EHINV 10 690 target_ulong CP0_EntryHi_ASID_mask; 691 /* 692 * CP0 Register 11 693 */ 694 int32_t CP0_Compare; 695 /* 696 * CP0 Register 12 697 */ 698 int32_t CP0_Status; 699 #define CP0St_CU3 31 700 #define CP0St_CU2 30 701 #define CP0St_CU1 29 702 #define CP0St_CU0 28 703 #define CP0St_RP 27 704 #define CP0St_FR 26 705 #define CP0St_RE 25 706 #define CP0St_MX 24 707 #define CP0St_PX 23 708 #define CP0St_BEV 22 709 #define CP0St_TS 21 710 #define CP0St_SR 20 711 #define CP0St_NMI 19 712 #define CP0St_IM 8 713 #define CP0St_KX 7 714 #define CP0St_SX 6 715 #define CP0St_UX 5 716 #define CP0St_KSU 3 717 #define CP0St_ERL 2 718 #define CP0St_EXL 1 719 #define CP0St_IE 0 720 int32_t CP0_IntCtl; 721 #define CP0IntCtl_IPTI 29 722 #define CP0IntCtl_IPPCI 26 723 #define CP0IntCtl_VS 5 724 int32_t CP0_SRSCtl; 725 #define CP0SRSCtl_HSS 26 726 #define CP0SRSCtl_EICSS 18 727 #define CP0SRSCtl_ESS 12 728 #define CP0SRSCtl_PSS 6 729 #define CP0SRSCtl_CSS 0 730 int32_t CP0_SRSMap; 731 #define CP0SRSMap_SSV7 28 732 #define CP0SRSMap_SSV6 24 733 #define CP0SRSMap_SSV5 20 734 #define CP0SRSMap_SSV4 16 735 #define CP0SRSMap_SSV3 12 736 #define CP0SRSMap_SSV2 8 737 #define CP0SRSMap_SSV1 4 738 #define CP0SRSMap_SSV0 0 739 /* 740 * CP0 Register 13 741 */ 742 int32_t CP0_Cause; 743 #define CP0Ca_BD 31 744 #define CP0Ca_TI 30 745 #define CP0Ca_CE 28 746 #define CP0Ca_DC 27 747 #define CP0Ca_PCI 26 748 #define CP0Ca_IV 23 749 #define CP0Ca_WP 22 750 #define CP0Ca_IP 8 751 #define CP0Ca_IP_mask 0x0000FF00 752 #define CP0Ca_EC 2 753 /* 754 * CP0 Register 14 755 */ 756 target_ulong CP0_EPC; 757 /* 758 * CP0 Register 15 759 */ 760 int32_t CP0_PRid; 761 target_ulong CP0_EBase; 762 target_ulong CP0_EBaseWG_rw_bitmask; 763 #define CP0EBase_WG 11 764 target_ulong CP0_CMGCRBase; 765 /* 766 * CP0 Register 16 767 */ 768 int32_t CP0_Config0; 769 #define CP0C0_M 31 770 #define CP0C0_K23 28 /* 30..28 */ 771 #define CP0C0_KU 25 /* 27..25 */ 772 #define CP0C0_MDU 20 773 #define CP0C0_MM 18 774 #define CP0C0_BM 16 775 #define CP0C0_Impl 16 /* 24..16 */ 776 #define CP0C0_BE 15 777 #define CP0C0_AT 13 /* 14..13 */ 778 #define CP0C0_AR 10 /* 12..10 */ 779 #define CP0C0_MT 7 /* 9..7 */ 780 #define CP0C0_VI 3 781 #define CP0C0_K0 0 /* 2..0 */ 782 int32_t CP0_Config1; 783 #define CP0C1_M 31 784 #define CP0C1_MMU 25 /* 30..25 */ 785 #define CP0C1_IS 22 /* 24..22 */ 786 #define CP0C1_IL 19 /* 21..19 */ 787 #define CP0C1_IA 16 /* 18..16 */ 788 #define CP0C1_DS 13 /* 15..13 */ 789 #define CP0C1_DL 10 /* 12..10 */ 790 #define CP0C1_DA 7 /* 9..7 */ 791 #define CP0C1_C2 6 792 #define CP0C1_MD 5 793 #define CP0C1_PC 4 794 #define CP0C1_WR 3 795 #define CP0C1_CA 2 796 #define CP0C1_EP 1 797 #define CP0C1_FP 0 798 int32_t CP0_Config2; 799 #define CP0C2_M 31 800 #define CP0C2_TU 28 /* 30..28 */ 801 #define CP0C2_TS 24 /* 27..24 */ 802 #define CP0C2_TL 20 /* 23..20 */ 803 #define CP0C2_TA 16 /* 19..16 */ 804 #define CP0C2_SU 12 /* 15..12 */ 805 #define CP0C2_SS 8 /* 11..8 */ 806 #define CP0C2_SL 4 /* 7..4 */ 807 #define CP0C2_SA 0 /* 3..0 */ 808 int32_t CP0_Config3; 809 #define CP0C3_M 31 810 #define CP0C3_BPG 30 811 #define CP0C3_CMGCR 29 812 #define CP0C3_MSAP 28 813 #define CP0C3_BP 27 814 #define CP0C3_BI 26 815 #define CP0C3_SC 25 816 #define CP0C3_PW 24 817 #define CP0C3_VZ 23 818 #define CP0C3_IPLV 21 /* 22..21 */ 819 #define CP0C3_MMAR 18 /* 20..18 */ 820 #define CP0C3_MCU 17 821 #define CP0C3_ISA_ON_EXC 16 822 #define CP0C3_ISA 14 /* 15..14 */ 823 #define CP0C3_ULRI 13 824 #define CP0C3_RXI 12 825 #define CP0C3_DSP2P 11 826 #define CP0C3_DSPP 10 827 #define CP0C3_CTXTC 9 828 #define CP0C3_ITL 8 829 #define CP0C3_LPA 7 830 #define CP0C3_VEIC 6 831 #define CP0C3_VInt 5 832 #define CP0C3_SP 4 833 #define CP0C3_CDMM 3 834 #define CP0C3_MT 2 835 #define CP0C3_SM 1 836 #define CP0C3_TL 0 837 int32_t CP0_Config4; 838 int32_t CP0_Config4_rw_bitmask; 839 #define CP0C4_M 31 840 #define CP0C4_IE 29 /* 30..29 */ 841 #define CP0C4_AE 28 842 #define CP0C4_VTLBSizeExt 24 /* 27..24 */ 843 #define CP0C4_KScrExist 16 844 #define CP0C4_MMUExtDef 14 845 #define CP0C4_FTLBPageSize 8 /* 12..8 */ 846 /* bit layout if MMUExtDef=1 */ 847 #define CP0C4_MMUSizeExt 0 /* 7..0 */ 848 /* bit layout if MMUExtDef=2 */ 849 #define CP0C4_FTLBWays 4 /* 7..4 */ 850 #define CP0C4_FTLBSets 0 /* 3..0 */ 851 int32_t CP0_Config5; 852 int32_t CP0_Config5_rw_bitmask; 853 #define CP0C5_M 31 854 #define CP0C5_K 30 855 #define CP0C5_CV 29 856 #define CP0C5_EVA 28 857 #define CP0C5_MSAEn 27 858 #define CP0C5_PMJ 23 /* 25..23 */ 859 #define CP0C5_WR2 22 860 #define CP0C5_NMS 21 861 #define CP0C5_ULS 20 862 #define CP0C5_XPA 19 863 #define CP0C5_CRCP 18 864 #define CP0C5_MI 17 865 #define CP0C5_GI 15 /* 16..15 */ 866 #define CP0C5_CA2 14 867 #define CP0C5_XNP 13 868 #define CP0C5_DEC 11 869 #define CP0C5_L2C 10 870 #define CP0C5_UFE 9 871 #define CP0C5_FRE 8 872 #define CP0C5_VP 7 873 #define CP0C5_SBRI 6 874 #define CP0C5_MVH 5 875 #define CP0C5_LLB 4 876 #define CP0C5_MRP 3 877 #define CP0C5_UFR 2 878 #define CP0C5_NFExists 0 879 int32_t CP0_Config6; 880 int32_t CP0_Config7; 881 uint64_t CP0_LLAddr; 882 uint64_t CP0_MAAR[MIPS_MAAR_MAX]; 883 int32_t CP0_MAARI; 884 /* XXX: Maybe make LLAddr per-TC? */ 885 /* 886 * CP0 Register 17 887 */ 888 target_ulong lladdr; /* LL virtual address compared against SC */ 889 target_ulong llval; 890 uint64_t llval_wp; 891 uint32_t llnewval_wp; 892 uint64_t CP0_LLAddr_rw_bitmask; 893 int CP0_LLAddr_shift; 894 /* 895 * CP0 Register 18 896 */ 897 target_ulong CP0_WatchLo[8]; 898 /* 899 * CP0 Register 19 900 */ 901 int32_t CP0_WatchHi[8]; 902 #define CP0WH_ASID 16 903 /* 904 * CP0 Register 20 905 */ 906 target_ulong CP0_XContext; 907 int32_t CP0_Framemask; 908 /* 909 * CP0 Register 23 910 */ 911 int32_t CP0_Debug; 912 #define CP0DB_DBD 31 913 #define CP0DB_DM 30 914 #define CP0DB_LSNM 28 915 #define CP0DB_Doze 27 916 #define CP0DB_Halt 26 917 #define CP0DB_CNT 25 918 #define CP0DB_IBEP 24 919 #define CP0DB_DBEP 21 920 #define CP0DB_IEXI 20 921 #define CP0DB_VER 15 922 #define CP0DB_DEC 10 923 #define CP0DB_SSt 8 924 #define CP0DB_DINT 5 925 #define CP0DB_DIB 4 926 #define CP0DB_DDBS 3 927 #define CP0DB_DDBL 2 928 #define CP0DB_DBp 1 929 #define CP0DB_DSS 0 930 /* 931 * CP0 Register 24 932 */ 933 target_ulong CP0_DEPC; 934 /* 935 * CP0 Register 25 936 */ 937 int32_t CP0_Performance0; 938 /* 939 * CP0 Register 26 940 */ 941 int32_t CP0_ErrCtl; 942 #define CP0EC_WST 29 943 #define CP0EC_SPR 28 944 #define CP0EC_ITC 26 945 /* 946 * CP0 Register 28 947 */ 948 uint64_t CP0_TagLo; 949 int32_t CP0_DataLo; 950 /* 951 * CP0 Register 29 952 */ 953 int32_t CP0_TagHi; 954 int32_t CP0_DataHi; 955 /* 956 * CP0 Register 30 957 */ 958 target_ulong CP0_ErrorEPC; 959 /* 960 * CP0 Register 31 961 */ 962 int32_t CP0_DESAVE; 963 964 /* We waste some space so we can handle shadow registers like TCs. */ 965 TCState tcs[MIPS_SHADOW_SET_MAX]; 966 CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; 967 /* QEMU */ 968 int error_code; 969 #define EXCP_TLB_NOMATCH 0x1 970 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ 971 uint32_t hflags; /* CPU State */ 972 /* TMASK defines different execution modes */ 973 #define MIPS_HFLAG_TMASK 0x1F5807FF 974 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ 975 /* 976 * The KSU flags must be the lowest bits in hflags. The flag order 977 * must be the same as defined for CP0 Status. This allows to use 978 * the bits as the value of mmu_idx. 979 */ 980 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ 981 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ 982 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ 983 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ 984 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ 985 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ 986 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ 987 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ 988 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ 989 /* 990 * True if the MIPS IV COP1X instructions can be used. This also 991 * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S 992 * and RSQRT.D. 993 */ 994 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ 995 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ 996 #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ 997 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ 998 #define MIPS_HFLAG_M16_SHIFT 10 999 /* 1000 * If translation is interrupted between the branch instruction and 1001 * the delay slot, record what type of branch it is so that we can 1002 * resume translation properly. It might be possible to reduce 1003 * this from three bits to two. 1004 */ 1005 #define MIPS_HFLAG_BMASK_BASE 0x803800 1006 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ 1007 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ 1008 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ 1009 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ 1010 /* Extra flags about the current pending branch. */ 1011 #define MIPS_HFLAG_BMASK_EXT 0x7C000 1012 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ 1013 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ 1014 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ 1015 #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */ 1016 #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */ 1017 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) 1018 /* MIPS DSP resources access. */ 1019 #define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */ 1020 #define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */ 1021 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */ 1022 /* Extra flag about HWREna register. */ 1023 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ 1024 #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */ 1025 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */ 1026 #define MIPS_HFLAG_MSA 0x1000000 1027 #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */ 1028 #define MIPS_HFLAG_ELPA 0x4000000 1029 #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */ 1030 #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */ 1031 target_ulong btarget; /* Jump / branch target */ 1032 target_ulong bcond; /* Branch condition (if needed) */ 1033 1034 int SYNCI_Step; /* Address step size for SYNCI */ 1035 int CCRes; /* Cycle count resolution/divisor */ 1036 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ 1037 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ 1038 uint64_t insn_flags; /* Supported instruction set */ 1039 int saarp; 1040 1041 /* Fields up to this point are cleared by a CPU reset */ 1042 struct {} end_reset_fields; 1043 1044 CPU_COMMON 1045 1046 /* Fields from here on are preserved across CPU reset. */ 1047 CPUMIPSMVPContext *mvp; 1048 #if !defined(CONFIG_USER_ONLY) 1049 CPUMIPSTLBContext *tlb; 1050 #endif 1051 1052 const mips_def_t *cpu_model; 1053 void *irq[8]; 1054 QEMUTimer *timer; /* Internal timer */ 1055 struct MIPSITUState *itu; 1056 MemoryRegion *itc_tag; /* ITC Configuration Tags */ 1057 target_ulong exception_base; /* ExceptionBase input to the core */ 1058 }; 1059 1060 /** 1061 * MIPSCPU: 1062 * @env: #CPUMIPSState 1063 * 1064 * A MIPS CPU. 1065 */ 1066 struct MIPSCPU { 1067 /*< private >*/ 1068 CPUState parent_obj; 1069 /*< public >*/ 1070 1071 CPUMIPSState env; 1072 }; 1073 1074 static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) 1075 { 1076 return container_of(env, MIPSCPU, env); 1077 } 1078 1079 #define ENV_OFFSET offsetof(MIPSCPU, env) 1080 1081 void mips_cpu_list(void); 1082 1083 #define cpu_signal_handler cpu_mips_signal_handler 1084 #define cpu_list mips_cpu_list 1085 1086 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); 1087 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); 1088 1089 /* 1090 * MMU modes definitions. We carefully match the indices with our 1091 * hflags layout. 1092 */ 1093 #define MMU_MODE0_SUFFIX _kernel 1094 #define MMU_MODE1_SUFFIX _super 1095 #define MMU_MODE2_SUFFIX _user 1096 #define MMU_MODE3_SUFFIX _error 1097 #define MMU_USER_IDX 2 1098 1099 static inline int hflags_mmu_index(uint32_t hflags) 1100 { 1101 if (hflags & MIPS_HFLAG_ERL) { 1102 return 3; /* ERL */ 1103 } else { 1104 return hflags & MIPS_HFLAG_KSU; 1105 } 1106 } 1107 1108 static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) 1109 { 1110 return hflags_mmu_index(env->hflags); 1111 } 1112 1113 typedef CPUMIPSState CPUArchState; 1114 typedef MIPSCPU ArchCPU; 1115 1116 #include "exec/cpu-all.h" 1117 1118 /* 1119 * Memory access type : 1120 * may be needed for precise access rights control and precise exceptions. 1121 */ 1122 enum { 1123 /* 1 bit to define user level / supervisor access */ 1124 ACCESS_USER = 0x00, 1125 ACCESS_SUPER = 0x01, 1126 /* 1 bit to indicate direction */ 1127 ACCESS_STORE = 0x02, 1128 /* Type of instruction that generated the access */ 1129 ACCESS_CODE = 0x10, /* Code fetch access */ 1130 ACCESS_INT = 0x20, /* Integer load/store access */ 1131 ACCESS_FLOAT = 0x30, /* floating point load/store access */ 1132 }; 1133 1134 /* Exceptions */ 1135 enum { 1136 EXCP_NONE = -1, 1137 EXCP_RESET = 0, 1138 EXCP_SRESET, 1139 EXCP_DSS, 1140 EXCP_DINT, 1141 EXCP_DDBL, 1142 EXCP_DDBS, 1143 EXCP_NMI, 1144 EXCP_MCHECK, 1145 EXCP_EXT_INTERRUPT, /* 8 */ 1146 EXCP_DFWATCH, 1147 EXCP_DIB, 1148 EXCP_IWATCH, 1149 EXCP_AdEL, 1150 EXCP_AdES, 1151 EXCP_TLBF, 1152 EXCP_IBE, 1153 EXCP_DBp, /* 16 */ 1154 EXCP_SYSCALL, 1155 EXCP_BREAK, 1156 EXCP_CpU, 1157 EXCP_RI, 1158 EXCP_OVERFLOW, 1159 EXCP_TRAP, 1160 EXCP_FPE, 1161 EXCP_DWATCH, /* 24 */ 1162 EXCP_LTLBL, 1163 EXCP_TLBL, 1164 EXCP_TLBS, 1165 EXCP_DBE, 1166 EXCP_THREAD, 1167 EXCP_MDMX, 1168 EXCP_C2E, 1169 EXCP_CACHE, /* 32 */ 1170 EXCP_DSPDIS, 1171 EXCP_MSADIS, 1172 EXCP_MSAFPE, 1173 EXCP_TLBXI, 1174 EXCP_TLBRI, 1175 1176 EXCP_LAST = EXCP_TLBRI, 1177 }; 1178 1179 /* 1180 * This is an internally generated WAKE request line. 1181 * It is driven by the CPU itself. Raised when the MT 1182 * block wants to wake a VPE from an inactive state and 1183 * cleared when VPE goes from active to inactive. 1184 */ 1185 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 1186 1187 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); 1188 1189 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU 1190 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX 1191 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU 1192 1193 bool cpu_supports_cps_smp(const char *cpu_type); 1194 bool cpu_supports_isa(const char *cpu_type, uint64_t isa); 1195 void cpu_set_exception_base(int vp_index, target_ulong address); 1196 1197 /* mips_int.c */ 1198 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); 1199 1200 /* mips_itu.c */ 1201 void itc_reconfigure(struct MIPSITUState *tag); 1202 1203 /* helper.c */ 1204 target_ulong exception_resume_pc(CPUMIPSState *env); 1205 1206 static inline void restore_snan_bit_mode(CPUMIPSState *env) 1207 { 1208 set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, 1209 &env->active_fpu.fp_status); 1210 } 1211 1212 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, 1213 target_ulong *cs_base, uint32_t *flags) 1214 { 1215 *pc = env->active_tc.PC; 1216 *cs_base = 0; 1217 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | 1218 MIPS_HFLAG_HWRENA_ULR); 1219 } 1220 1221 #endif /* MIPS_CPU_H */ 1222